Chapter 1 Merged

48 SEMICONDUCTOR COMMON CATHODE
DIODES PIN # FUNCTION

1. Anode f
2. ANODE g
3. NO PIN
1 14
a 4. COMMON CATHODE
5. NO PIN
f b 6. ANODE e
0.630" 7. ANODE d
e g c 1.0875" 8. ANODE c
9. ANODE d
d 10. NO PIN
7 8 11. NO PIN
12. COMMON CATHODE
13. ANODE b
0.803" 14. ANODE a
(a) (b)
Computer control
5V 5V5V 5V 5V
1 14
2 13
3 12
4 11
5 10
6 9
7 8
(c)
FIG. 1.54
Seven-segment display: (a) face with pin idenfication; (b) pin function; (c) displaying the numeral 5.
1.17 SUMMARY
●
Important Conclusions and Concepts
1. The characteristics of an ideal diode are a close match with those of a simple switch
except for the important fact that an ideal diode can conduct in only one direction.
2. The ideal diode is a short in the region of conduction and an open circuit in the
region of nonconduction.
3. A semiconductor is a material that has a conductivity level somewhere between that
of a good conductor and that of an insulator.
4. A bonding of atoms, strengthened by the sharing of electrons between neighboring
atoms, is called covalent bonding.
5. Increasing temperatures can cause a significant increase in the number of free elec-
trons in a semiconductor material.
6. Most semiconductor materials used in the electronics industry have negative tem-
perature coefficients; that is, the resistance drops with an increase in temperature.
7. Intrinsic materials are those semiconductors that have a very low level of impurities,
whereas extrinsic materials are semiconductors that have been exposed to a doping
process.
8. An n-type material is formed by adding donor atoms that have five valence electrons
to establish a high level of relatively free electrons. In an n-type material, the electron
is the majority carrier and the hole is the minority carrier.
9. A p-type material is formed by adding acceptor atoms with three valence electrons to
establish a high level of holes in the material. In a p-type material, the hole is the
majority carrier and the electron is the minority carrier.
10. The region near the junction of a diode that has very few carriers is called the deple-
tion region.
11. In the absence of any externally applied bias, the diode current is zero.
12. In the forward-bias region the diode current increases exponentially with increase in
voltage across the diode.
13. In the reverse-bias region the diode current is the very small reverse saturation cur- COMPUTER ANALYSIS 49
rent until Zener breakdown is reached and current will flow in the opposite direction
through the diode.
14. The reverse saturation current Is will just about double in magnitude for every 10-fold
increase in temperature.
15. The dc resistance of a diode is determined by the ratio of the diode voltage and cur-
rent at the point of interest and is not sensitive to the shape of the curve. The dc resis-
tance decreases with increase in diode current or voltage.
16. The ac resistance of a diode is sensitive to the shape of the curve in the region of inter-
est and decreases for higher levels of diode current or voltage.
17. The threshold voltage is about 0.7 V for silicon diodes and 0.3 V for germanium diodes.
18. The maximum power dissipation level of a diode is equal to the product of the diode
voltage and current.
19. The capacitance of a diode increases exponentially with increase in the forward-bias
voltage. Its lowest levels are in the reverse-bias region.
20. The direction of conduction for a Zener diode is opposite to that of the arrow in the
symbol, and the Zener voltage has a polarity opposite to that of a forward-biased diode.
21. Light emitting diodes (LEDs) emit light under forward-bias conditions but require 2
V to 4 V for good emission.
Equations
kT
ID = Is(eVD>nVT - 1) VT = TK = TC + 273⬚ k = 1.38 * 10-23 J>K
q
VK ⬵ 0.7 V (Si)
VK ⬵ 1.2 V (GaAs)
VK ⬵ 0.3 V (Ge)
VD
RD =
ID
⌬Vd 26 mV
rd = =
⌬Id ID
⌬Vd
rav = `
⌬Id pt. to pt.
PDmax = VD ID
1.18 COMPUTER ANALYSIS

●
Two software packages designed to analyze electronic circuits will be introduced and applied
throughout the text. They include Cadence OrCAD, version 16.3 (Fig. 1.55), and Multi-
sim, version 11.0.1 (Fig. 1.56). The content was written with sufficient detail to ensure that
the reader will not need to reference any other computer literature to apply both programs.
FIG. 1.55 FIG. 1.56

Cadence OrCAD Design package version 16.3. Multisim 11.0.1.
(Photo by Dan Trudden/Pearson.) (Photo by Dan Trudden/Pearson.)
50 SEMICONDUCTOR Those of you who have used either program in the past will find that the changes are minor
DIODES and appear primarily in the front end and in the generation of specific data and plots.
The reason for including two programs stems from the fact that both are used throughout
the educational community. You will find that the OrCAD software has a broader area of
investigation but the Multisim software generates displays that are a better match to the
actual laboratory experience.
The demo version of OrCAD is free from Cadence Design Systems, Inc., and can be
downloaded directly from the EMA Design Automation, Inc., web site, info@emaeda.com.
Multisim must be purchased from the National Instruments Corporation using their web
site, ni.com/multisim.
In previous editions, the OrCAD package was referred to as a PSpice program primarily
because it is a subset of a more sophisticated version used extensively in industry called
SPICE. The result is the use of the term PSpice in the descriptions to follow when initiating
an analysis using the OrCAD software.
The downloading process for each software package will now be introduced along with
the general appearance of the resulting screen.
OrCAD
Installation:
Insert the OrCAD Release 16.3 DVD into the disk drive to open the Cadence OrCAD
16.3 software screen.
Select Demo Installation and the Preparing Setup dialog box will open, followed by
the message Welcome to the Installation Wizard for OrCAD 16.3 Demo. Select
Next, and the License Agreement dialog box opens. Choose I accept and select
Next, and the Choose Destination dialog box will open with Install OrCAD 16.3
Demo Accept C:\OrCAD\OrCAD_16.3 Demo.
Select Next, and the Start Copying Files dialog box opens. Choose Select again, and
the Ready to Install Program dialog box opens. Click Install, and the Installing
Crystal Report Xii box will appear. The Setup dialog box opens with the prompt:
Setup status installs program. The Install Wizard is now installing the OrCAD
16.3 Demo.
At completion, a message will appear: Searching for and adding programs to the
Windows firewall exception list. Generating indexes for Cadence Help. This
may take some time.
When the process has completed, select Finish and the Cadence OrCAD 16.3 screen
will appear. The software has been installed.
Screen Icon: The screen icon can be established (if it does not appear automatically) by
applying the following sequence. START-All Programs-Cadence-OrCAD 16.3 Demo-
OrCAD Capture CIS Demo, followed by a right-click of the mouse to obtain a listing
where Send to is chosen, followed by Desktop (create shortcut). The OrCAD icon will
then appear on the screen and can be moved to the appropriate location.
Folder Creation: Starting with the OrCAD opening screen, right-click on the Start
option at the bottom left of the screen. Then choose Explore followed by Hard Drive
(C:). Then place the mouse on the folder listing, and a right-click will result in a listing in
which New is an option. Choose New followed by Folder, and then type in OrCAD 11.3
in the provided area of the screen, followed by a right-click of the mouse. A location for all
the files generated using OrCAD has now been established.
Multisim
Installation:
Insert the Multisim disk into the DVD disk drive to obtain the Autoplay dialog box.
Then select Always do this for software and games, followed by the selection of
Auto-run to open the NI Circuit Design Suite 11.0 dialog box.
Enter the full name to be used and provide the serial number. (The serial number PROBLEMS 51
appears in the Certificate of Ownership document that came with the NI Circuit
Design Suite packet.)
Selecting Next will result in the Destination Directory dialog box from which one will
Accept the following: C:\Program Files(X86) National Instruments\. Select Next
to open the Features dialog box and then select NI Circuit Design Suite 11.0.1
Education.
Selecting Next will result in the Product Notification dialog box with a succeeding
Next resulting in the License Agreement dialog box. A left-click of the mouse on I
accept can then be followed by choosing Next to obtain the Start Installation dialog
box. Another left-click and the installation process begins, with the progress being
displayed. The process takes between 15 and 20 minutes.
At the conclusion of the installation, you will be asked to install the NI Elvismx driver
DVD. This time Cancel will be selected, and the NI Circuit Design Suite 11.0.1
dialog box will appear with the following message: NI Circuit Design Suite 11.0.1
has been installed. Click Finish, and the response will be to restart the computer to
complete the operation. Select Restart, and the computer will shut down and start up
again, followed by the appearance of the Multisim Screen dialog box.
Select Activate and then Activate through secure Internet connection, and the Acti-
vation Wizard dialog box will open. Enter the serial number followed by Next to
enter all the information into the NI Activation Wizard dialog box. Selecting Next
will result in the option of Send me an email confirmation of this activation. Select
this option and the message Product successfully activated will appear. Selecting
Finish will complete the process.
Screen Icon: The process described for the OrCAD program will produce the same
results for Multisim.
Folder Creation: Following the procedure introduced above for the OrCAD program, a
folder labeled OrCAD 16.3 was established for the Multisim files.
The computer section of the next chapter will cover the details of opening both the
OrCAD and Multisim analysis packages, setting up a specific circuit, and generating a
variety of results.
PROBLEMS
●
*Note: Asterisks indicate more difficult problems.
1.3 Covalent Bonding and Intrinsic Materials
1. Sketch the atomic structure of copper and discuss why it is a good conductor and how its struc-
ture is different from that of germanium, silicon, and gallium arsenide.
2. In your own words, define an intrinsic material, a negative temperature coefficient, and cova-
lent bonding.
3. Consult your reference library and list three materials that have a negative temperature coeffi-
cient and three that have a positive temperature coefficient.
1.4 Energy Levels

4. a. How much energy in joules is required to move a charge of 12 mC through a difference in
potential of 6 V?
b. For part (a), find the energy in electron-volts.
5. If 48 eV of energy is required to move a charge through a potential difference of 3.2 V, deter-
mine the charge involved.
6. Consult your reference library and determine the level of Eg for GaP, ZnS, and GaAsP, three semi-
conductor materials of practical value. In addition, determine the written name for each material.
1.5 n-Type and p-Type Materials

7. Describe the difference between n-type and p-type semiconductor materials.
8. Describe the difference between donor and acceptor impurities.
9. Describe the difference between majority and minority carriers.
52 SEMICONDUCTOR 10. Sketch the atomic structure of silicon and insert an impurity of arsenic as demonstrated for
DIODES silicon in Fig. 1.7.
11. Repeat Problem 10, but insert an impurity of indium.
12. Consult your reference library and find another explanation of hole versus electron flow. Using
both descriptions, describe in your own words the process of hole conduction.
1.6 Semiconductor Diode

13. Describe in your own words the conditions established by forward- and reverse-bias conditions
on a p–n junction diode and how the resulting current is affected.
14. Describe how you will remember the forward- and reverse-bias states of the p–n junction
diode. That is, how will you remember which potential (positive or negative) is applied to
which terminal?
15. a. Determine the thermal voltage for a diode at a temperature of 20°C.
b. For the same diode of part (a), find the diode current using Eq. 1.2 if Is 40 nA, n 2 (low
value of VD), and the applied bias voltage is 0.5 V.
16. Repeat Problem 15 for T 100°C (boiling point of water). Assume that Is has increased to 5.0 mA.
17. a. Using Eq. (1.2), determine the diode current at 20°C for a silicon diode with n 2, Is
0.1 mA at a reverse-bias potential of -10 V.
b. Is the result expected? Why?
18. Given a diode current of 8 mA and n 1, find Is if the applied voltage is 0.5 V and the tem-
perature is room temperature (25°C).
*19. Given a diode current of 6 mA, VT 26 mV, n 1, and Is 1 nA, find the applied voltage VD.
20. a. Plot the function y = ex for x from 0 to 10. Why is it difficult to plot?
b. What is the value of y = ex at x 0?
c. Based on the results of part (b), why is the factor 1 important in Eq. (1.2)?
21. In the reverse-bias region the saturation current of a silicon diode is about 0.1 mA (T 20°C).
Determine its approximate value if the temperature is increased 40°C.
22. Compare the characteristics of a silicon and a germanium diode and determine which you would
prefer to use for most practical applications. Give some details. Refer to a manufacturer’s listing
and compare the characteristics of a germanium and a silicon diode of similar maximum ratings.
23. Determine the forward voltage drop across the diode whose characteristics appear in Fig. 1.19 at
temperatures of 75°C, 25°C, 125°C and a current of 10 mA. For each temperature, determine the
level of saturation current. Compare the extremes of each and comment on the ratio of the two.
1.7 Ideal versus Practical

24. Describe in your own words the meaning of the word ideal as applied to a device or a system.
25. Describe in your own words the characteristics of the ideal diode and how they determine the
on and off states of the device. That is, describe why the short-circuit and open-circuit equiva-
lents are appropriate.
26. What is the one important difference between the characteristics of a simple switch and those
of an ideal diode?
1.8 Resistance Levels

27. Determine the static or dc resistance of the commercially available diode of Fig. 1.15 at a for-
ward current of 4 mA.
28. Repeat Problem 27 at a forward current of 15 mA and compare results.
29. Determine the static or dc resistance of the commercially available diode of Fig. 1.15 at a reverse
voltage of 10 V. How does it compare to the value determined at a reverse voltage of 30 V?
30. Calculate the dc and ac resistances for the diode of Fig. 1.15 at a forward current of 10 mA and
compare their magnitudes.
31. a. Determine the dynamic (ac) resistance of the commercially available diode of Fig. 1.15 at a
forward current of 10 mA using Eq. (1.5).
b. Determine the dynamic (ac) resistance of the diode of Fig. 1.15 at a forward current of 10 mA
using Eq. (1.6).
c. Compare solutions of parts (a) and (b).
32. Using Eq. (1.5), determine the ac resistance at a current of 1 mA and 15 mA for the diode of
Fig. 1.15. Compare the solutions and develop a general conclusion regarding the ac resistance
and increasing levels of diode current.
33. Using Eq. (1.6), determine the ac resistance at a current of 1 mA and 15 mA for the diode of PROBLEMS 53
Fig. 1.15. Modify the equation as necessary for low levels of diode current. Compare to the
solutions obtained in Problem 32.
34. Determine the average ac resistance for the diode of Fig. 1.15 for the region between 0.6 V
and 0.9 V.
35. Determine the ac resistance for the diode of Fig. 1.15 at 0.75 V and compare it to the average
ac resistance obtained in Problem 34.
1.9 Diode Equivalent Circuits

36. Find the piecewise-linear equivalent circuit for the diode of Fig. 1.15. Use a straight-line seg-
ment that intersects the horizontal axis at 0.7 V and best approximates the curve for the region
greater than 0.7 V.
37. Repeat Problem 36 for the diode of Fig. 1.27.
38. Find the piecewise-linear equivalent circuit for the germanium and gallium arsenide diodes of
Fig. 1.18.
1.10 Transition and Diffusion Capacitance

*39. a. Referring to Fig. 1.33, determine the transition capacitance at reverse-bias potentials of
25 V and 10 V. What is the ratio of the change in capacitance to the change in voltage?
b. Repeat part (a) for reverse-bias potentials of 10 V and 1 V. Determine the ratio of the
change in capacitance to the change in voltage.
c. How do the ratios determined in parts (a) and (b) compare? What does this tell you about
which range may have more areas of practical application?
40. Referring to Fig. 1.33, determine the diffusion capacitance at 0 V and 0.25 V.
41. Describe in your own words how diffusion and transition capacitances differ.
42. Determine the reactance offered by a diode described by the characteristics of Fig. 1.33 at a
forward potential of 0.2 V and a reverse potential of 20 V if the applied frequency is 6 MHz.
43. The no-bias transition capacitance of a silicon diode is 8 pF with VK 0.7 V and n 1>2.
What is the transition capacitance if the applied reverse bias potential is 5 V?
44. Find the applied reverse bias potential if the transition capacitance of a silicon diode is 4 pF but
the no-bias level is 10 pF with n 1>3 and VK 0.7 V.
1.11 Reverse Recovery Time

45. Sketch the waveform for i of the network of Fig. 1.57 if tt = 2ts and the total reverse recovery
time is 9 ns.
FIG. 1.57
Problem 45.
1.12 Diode Specification Sheets

*46. Plot IF versus VF using linear scales for the diode of Fig. 1.37. Note that the provided graph
employs a log scale for the vertical axis (log scales are covered in Sections 9.2 and 9.3).
47. a. Comment on the change in capacitance level with increase in reverse-bias potential for the
diode of Fig. 1.37.
b. What is the level of C(0)?
c. Using VK 0.7 V, find the level of n in Eq. 1.9.
48. Does the reverse saturation current of the diode of Fig. 1.37 change significantly in magnitude
for reverse-bias potentials in the range 25 V to 100 V?
54 SEMICONDUCTOR *49. For the diode of Fig. 1.37 determine the level of IR at room temperature (25°C) and the boiling
DIODES point of water (100°C). Is the change significant? Does the level just about double for every
10°C increase in temperature?
50. For the diode of Fig. 1.37, determine the maximum ac (dynamic) resistance at a forward cur-
rent of 0.1, 1.5, and 20 mA. Compare levels and comment on whether the results support con-
clusions derived in earlier sections of this chapter.
51. Using the characteristics of Fig. 1.37, determine the maximum power dissipation levels for the
diode at room temperature (25°C) and 100°C. Assuming that VF remains fixed at 0.7 V, how
has the maximum level of IF changed between the two temperature levels?
52. Using the characteristics of Fig. 1.37, determine the temperature at which the diode current
will be 50% of its value at room temperature (25°C).
1.15 Zener Diodes

53. The following characteristics are specified for a particular Zener diode: VZ 29 V, VR 16.8 V,
IZT 10 mA, IR 20 mA, and IZM 40 mA. Sketch the characteristic curve in the manner
displayed in Fig. 1.47.
*54. At what temperature will the 10-V Zener diode of Fig. 1.47 have a nominal voltage of 10.75 V?
(Hint: Note the data in Table 1.7.)
55. Determine the temperature coefficient of a 5-V Zener diode (rated 25°C value) if the nominal
voltage drops to 4.8 V at a temperature of 100°C.
56. Using the curves of Fig. 1.48a, what level of temperature coefficient would you expect for a
20-V diode? Repeat for a 5-V diode. Assume a linear scale between nominal voltage levels and
a current level of 0.1 mA.
57. Determine the dynamic impedance for the 24-V diode at IZ = 10 mA for Fig. 1.48b. Note that
it is a log scale.
*58. Compare the levels of dynamic impedance for the 24-V diode of Fig. 1.48b at current levels of
0.2, 1, and 10 mA. How do the results relate to the shape of the characteristics in this region?
1.16 Light-Emitting Diodes

59. Referring to Fig. 1.52e, what would appear to be an appropriate value of VK for this device?
How does it compare to the value of VK for silicon and germanium?
60. Given that Eg 0.67 eV for germanium, find the wavelength of peak solar response for the
material. Do the photons at this wavelength have a lower or higher energy level?
61. Using the information provided in Fig. 1.52, determine the forward voltage across the diode if
the relative luminous intensity is l.5.
*62. a. What is the percentage increase in relative efficiency of the device of Fig. 1.52 if the peak
current is increased from 5 mA to 10 mA?
b. Repeat part (a) for 30 mA to 35 mA (the same increase in current).
c. Compare the percentage increase from parts (a) and (b). At what point on the curve would
you say there is little to be gained by further increasing the peak current?
63. a. If the luminous intensity at 0° angular displacement is 3.0 mcd for the device of Fig. 1.52,
at what angle will it be 0.75 mcd?
b. At what angle does the loss of luminous intensity drop below the 50% level?
*64. Sketch the current derating curve for the average forward current of the high-efficiency red
LED of Fig. 1.52 as determined by temperature. (Note the absolute maximum ratings.)
a small blue box around it and produce a dialog box for the change. For the source, a dia- PROBLEMS 119
log box labeled DC_POWER will result, in which the heading Label is selected and the
refDEs retyped as E. Click OK and the label E will appear. The same procedure can change
the value to 20 V, although in this case the Value heading is chosen and the units are chosen
using the scroll at the right of the entered value.
The next step is to determine what quantities are to be measured and how to measure
them. For this network a multimeter will be used to measure the current through the resistor
R1. The multimeter is found at the top of the Instrument toolbar. After selection it can be
placed on the screen in the same manner as the other elements. Double-clicking the meter
will then result in the Multimeter-XXM1 dialog box, in which A is selected to set the mul-
timeter as an ammeter. In addition, the DC box (a straight line) must be selected because
we are dealing with dc voltages. The current through the diode D1 and the voltage across
the resistor R2 will be found using Indicators, which are found as the tenth option to the
right on the Component toolbar. The software symbol looks like an LED with a red dashed
figure eight inside. Click on this option and a Select a Component dialog box will appear.
Under Family, select AMMETER and then take note of the Component listing and the
four options for the orientation of the indicator. For our analysis the AMMETER_H will
be chosen since the plus sign or entering point for the current is on the left for the diode
D1. Click OK and the indicator can be placed to the left of the diode D1. For the voltage
across the resistor R2, the option VOLTMETER_HR is chosen so the polarity matches
that across the resistor.
Finally, all the components and meters must be connected. This is accomplished by
simply placing the cursor at the end of an element until a small circle and a set of crosshairs
appear to designate the starting point. Once these are in place, click the location and an x
will appear at the terminal. Then move to the end of the other element and left-click the
mouse again—a red connecting wire will automatically appear with the most direct route
between the two elements. The process is called Automatic Wiring.
Now that all the components are in place it is time to initiate the analysis of the circuit,
an operation that can be performed in one of three ways. One option is to select Simulate
at the head of the screen followed by Run. The next is the green arrow in the Simulation
toolbar. The last is to simply toggle the switch at the head of the screen to the 1 position. In
each case a solution appears in the indicators after a few seconds that seems to flicker over
time. This flickering simply indicates the software package is repeating the analysis over
time. To accept the solution and stop the continuing simulation, either toggle the switch to
the 0 position or select the lightning bolt keypad again.
The current through the diode is 3.349 mA, which compares well with the 3.32 mA in
Example 2.13. The voltage across the resistor R2 is 18.722 V, which is close to the 18.6 V
of the same example. After the simulation, the multimeter can be displayed as shown in
Fig. 2.151 by double-clicking on the meter symbol. By clicking anywhere on the meter, the
top portion is dark blue, and the meter can be moved to any location by simply clicking on
the blue region and dragging it to the desired location. The current of 193.285 mA is very
close to the 212 mA of Example 2.13. The differences are primarily due to the fact that each
diode voltage is assumed to be 0.7 V, whereas in fact it is different for each diode of Fig.
2.151 since the current through each is different. In all, however, the Multisim solution is
a very close match with the approximate solution of Example 2.13.
PROBLEMS
●
2.2 Load-Line Analysis
1. a. Using the characteristics of Fig. 2.152b, determine ID, VD, and VR for the circuit of Fig. 2.152a.
b. Repeat part (a) using the approximate model for the diode, and compare results.
c. Repeat part (a) using the ideal model for the diode, and compare results.
2. a. Using the characteristics of Fig. 2.152b, determine ID and VD for the circuit of Fig. 2.153.
b. Repeat part (a) with R = 0.47 k.
c. Repeat part (a) with R = 0.68 k.
d. Is the level of VD relatively close to 0.7 V in each case?
How do the resulting levels of ID compare? Comment accordingly.
120 DIODE APPLICATIONS + VD –
Si
ID
+
+
E 12 V R 0.75 k⍀ VR
–
–
(a)
ID (mA)
30
25
20
15
10
0 1 2 3 4 5 6 7 8 9 10 11 12 VD (V)
0.7 V
(b)
FIG. 2.152
Problems 1 and 2.
3. Determine the value of R for the circuit of Fig. 2.153 that will result in a diode current of
10 mA if E 7 V. Use the characteristics of Fig. 2.152b for the diode.
4. a. Using the approximate characteristics for the Si diode, determine VD, ID, and VR for the
circuit of Fig. 2.154.
b. Perform the same analysis as part (a) using the ideal model for the diode.
c. Do the results obtained in parts (a) and (b) suggest that the ideal model can provide a good
approximation for the actual response under some conditions?
+ VD –
+ VD –
ID Si
ID Si + +
+ +
E E 30 V R 1.5 k⍀ VR
6V R 0.2 k⍀ VR –
– – –
FIG. 2.153 FIG. 2.154

Problems 2 and 3. Problem 4.
2.3 Series Diode Configurations PROBLEMS 121
5. Determine the current I for each of the configurations of Fig. 2.155 using the approximate
equivalent model for the diode.
–
+
I
+ –
(a)
(b) (c)
FIG. 2.155
Problem 5.
6. Determine Vo and ID for the networks of Fig. 2.156.
ID
Vo Vo
ID
–6 V
(a) (b)
FIG. 2.156
Problems 6 and 49.
*7. Determine the level of Vo for each network of Fig. 2.157.
12 V
10 k⍀
10 V
(a) (b)
FIG. 2.157
Problem 7.
*8. Determine Vo and ID for the networks of Fig. 2.158.
Vo
2.2 k⍀
–20 V
(a) (b)
FIG. 2.158
Problem 8.
122 DIODE APPLICATIONS *9. Determine Vo1 and Vo2 for the networks of Fig. 2.159.
GaAs kΩ
(a) (b)
FIG. 2.159
Problem 9.
2.4 Parallel and Series–Parallel Configurations

10. Determine Vo and ID for the networks of Fig. 2.160.
20 V
12 V
Ge
GaAs
4V
(a) (b)
FIG. 2.160
Problems 10 and 50.
*11. Determine Vo and I for the networks of Fig. 2.161.
1V
GaAs
–4 V
(a) (b)
FIG. 2.161
Problem 11.
12. Determine Vo1, Vo2, and I for the network of Fig. 2.162.
*13. Determine Vo and ID for the network of Fig. 2.163.
PROBLEMS 123
+
Si
– GaAs
FIG. 2.162 FIG. 2.163

Problem 12. Problems 13 and 51.
2.5 AND/OR Gates

14. Determine Vo for the network of Fig. 2.39 with 0 V on both inputs.
18. Determine Vo for the negative logic OR gate of Fig. 2.164.
19. Determine Vo for the negative logic AND gate of Fig. 2.165.
–5 V –5 V
Si Si
0V 0V
Vo Vo
Si Si
1 kΩ 2.2 kΩ
–5 V
FIG. 2.164 FIG. 2.165

Problem 18. Problem 19.
20. Determine the level of Vo for the gate of Fig. 2.166.

21. Determine Vo for the configuration of Fig. 2.167.
FIG. 2.166 FIG. 2.167

2.6 Sinusoidal Inputs; Half-Wave Rectification

22. Assuming an ideal diode, sketch vi, vd, and id for the half-wave rectifier of Fig. 2.168. The
input is a sinusoidal waveform with a frequency of 60 Hz. Determine the profit value of vi from
the given dc level.
23. Repeat Problem 22 with a silicon diode (VK 0.7 V).
24. Repeat Problem 22 with a 10 k load applied as shown in Fig. 2.169. Sketch vL and iL.
124 DIODE APPLICATIONS id + vd – Vdc = 2 V
Ideal
Ideal vi iL
Vdc = 2 V
+ + vd
– id +
vi 2 kΩ 2 k⍀ RL 10 k⍀ vL
– –
FIG. 2.168 FIG. 2.169

Problems 22 through 24. Problem 24.
25. For the network of Fig. 2.170, sketch vo and determine Vdc.
*26. For the network of Fig. 2.171, sketch vo and iR.
vi iR
2 kΩ
10 V
1 kΩ
+ +
2 0 t vi Si 1 kΩ vo
–10 V – –
FIG. 2.170 FIG. 2.171

*27. a. Given Pmax = 14 mW for each diode at Fig. 2.172, determine the maximum current rating
of each diode (using the approximate equivalent model).
b. Determine Imax for the parallel diodes.
c. Determine the current through each diode at Vimax using the results of part (b).
d. If only one diode were present, which would be the expected result?
vi Imax
Si
160 V
+
0 t vi Si 4.7 kΩ 68 kΩ
FIG. 2.172
Problem 27.
2.7 Full-Wave Rectification

28. A full-wave bridge rectifier with a 120-V rms sinusoidal input has a load resistor of 1 k.
a. If silicon diodes are employed, what is the dc voltage available at the load?
b. Determine the required PIV rating of each diode.
c. Find the maximum current through each diode during conduction.
d. What is the required power rating of each diode?
29. Determine vo and the required PIV rating of each diode for the configuration of Fig. 2.173. In
addition, determine the maximum current through each diode.
vi
+
100 V
vi Ideal diodes vo
t +
–100 V
2.2 kΩ
–
–
FIG. 2.173
Problem 29.
*30. Sketch vo for the network of Fig. 2.174 and determine the dc voltage available. PROBLEMS 125
vi
+
100 V
Ideal diodes
vi vo
t +
–100 V
2.2 kΩ 2.2 kΩ 2.2 kΩ
–
–
FIG. 2.174
Problem 30.
*31. Sketch vo for the network of Fig. 2.175 and determine the dc voltage available.
vi
+
170 V Ideal 2.2 kΩ
diodes
– vo +
vi
t
2.2 kΩ
–170 V
2.2 kΩ
–
FIG. 2.175
Problem 31.
2.8 Clippers
32. Determine vo for each network of Fig. 2.176 for the input shown.
8V
+ –
100 kΩ 2 kΩ
FIG. 2.176
Problem 32.
33. Determine vo for each network of Fig. 2.177 for the input shown.
4V
12 V vo
vo
– +
1.8 kΩ 10 kΩ
–12 V
(a) (b)
FIG. 2.177
Problem 33.
126 DIODE APPLICATIONS *34. Determine vo for each network of Fig. 2.178 for the input shown.
– 4 V + Ideal
+ +
vi 1 kΩ vo
– –
(a) (b)
FIG. 2.178
Problem 34.
*35. Determine vo for each network of Fig. 2.179 for the input shown.
3V
1 kΩ
+ –
Si
+
4V
–
(a) (b)
FIG. 2.179
Problem 35.
36. Sketch iR and vo for the network of Fig. 2.180 for the input shown.
+ –
5.3 V 7.3 V
– +
FIG. 2.180
Problem 36.
2.9 Clampers
37. Sketch vo for each network of Fig. 2.181 for the input shown.
–
+
(a) (b)
FIG. 2.181
Problem 37.
38. Sketch vo for each network of Fig. 2.182 for the input shown. PROBLEMS 127
Ideal
Ideal +
E
–
(a) (b)
FIG. 2.182
Problem 38.
*39. For the network of Fig. 2.183:

a. Calculate 5t.
b. Compare 5t to half the period of the applied signal.
c. Sketch vo.
12 V
–12 V +
FIG. 2.183
Problem 39.
*40. Design a clamper to perform the function indicated in Fig. 2.184.
FIG. 2.184
Problem 40.
*41. Design a clamper to perform the function indicated in Fig. 2.185.
Design
FIG. 2.185
Problem 41.
128 DIODE APPLICATIONS 2.10 Zener Diodes
*42. a. Determine VL, IL, IZ, and IR for the network of Fig. 2.186 if RL 180 .
b. Repeat part (a) if RL 470 .
c. Determine the value of RL that will establish maximum power conditions for the Zener diode.
d. Determine the minimum value of RL to ensure that the Zener diode is in the “on” state.
VZ = 10 V
PZ max = 400 mW
FIG. 2.186
Problem 42.
*43. a. Design the network of Fig. 2.187 to maintain VL at 12 V for a load variation (IL) from 0 mA
to 200 mA. That is, determine RS and VZ.
b. Determine PZ max for the Zener diode of part (a).
*44. For the network of Fig. 2.188, determine the range of Vi that will maintain VL at 8 V and not
exceed the maximum power rating of the Zener diode.
VZ
FIG. 2.187 FIG. 2.188

45. Design a voltage regulator that will maintain an output voltage of 20 V across a 1-k load with
an input that will vary between 30 V and 50 V. That is, determine the proper value of RS and
the maximum current IZM.
46. Sketch the output of the network of Fig. 2.145 if the input is a 50-V square wave. Repeat for a
5-V square wave.
2.11 Voltage-Multiplier Circuits

47. Determine the voltage available from the voltage doubler of Fig. 2.123 if the secondary voltage
of the transformer is 120 V (rms).
48. Determine the required PIV ratings of the diodes of Fig. 2.123 in terms of the peak secondary
voltage Vm.
2.14 Computer Analysis
49. Perform an analysis of the network of Fig. 2.156b using PSpice Windows.
50. Perform an analysis of the network of Fig. 2.161b using PSpice Windows.
51. Perform an analysis of the network of Fig. 2.162 using PSpice Windows.
52. Perform a general analysis of the Zener network of Fig. 2.188 using PSpice Windows.
53. Repeat Problem 49 using Multisim.
PROBLEMS 157
IB = 80 ␮A
IC
IB = 60 ␮A
IB = 40 ␮A
IB = 20 ␮A
VCE
FIG. 3.36
Ideal collector characteristics for the transistor of Fig. 3.34.
PROBLEMS
●
3.2 Transistor Construction
1. What names are applied to the two types of BJT transistors? Sketch the basic construction of
each and label the various minority and majority carriers in each. Draw the graphic symbol next
to each. Is any of this information altered by changing from a silicon to a germanium base?
2. What is the major difference between a bipolar and a unipolar device?
3.3 Transistor Operation

3. How must the two transistor junctions be biased for proper transistor amplifier operation?
4. What is the source of the leakage current in a transistor?
5. Sketch a figure similar to Fig. 3.4a for the forward-biased junction of an npn transistor.
Describe the resulting carrier motion.
6. Sketch a figure similar to Fig. 3.4b for the reverse-biased junction of an npn transistor. Describe
the resulting carrier motion.
7. Sketch a figure similar to Fig. 3.5 for the majority- and minority-carrier flow of an npn transis-
tor. Describe the resulting carrier motion.
8. Which of the transistor currents is always the largest? Which is always the smallest? Which
two currents are relatively close in magnitude?
9. If the emitter current of a transistor is 8 mA and IB is 1兾100 of IC, determine the levels of IC and IB.
3.4 Common-Base Configuration
10. From memory, sketch the transistor symbol for a pnp and an npn transistor, and then insert the
conventional flow direction for each current.
11. Using the characteristics of Fig. 3.7, determine VBE at IE 5 mA for VCB 1, 10, and 20 V. Is
it reasonable to assume on an approximate basis that VCB has only a slight effect on the rela-
tionship between VBE and IE?
158 BIPOLAR JUNCTION 12. a. Determine the average ac resistance for the characteristics of Fig. 3.10b.
TRANSISTORS b. For networks in which the magnitude of the resistive elements is typically in kilohms, is the
approximation of Fig. 3.10c a valid one [based on the results of part (a)]?
13. a. Using the characteristics of Fig. 3.8, determine the resulting collector current if IE 3.5 mA
and VCB 10 V.
b. Repeat part (a) for IE 3.5 mA and VCB 20 V.
c. How have the changes in VCB affected the resulting level of IC?
d. On an approximate basis, how are IE and IC related based on the results above?
14. a. Using the characteristics of Figs. 3.7 and 3.8, determine IC if VCB = 5 V and VBE 0.7 V.
b. Determine VBE if IC 5 mA and VCB 15 V.
c. Repeat part (b) using the characteristics of Fig. 3.10b.
d. Repeat part (b) using the characteristics of Fig. 3.10c.
e. Compare the solutions for VBE for parts (b) through (d). Can the difference be ignored if
voltage levels greater than a few volts are typically encountered?
15. a. Given an adc of 0.998, determine IC if IE 4 mA.
b. Determine adc if IE 2.8 mA, IC 2.75 mA and ICBO 0.1 mA.
16. From memory only, sketch the common-base BJT transistor configuration (for npn and pnp)
and indicate the polarity of the applied bias and resulting current directions.
3.5 Common-Emitter Configuration

17. Define ICBO and ICEO. How are they different? How are they related? Are they typically close
in magnitude?
18. Using the characteristics of Fig. 3.13:
a. Find the value of IC corresponding to VBE 750 mV and VCE 4 V.
b. Find the value of VCE and VBE corresponding to IC 3.5 mA and IB 30 mA.
*19. a. For the common-emitter characteristics of Fig. 3.13, find the dc beta at an operating point
of VCE 6 V and IC 2 mA.
b. Find the value of a corresponding to this operating point.
c. At VCE 6 V, find the corresponding value of ICEO.
d. Calculate the approximate value of ICBO using the dc beta value obtained in part (a).
*20. a. Using the characteristics of Fig. 3.13a, determine ICEO at VCE 10 V.
b. Determine bdc at IB 10 mA and VCE 10 V.
c. Using the bdc determined in part (b), calculate ICBO.
21. a. Using the characteristics of Fig. 3.13a, determine bdc at IB 60 mA and VCE 4 V.
b. Repeat part (a) at IB 30 mA and VCE 7 V.
c. Repeat part (a) at IB 10 mA and VCE 10 V.
d. Reviewing the results of parts (a) through (c), does the value of bdc change from point to point
on the characteristics? Where were the higher values found? Can you develop any general con-
clusions about the value of bdc on a set of characteristics such as those provided in Fig. 3.13a?
*22. a. Using the characteristics of Fig. 3.13a, determine bac at IB 60 mA and VCE 4 V.
b. Repeat part (a) at IB 30 mA and VCE 7 V.
c. Repeat part (a) at IB 10 mA and VCE 10 V.
d. Reviewing the results of parts (a) through (c), does the value of bac change from point to
point on the characteristics? Where are the high values located? Can you develop any gen-
eral conclusions about the value of bac on a set of collector characteristics?
e. The chosen points in this exercise are the same as those employed in Problem 21. If Prob-
lem 21 was performed, compare the levels of bdc and bac for each point and comment on
the trend in magnitude for each quantity.
23. Using the characteristics of Fig. 3.13a, determine bdc at IB 25 mA and VCE 10 V. Then
calculate adc and the resulting level of IE. (Use the level of IC determined by IC = bdcIB.)
24. a. Given that adc = 0.980, determine the corresponding value of bdc.
b. Given bdc = 120, determine the corresponding value of a.
c. Given that bdc = 120 and IC 2.0 mA, find IE and IB.
25. From memory only, sketch the common-emitter configuration (for npn and pnp) and insert the
proper biasing arrangement with the resulting current directions for IB, IC, and IE.
3.6 Common-Collector Configuration

26. An input voltage of 2 V rms (measured from base to ground) is applied to the circuit of Fig. 3.21.
Assuming that the emitter voltage follows the base voltage exactly and that Vbe (rms) 0.1 V,
calculate the circuit voltage amplification (Av = Vo >Vi) and emitter current for RE 1 k.
27. For a transistor having the characteristics of Fig. 3.13, sketch the input and output characteris- PROBLEMS 159
tics of the common-collector configuration.
3.7 Limits of Operation

28. Determine the region of operation for a transistor having the characteristics of Fig. 3.13 if
ICmax = 6 mA, BVCEO 15 V, and PCmax = 35 mW.
29. Determine the region of operation for a transistor having the characteristics of Fig. 3.8 if
ICmax = 7 mA, BVCBO 20 V, and PCmax = 42 mW.
3.8 Transistor Specification Sheet
30. Referring to Fig. 3.23, determine the temperature range for the device in degrees Fahrenheit.
31. Using the information provided in Fig. 3.23 regarding PDmax, VCEmax, ICmax and VCEsat, sketch the
boundaries of operation for the device.
32. Based on the data of Fig. 3.23, what is the expected value of ICEO using the average value of bdc?
33. How does the range of hFE (Fig. 3.23c, normalized from hFE = 100) compare with the range
of hfe (Fig. 3.23b) for the range of IC from 0.1 to 10 mA?
34. Using the characteristics of Fig. 3.23d, determine whether the input capacitance in the common-
base configuration increases or decreases with increasing levels of reverse-bias potential. Can
you explain why?
*35. Using the characteristics of Fig. 3.23b, determine how much the level of hfe has changed from
its value at 1 mA to its value at 10 mA. Note that the vertical scale is a log scale that may require
reference to Section 11.2. Is the change one that should be considered in a design situation?
*36. Using the characteristics of Fig. 3.23c, determine the level of bdc at IC 10 mA at the three
levels of temperature appearing in the figure. Is the change significant for the specified tem-
perature range? Is it an element to be concerned about in the design process?
3.9 Transistor Testing

37. a. Using the characteristics of Fig. 3.24, determine bac at IC 14 mA and VCE 3 V.
b. Determine bdc at IC 1 mA and VCE 8 V.
c. Determine bac at IC 14 mA and VCE 3 V.
d. Determine bdc at IC 1 mA and VCE 8 V.
e. How does the level of bac and bdc compare in each region?
f. Is the approximation bdc ⬵ bac a valid one for this set of characteristics?
the 4.7-V Zener and the transistor and establish a collector current through the LED suffi- SUMMARY 233
cient in magnitude to turn on the green LED.
Once the potentiometer is set, the LED will emit its green light as long as the supply
voltage is near 9 V. However, if the terminal voltage of the 9-V battery should decrease,
the voltage set up by the voltage-divider network may drop to 5 V from 5.4 V. At 5 V there
is insufficient voltage to turn on both the Zener and the transistor, and the transistor will be
in the “off” state. The LED will immediately turn off, revealing that the supply voltage has
dropped below 9 V or that the power source has been disconnected.
9V
1 k⍀
1 k⍀
Green LED
4.7 V
+ –
10 k⍀ +
+ 0.7 V
5.4 V
–
–
FIG. 4.112
Voltage level indicator.
4.20 SUMMARY
●
Important Conclusions and Concepts
1. No matter what type of configuration a transistor is used in, the basic relationships
between the currents are always the same, and the base-to-emitter voltage is the
threshold value if the transistor is in the “on” state.
2. The operating point defines where the transistor will operate on its characteristic
curves under dc conditions. For linear (minimum distortion) amplification, the dc
operating point should not be too close to the maximum power, voltage, or current
rating and should avoid the regions of saturation and cutoff.
3. For most configurations the dc analysis begins with a determination of the base current.
4. For the dc analysis of a transistor network, all capacitors are replaced by an open-
circuit equivalent.
5. The fixed-bias configuration is the simplest of transistor biasing arrangements, but it
is also quite unstable due its sensitivity to beta at the operating point.
6. Determining the saturation (maximum) collector current for any configuration can
usually be done quite easily if an imaginary short circuit is superimposed between
the collector and emitter terminals of the transistor. The resulting current through the
short is then the saturation current.
7. The equation for the load line of a transistor network can be found by applying
Kirchhoff’s voltage law to the output or collector network. The Q-point is then deter-
mined by finding the intersection between the base current and the load line drawn on
the device characteristics.
8. The emitter-stabilized biasing arrangement is less sensitive to changes in beta—
providing more stability for the network. Keep in mind, however, that any resistance
in the emitter leg is “seen” at the base of the transistor as a much larger resistor, a
fact that will reduce the base current of the configuration.
9. The voltage-divider bias configuration is probably the most common of all the con-
figurations. Its popularity is due primarily to its low sensitivity to changes in beta
from one transistor to another of the same lot (with the same transistor label). The
exact analysis can be applied to any configuration, but the approximate one can be
applied only if the reflected emitter resistance as seen at the base is much larger than
the lower resistor of the voltage-divider bias arrangement connected to the base of the
transistor.
234 DC BIASING—BJTs 10. When analyzing the dc bias with a voltage feedback configuration, be sure to
remember that both the emitter resistor and the collector resistor are reflected
back to the base circuit by beta. The least sensitivity to beta is obtained when the
reflected resistance is much larger than the feedback resistor between the base and
the collector.
11. For the common-base configuration the emitter current is normally determined
first due to the presence of the base-to-emitter junction in the same loop. Then the fact
that the emitter and the collector currents are essentially of the same magnitude is
employed.
12. A clear understanding of the procedure employed to analyze a dc transistor network
will usually permit a design of the same configuration with a minimum of difficulty
and confusion. Simply start with those relationships that minimize the number of
unknowns and then proceed to make some decisions about the unknown elements of
the network.
13. In a switching configuration, a transistor quickly moves between saturation and cut-
off, or vice versa. Essentially, the impedance between collector and emitter can be
approximated as a short circuit for saturation and an open circuit for cutoff.
14. When checking the operation of a dc transistor network, first check that the base-to-
emitter voltage is very close to 0.7 V and that the collector-to-emitter voltage is
between 25% and 75% of the applied voltage VCC.
15. The analysis of pnp configurations is exactly the same as that applied to npn transis-
tors with the exception that current directions will reverse and voltages will have the
opposite polarities.
16. Beta is very sensitive to temperature, and VBE decreases about 2.5 mV (0.0025 V)
for each 1 increase in temperature on a Celsius scale. The reverse saturation current
typically doubles for every 10° increase in Celsius temperature.
17. Keep in mind that networks that are the most stable and least sensitive to temperature
changes have the smallest stability factors.
Equations
VBE ⬵ 0.7 V, IE = (b + 1)IB ⬵ IC, IC = bIB
Fixed bias:
VCC - VBE
IB = , IC = bIB
RB
Emitter stabilized:
VCC - VBE
IB = , Ri = (b + 1)RE
RB + (b + 1)RE
Voltage-divider bias:
R2VCC ETh - VBE
Exact: RTh = R1 } R2, ETh = VR2 = , IB =
R1 + R2 RTh + (b + 1)RE
Approximate: Test bRE Ú 10R2
R2VCC VE
VB = , VE = VB - VBE, IE = ⬵ IC
R1 + R2 RE
DC bias with voltage feedback:
VCC - VBE
IB = , IC ⬵ IC ⬵ IE
RB + b(RC + RE)
Common base:
VEE - VBE
IE = , IC ⬵ IE
RE
Transistor switching networks:
VCC ICsat VCEsat
ICsat = , IB 7 , Rsat = , ton = tr + td, toff = ts + tf
RC bdc ICsat
Stability factors: COMPUTER ANALYSIS 235
IC IC IC
S(ICO) = , S(VBE) = , S(b) =
ICO VBE b
S(ICO):
Fixed bias: S(ICO) ⬵ b
b(1 + RB>RE)*
Emitter bias: S(ICO) =
b + RB>RE
*Voltage-divider bias: Change RB to RTh in above equation.
*Feedback bias: Change RE to RC in above equation.
S(VBE):
b
Fixed bias: S(VBE) = -
RB
-b>RE-
Emitter bias: S(VBE) =
b + RB>RE
†
Voltage-divider bias: Change RB to RTh in above equation.
†
Feedback bias: Change RE to RC in above equation.
S(b):
IC1
Fixed bias: S(b) =
b1
IC1(1 + RB>RE)[
Emitter bias: S(b) =
b1(1 + b2 + RB>RE)
‡
Voltage-divider bias: Change RB to RTh in above equation.
‡
Feedback bias: Change RE to RC in above equation.
4.21 COMPUTER ANALYSIS

●
Cadence OrCAD
Voltage-Divider Configuration The results of Example 4.8 will now be verified using
Cadence OrCAD. Using methods described in detail in the previous chapters, we can con-
struct the network of Fig. 4.113. Recall from the previous chapter that the transistor is
found under the EVAL library, the dc source under the SOURCE library, and the resistors
under the ANALOG library. The capacitor has not been called up earlier but can also be
found in the ANALOG library. For the transistor, the list of available transistors can be
found in the EVAL library.
The value of beta is changed to 140 to match Example 4.8 by first clicking on the
transistor symbol on the screen. It will then appear boxed in red to reveal it is in an active
status. Then proceed with Edit-PSpice Model, and the PSpice Model Editor Demo dialog
box will appear in which Bf can be changed to 140. As you try to leave the dialog box the
Model Editor/16.3 dialog box will appear asking if you want to save the changes in the
network library. Once they are saved, the screen will automatically return with beta set at
its new value.
The analysis can then proceed by selecting the New simulation profile key (looks like
a printout with an asterisk in the top left corner) to obtain the New Simulation dialog box.
Insert Fig. 4.113 and select Create. The Simulation Settings dialog box will appear in
which Bias Point is selected under the Analysis Type heading. An OK, and the system is
ready for simulation.
Proceed by selecting the Run PSpice key (white arrow in green background) or the se-
quence PSpice–Run. The bias voltages will appear as shown in Fig. 4.113 if the V option
selected. The collector-to-emitter voltage is 13.19 V 1.333 V 11.857 V versus 12.22 V
of Example 4.8. The difference is primarily due to the fact that we are using an actual
transistor whose parameters are very sensitive to the operating conditions. Also recall the
difference in beta from the specification value and the value obtained from the plot of the
previous chapter.
236 DC BIASING—BJTs
FIG. 4.113 FIG. 4.114

Applying PSpice Windows to the voltage- Response obtained after changing b from 140
divider configuration of Example 4.8. to 255.9 for the network of Fig. 4.113.
Because the voltage-divider network has a low sensitivity to changes in beta, let us return
to the transistor specifications and replace beta by the default value of 255.9 and see how
the results change. The result is the printout of Fig. 4.114, with voltage levels very close to
those obtained in Fig. 4.113.
Note the distinct advantage of having the network set up in memory. Any parameter
can now be changed and a new solution obtained almost instantaneously—a wonderful
advantage in the design process.
Fixed-Bias Configuration Although the voltage-divider bias network is relatively

insensitive to changes in the beta value, the fixed-bias configuration is very sensitive to
beta variations. This can be demonstrated by setting up the fixed-bias configuration of
Example 4.1 using a beta of 50 for the first run. The results of Fig. 4.115 demonstrate
that the design is a fairly good one. The collector or collector-to-emitter voltage is
appropriate for the applied source. The resulting base and collector currents are fairly
common for a good design.
However, if we now go back to the transistor specifications and change beta back to the
default value of 255.9, we obtain the results of Fig. 4.116. The collector voltage is now only
0.113 V at a current of 5.4 mA—a terrible operating point. Any applied ac signal would be
severely truncated due to the low collector voltage.
FIG. 4.115 FIG. 4.116

Fixed-bias configuration with a b of 50. Network of Fig. 4.115 with a b of 255.9.
Clearly, therefore, from the preceding analysis, the voltage-divider configuration is the COMPUTER ANALYSIS 237
preferred design if there is any concern about beta variations.
Multisim
Multisim will now be applied to the fixed-bias network of Example 4.4 to provide an
opportunity to review the transistor options internal to the software package and to com-
pare results with the handwritten approximate solution.
All the components of Fig. 4.117 except the transistor can be entered using the procedure
described in Chapter 2. Transistors are available through the Transistor key pad, which
is the fourth option down on the Component toolbar. When it is selected, the Select a
Component dialog box will appear, from which BJT_NPN is chosen. The result is a Com-
ponent list, from which 2N2222A can be selected. An OK, and the transistor will appear
on the screen with the labels Q1 and 2N2222A. The label Bf ⴝ 50 can be added by first
selecting Place in the top toolbar followed by the Text option. Place the resulting marker
in the area you want to place the text and click once more. The result is a blank space with
a blinking marker for where the text will appear when entered. When finished, a second
double-click, and the label is set. To move the label to the position shown in Fig. 4.117,
simply click on the label to place the four small squares around the device. Then click it
once more and drag it to the desired position. Release the clicker, and it is in place. Another
click, and the four small markers will disappear.
FIG. 4.117
Verifying the results of Example 4.4 using Multisim.
Even though the label may say Bf ⴝ 50, the transistor will still have the default param-
eters stored in memory. To change the parameters, the first step is to click on the device
to establish the device boundaries. Then select Edit, followed by Properties, to obtain
the BJT_NPN dialog box. If it is not already present, select Value and then Edit Model.
The result will be the Edit Model dialog box in which b and Is can be set to 50 and 1 nA,
respectively. Then choose Change Part Model to obtain the BJT_NPN dialog box again
and select OK. The transistor symbol on the screen will now have an asterisk to indicate
that the default parameters have been modified. One more click to remove the four markers,
and the transistor is set with its new parameters.
The indicators appearing in Fig. 4.117 were set as described in the previous chapter.
Finally, the network must be simulated using one of the methods described in Chapter 2.
For this example the switch was set to the 1 position and then back to the 0 position after the
Indicator values stabilized. The relatively low levels of current were partially responsible
for the low level of this voltage.
238 DC
SEMICONDUCTOR
BIASING—BJTs The results are a close match with those of Example 4.4 with IC 2.217 mA, VB
DIODES 2.636 V, VC 15.557 V, and VE 2.26 V.
The relatively few comments required here to permit the analysis of transistor networks
is a clear indication that the breadth of analysis using Multisim can be expanded dramati-
cally without having to learn a whole new set of rules—a very welcome characteristic of
most technology software packages.
PROBLEMS
●
4.3 Fixed-Bias Configuration
1. For the fixed-bias configuration of Fig. 4.118, determine:
a. IBQ.
b. ICQ.
c. VCEQ.
d. VC.
e. VB.
f. VE.
ICQ
1.8 kΩ
510 kΩ
β=120
FIG. 4.118
Problems 1, 4, 6, 7, 14, 65, 69,
71, and 75.
2. Given the information appearing in Fig. 4.119, determine:

a. IC.
b. RC.
c. RB.
d. VCE.
a. IC.
b. VCC.
c. b.
d. RB.
12 V
IC
RC
RB
VC = 6 V
+
VCE β = 80
I B = 40 μA –
FIG. 4.119 FIG. 4.120

4. Find the saturation current (ICsat) for the fixed-bias configuration of Fig. 4.118. LASTPROBLEMS
H1 HEAD 239
*5. Given the BJT transistor characteristics of Fig. 4.121:
a. Draw a load line on the characteristics determined by E = 21 V and RC = 3 k for a
fixed-bias configuration.
b. Choose an operating point midway between cutoff and saturation. Determine the value of
RB to establish the resulting operating point.
c. What are the resulting values of ICQ and VCEQ?
d. What is the value of b at the operating point?
e. What is the value of a defined by the operating point?
f. What is the saturation current (ICsat) for the design?
g. Sketch the resulting fixed-bias configuration.
h. What is the dc power dissipated by the device at the operating point?
i. What is the power supplied by VCC?
j. Determine the power dissipated by the resistive elements by taking the difference between
the results of parts (h) and (i).
IC (mA)
110 μA
100 μA
10 90 μA
80 μA
9
70 μA
8
60 μA
7
50 μA
6
40 μA
5
30 μA
4
3 20 μA
2
10 μA
1
IB = 0 μA
0 5 10 15 20 25 30 VCE (V)
FIG. 4.121
Problems 5, 6, 9, 13, 24, 44, and 57.
6. a. Ignoring the provided value of b(120) draw the load line for the network of Fig. 4.118 on the
characteristics of Fig. 4.121.
b. Find the Q-point and the resulting ICQ and VCEQ.
c. What is the beta value at this Q-point?
7. If the base resistor of Fig. 4.118 is increased to 910 k, find the new Q-point and resulting
values of ICQ and VCEQ.
4.4 Emitter-Bias Configuration

8. For the emitter-stabilized bias circuit of Fig. 4.122, determine:
a. IBQ.
b. ICQ.
c. VCEQ.
d. VC.
e. VB.
f. VE.
240 DC
SEMICONDUCTOR
BIASING—BJTs
DIODES
470 Ω
270 kΩ
β=125
2.2 kΩ
FIG. 4.122
Problems 8, 9, 12, 14, 66, 69, 72, and 76.
9. a. Draw the load line for the network of Fig. 4.122 on the characteristics of Fig. 4.121 using b
from problem 8 to find IBQ.
b. Find the Q-point and resulting values ICQ and VCEQ.
c. Find the value of b at the Q-point.
d. How does the value of part (c) compare with b 125 in problem 8?
e. Why are the results for problem 9 different from those of problem 8?
10. Given the information provided in Fig. 4.123, determine:
a. RC.
b. RE.
c. RB.
d. VCE.
e. VB.
a. b.
b. VCC.
c. RB.
FIG. 4.123 FIG. 4.124

12. Determine the saturation current (ICsat) for the network of Fig. 4.122.
*13. Using the characteristics of Fig. 4.121, determine the following for an emitter-bias configura-
tion if a Q-point is defined at ICQ = 4 mA and VCEQ = 10 V.
a. RC if VCC = 24 V and RE = 1.2 k.
b. b at the operating point.
c. RB.
d. Power dissipated by the transistor.
e. Power dissipated by the resistor RC.
*14. a. Determine IC and VCE for the network of Fig. 4.118. LASTPROBLEMS
H1 HEAD 241
b. Change b to 180 and determine the new value of IC and VCE for the network of Fig. 4.118.
c. Determine the magnitude of the percentage change in IC and VCE using the following
equations:
IC(part b) - IC(part a) VCE(part b) - VCE(part a)
%IC = ` ` * 100%, %VCE = ` ` * 100%
IC(part a) VCE(part a)
d. Determine IC and VCE for the network of Fig. 4.122.
e. Change b to 187.5 and determine the new value of IC and VCE for the network of Fig. 4.122.
f. Determine the magnitude of the percentage change in IC and VCE using the following
equations:
IC(part c) - IC(part d) VCE(part c) - VCE(part d)
%IC = ` ` * 100%, %VCE = ` ` * 100%
IC(part d) VCE(part d)
g. In each of the above, the magnitude of b was increased 50%. Compare the percentage
change in IC and VCE for each configuration, and comment on which seems to be less sensi-
tive to changes in b.
4.5 Voltage-Divider Bias Configuration

15. For the voltage-divider bias configuration of Fig. 4.125, determine:
a. IBQ.
b. ICQ.
c. VCEQ.
d. VC.
e. VE.
f. VB.
16. a. Repeat problem 15 for b 140 using the general approach (not the approximate).
b. What levels are affected the most? Why?
a. IC.
b. VE.
c. VB.
d. R1.
FIG. 4.125 FIG. 4.126

Problems 15, 16, 20, 23, 25, 67, Problems 17 and 19.
69, 70, 73, and 77.

a. IC.
b. VE.
c. VCC.
d. VCE.
e. VB.
f. R1.
242 DC
SEMICONDUCTOR
BIASING—BJTs
DIODES
VE
FIG. 4.127
Problem 18.
19. Determine the saturation current (ICsat) for the network of Fig. 4.125.
20. a. Repeat problem 16 with b 140 using the approximate approach and compare results.
b. Is the approximate approach valid?
*21. Determine the following for the voltage-divider configuration of Fig. 4.128 using the approxi-
mate approach if the condition established by Eq. (4.33) is satisfied.
a. IC.
b. VCE.
c. IB.
d. VE.
e. VB.
FIG. 4.128
Problems 21, 22, and 26.
*22. Repeat Problem 21 using the exact (Thévenin) approach and compare solutions. Based on the
results, is the approximate approach a valid analysis technique if Eq. (4.33) is satisfied?
23. a. Determine ICQ, VCEQ, and IBQ for the network of Problem 15 (Fig. 4.125) using the approxi-
mate approach even though the condition established by Eq. (4.33) is not satisfied.
b. Determine ICQ, VCEQ, and IBQ using the exact approach.
c. Compare solutions and comment on whether the difference is sufficiently large to require
standing by Eq. (4.33) when determining which approach to employ.
*24. a. Using the characteristics of Fig. 4.121, determine RC and RE for a voltage-divider network
having a Q-point of ICQ = 5 mA and VCEQ = 8 V. Use VCC = 24 V and RC = 3RE.
b. Find VE.
c. Determine VB.
d. Find R2 if R1 = 24 k assuming that bRE 7 10R2.
e. Calculate b at the Q-point.
f. Test Eq. (4.33), and note whether the assumption of part (d) is correct.
*25. a. Determine IC and VCE for the network of Fig. 4.125. LASTPROBLEMS
H1 HEAD 243
b. Change b to 120 (50% increase), and determine the new values of IC and VCE for the net-
work of Fig. 4.125.
c. Determine the magnitude of the percentage change in IC and VCE using the following
equations:
%IC = ` ` * 100%, %VCE = ` ` * 100%
d. Compare the solution to part (c) with the solutions obtained for parts (c) and (f) of Problem 14.
e. Based on the results of part (d), which configuration is least sensitive to variations in b?
*26. a. Repeat parts (a) through (e) of Problem 25 for the network of Fig. 4.128. Change b to 180
in part (b).
b. What general conclusions can be made about networks in which the condition bRE 7 10R2
is satisfied and the quantities IC and VCE are to be determined in response to a change in b?
4.6 Collector-Feedback Configuration

27. For the collector-feedback configuration of Fig. 4.129, determine:
a. IB.
b. IC.
c. VC.
270 kΩ
1.2 kΩ
FIG. 4.129
Problems 27, 28, 74, and 78.
28. For the network of problem 27

V VCC - VBE
a. Determine ICQ using the equation ICQ ⬵ =
R RC + RE
b. Compare with the results of problem 27 for ICQ.
c. Compare R to RF>b.
d. Is the statement valid that the larger R is compared with RF>b, the more accurate the
V
equation ICQ ⬵ ? Prove using a short derivation for the exact current ICQ.
R
e. Repeat parts (a) and (b) for b 240 and comment on the new level of ICQ.
29. For the voltage feedback network of Fig. 4.130, determine:
a. IC.
b. VC.
c. VE.
d. VCE.
30. a. Compare levels of R = RC + RE to RF>b for the network of Fig. 4.131.
b. Is the approximation ICQ ⬵ V>R valid?
*31. a. Determine the levels of IC and VCE for the network of Fig. 4.131.
b. Change b to 135 (50% increase), and calculate the new levels of IC and VCE.
c. Determine the magnitude of the percentage change in IC and VCE using the following equations:
%IC = ` ` * 100%, %VCE = ` ` * 100%
d. Compare the results of part (c) with those of Problems 14(c), 14(f ), and 25(c). How does
the collector-feedback network stack up against the other configurations in sensitivity to
changes in b?
244 DC
SEMICONDUCTOR
BIASING—BJTs
DIODES
8.2 kΩ
330 kΩ
β=180
1.8 kΩ
FIG. 4.130 FIG. 4.131

Problems 29 and 30. Problems 30 and 31.
32. Determine the range of possible values for VC for the network of Fig. 4.132 using the 1-MÆ
potentiometer.
*33. Given VB = 4 V for the network of Fig. 4.133, determine:
a. VE.
b. IC.
c. VC.
d. VCE.
e. IB.
f. b.
FIG. 4.132 FIG. 4.133

4.7 Emitter-Follower Configuration

*34. Determine the level of VE and IE for the network of Fig. 4.134.
FIG. 4.134
Problem 34.
35. For the emitter follower network of Fig. 4.135 LASTPROBLEMS
H1 HEAD 245
a. Find IB, IC, and IE.
b. Determine VB, VC, and VE.
c. Calculate VBC and VCE.
12 V
22 k⍀
C
Vi β = 110
B
Vo
E
82 k⍀
1.2 k⍀
FIG. 4.135
Problem 35.
4.8 Common-Base Configuration

*36. For the network of Fig. 4.136, determine:
a. IB.
b. IC.
c. VCE.
d. VC.
a. IE.
b. VC.
c. VCE.
38. For the common-base network of Fig. 4.138
a. Using the information provided determine the value of RC.
b. Find the currents IB and IE.
c. Determine the voltages VBC and VCE.
14 V
RC
VC = 8 V
– 8V
Vo
β = 80 2.2 kΩ
– VCE + VC β = 90
4V
Vi
IE
1.8 kΩ RE 1.1 k⍀
10 V
FIG. 4.136 FIG. 4.137 FIG. 4.138

Problem 36. Problem 37. Problem 38.
4.9 Miscellaneous Bias Configurations

a. IB.
b. IC.
c. VE.
d. VCE.
246 DC
SEMICONDUCTOR
BIASING—BJTs
DIODES
IB
FIG. 4.139 FIG. 4.140

40. Given VC = 8 V for the network of Fig. 4.140, determine:

a. IB.
b. IC.
c. b.
d. VCE.
4.11 Design Operations

41. Determine RC and RB for a fixed-bias configuration if VCC = 12 V, b = 80, and ICQ = 2.5 mA
with VCEQ = 6 V. Use standard values.
42. Design an emitter-stabilized network at ICQ = 12ICsat and VCEQ = 12VCC. Use VCC = 20 V,
ICsat = 10 mA, b = 120, and RC = 4RE. Use standard values.
43. Design a voltage-divider bias network using a supply of 24 V, a transistor with a beta of 110,
and an operating point of ICQ = 4 mA and VCEQ = 8 V. Choose VE = 18VCC. Use standard
values.
*44. Using the characteristics of Fig. 4.121, design a voltage-divider configuration to have a satura-
tion level of 10 mA and a Q-point one-half the distance between cutoff and saturation. The
available supply is 28 V, and VE is to be one-fifth of VCC. The condition established by Eq.
(4.33) should also be met to provide a high stability factor. Use standard values.
4.12 Multiple BJT Networks

45. For the R–C-coupled amplifier of Fig. 4.141 determine
a. the voltages VB, VC, and VE for each transistor.
b. the currents IB, IC, and IE for each transistor
+20 V
2.2 kΩ 22 kΩ 2.2 kΩ
18 kΩ
Vo
10 μF 10 μF
Vi
Q1 β = 160 Q2 β = 90
10 μF
4.7 kΩ + 3.3 kΩ +
1 kΩ 20 μF 1.2 kΩ 20 μF
FIG. 4.141
Problem 45.
46. For the Darlington amplifier of Fig. 4.142 determine
a. the level of bD.
b. the base current of each transistor.
c. the collector current of each transistor.
d. the voltages VC1, VC2, VE1, and VE2.
18 V LASTPROBLEMS
H1 HEAD 247
2.2 MΩ
Vi β1 = 50, β2 = 75
VBE1 = VBE2 = 0.7 V
Vo
470 Ω
FIG. 4.142
Problem 46.
47. For the cascode amplifier of Fig. 4.143 determine

a. the base and collector currents of each transistor.
b. the voltages VB1, VB2, VE1, VC1, VE2, and VC2.
VCC = 22 V
RC
RB 2.2 kΩ
1
8.2 kΩ Vo
C1 C = 5 μF
Q 2 β2 = 120
10 μF
RB
2
4.7 kΩ
Vi Q 1 β1 = 60
Cs = 5 μF
RB
3
3.3 kΩ RE
CE = 20 μF
1.1 kΩ
FIG. 4.143
Problem 47.
48. For the feedback amplifier of Fig. 4.144 determine

a. the base and collector current of each transistor.
b. the base, emitter, and collector voltages of each transistor.
4.13 Current Mirror Circuits

49. Calculate the mirrored current I in the circuit of Fig. 4.145.
248 DC
SEMICONDUCTOR
BIASING—BJTs 12 V
DIODES
220 Ω
Vo
Vi
β1 = 80
β2 = 160
1.8 MΩ
FIG. 4.144 FIG. 4.145

*50. Calculate collector currents for Q1 and Q2 in Fig. 4.146.
FIG. 4.146
Problem 50.
4.14 Current Source Circuits

51. Calculate the current through the 2.2-k⍀ load in the circuit of Fig. 4.147.
52. For the circuit of Fig. 4.148, calculate the current I.
28 V
I
2.2 kΩ
⫹6 V RB
β = 120
100 kΩ
1.2 kΩ
FIG. 4.147 FIG. 4.148

*53. Calculate the current I in the circuit of Fig. 4.149. LASTPROBLEMS
H1 HEAD 249
FIG. 4.149
Problem 53.
4.15 pnp Transistors

54. Determine VC, VCE, and IC for the network of Fig. 4.150.
55. Determine VC and IB for the network of Fig. 4.151.
FIG. 4.150 FIG. 4.151

56. Determine IE and VC for the network of Fig. 4.152.
FIG. 4.152
Problem 56.
4.16 Transistor Switching Networks

*57. Using the characteristics of Fig. 4.121, determine the appearance of the output waveform for
the network of Fig. 4.153. Include the effects of VCEsat, and determine IB, IBmax, and ICsat when
Vi = 10 V. Determine the collector-to-emitter resistance at saturation and cutoff.
250 DC
SEMICONDUCTOR
BIASING—BJTs 10 V
DIODES
Vi 2.4 kΩ
Vo
10 V
180 kΩ
Vi
0V
t
FIG. 4.153
Problem 57.
*58. Design the transistor inverter of Fig. 4.154 to operate with a saturation current of 8 mA using a
transistor with a beta of 100. Use a level of IB equal to 120% of IBmax and standard resistor values.
5V
Vi RC
5V Vo
RB
Vi = 100
0V
t
FIG. 4.154
Problem 58.
59. a. Using the characteristics of Fig. 3.23e, determine ton and toff at a current of 2 mA. Note the
use of log scales and the possible need to refer to Section 9.2.
b. Repeat part (a) at a current of 10 mA. How have ton and toff changed with increase in col-
lector current?
c. For parts (a) and (b), sketch the pulse waveform of Fig. 4.91 and compare results.
4.17 Troubleshooting Techniques

*60. The measurements of Fig. 4.155 all reveal that the network is not functioning correctly. List as
many reasons as you can for the measurements obtained.
(a) (b) (c)
FIG. 4.155
Problem 60.
*61. The measurements appearing in Fig. 4.156 reveal that the networks are not operating properly.
Be specific in describing why the levels obtained reflect a problem with the expected network
behavior. In other words, the levels obtained reflect a very specific problem in each case.
16 V 16 V LASTPROBLEMS
H1 HEAD 251
3.6 kΩ 3.6 kΩ
91 kΩ 91 kΩ
VB = 9.4 V
= 100 2.64 V = 100
4V
18 kΩ 18 kΩ
1.2 kΩ 1.2 kΩ
(a) (b)
FIG. 4.156
Problem 61.
62. For the circuit of Fig. 4.157:

a. Does VC increase or decrease if RB is increased?
b. Does IC increase or decrease if b is reduced?
c. What happens to the saturation current if b is increased?
d. Does the collector current increase or decrease if VCC is reduced?
e. What happens to VCE if the transistor is replaced by one with smaller b?
63. Answer the following questions about the circuit of Fig. 4.158:
a. What happens to the voltage VC if the transistor is replaced by one having a larger value of b?
b. What happens to the voltage VCE if the ground leg of resistor RB2 opens (does not connect
to ground)?
c. What happens to IC if the supply voltage is low?
d. What voltage VCE would occur if the transistor base–emitter junction fails by becoming
open?
e. What voltage VCE would result if the transistor base–emitter junction fails by becoming a
short?
*64. Answer the following questions about the circuit of Fig. 4.159:
a. What happens to the voltage VC if the resistor RB is open?
b. What should happen to VCE if b increases due to temperature?
c. How will VE be affected when replacing the collector resistor with one whose resistance is
at the lower end of the tolerance range?
d. If the transistor collector connection becomes open, what will happen to VE?
e. What might cause VCE to become nearly 18 V?
VC
VC
VB
VB
VE VE
FIG. 4.157 FIG. 4.158 FIG. 4.159

Problem 62. Problem 63. Problem 64.
252 DC
SEMICONDUCTOR
BIASING—BJTs 4.18 Bias Stabilization
DIODES 65. Determine the following for the network of Fig. 4.118:
a. S(ICO).
b. S(VBE).
c. S(b), using T1 as the temperature at which the parameter values are specified and b(T2) as
25% more than b(T1).
d. Determine the net change in IC if a change in operating conditions results in ICO increasing
from 0.2 mA to 10 mA, VBE drops from 0.7 V to 0.5 V, and b increases 25%.
a. S(ICO).
b. S(VBE).
a. S(ICO).
b. S(VBE).
a. S(ICO).
b. S(VBE).
*69. Compare the relative values of stability for Problems 65 through 68. The results for Exercises
65 and 67 can be found in Appendix E. Can any general conclusions be derived from the
results?
*70. a. Compare the levels of stability for the fixed-bias configuration of Problem 65.
b. Compare the levels of stability for the voltage-divider configuration of Problem 67.
c. Which factors of parts (a) and (b) seem to have the most influence on the stability of the
system, or is there no general pattern to the results?

71. Perform a PSpice analysis of the network of Fig. 4.118. That is, determine IC, VCE, and IB.
72. Repeat Problem 71 for the network of Fig. 4.122.
PROBLEMS 361
FIG. 5.149
Network of Example 5.9 redrawn using Multisim.
PROBLEMS
●
5.2 Amplification in the AC Domain
1. a. What is the expected amplification of a BJT transistor amplifier if the dc supply is set to
zero volts?
b. What will happen to the output ac signal if the dc level is insufficient? Sketch the effect on
the waveform.
c. What is the conversion efficiency of an amplifier in which the effective value of the current
through a 2.2-k load is 5 mA and the drain on the 18-V dc supply is 3.8 mA?
2. Can you think of an analogy that would explain the importance of the dc level on the resulting
ac gain?
3. If a transistor amplifier has more than one dc source, can the superposition theorem be applied
to obtain the response of each dc source and algebraically add the results?
5.3 BJT Transistor Modeling

4. What is the reactance of a 10@mF capacitor at a frequency of 1 kHz? For networks in which the
resistor levels are typically in the kilohm range, is it a good assumption to use the short-circuit
equivalence for the conditions just described? How about at 100 kHz?
5. Given the common-base configuration of Fig. 5.150, sketch the ac equivalent using the nota-
tion for the transistor model appearing in Fig. 5.7.
FIG. 5.150
Problem 5.
5.4 The re Transistor Model
6. a. Given an Early voltage of VA 100 V, determine ro if VCEQ = 8 V and ICQ = 4 mA.
b. Using the results of part (a), find the change in IC for a change in VCE of 6 V at the same
Q-point as part (a).
362 BJT AC ANALYSIS 7. For the common-base configuration of Fig. 5.18, an ac signal of 10 mV is applied, resulting in
an ac emitter current of 0.5 mA. If a 0.980, determine:
a. Zi.
b. Vo if RL = 1.2 k.
c. Av = Vo>Vi.
d. Zo with ro .
e. Ai = Io >Ii.
f. Ib.
8. Using the model of Fig. 5.16, determine the following for a common-emitter amplifier if
b 80, IE(dc) = 2 mA, and ro = 40 k.
a. Zi.
b. Ib.
c. Ai = Io >Ii = IL >Ib if RL = 1.2 k.
d. Av if RL = 1.2 k.
9. The input impedance to a common-emitter transistor amplifier is 1.2 k with b 140,
ro = 50 k, and RL = 2.7 k. Determine:
a. re.
b. Ib if Vi = 30 mV.
c. Ic.
d. Ai = Io>Ii = IL >Ib.
e. Av = Vo>Vi.
10. For the common-base configuration of Fig. 5.18, the dc emitter current is 3.2 mA and a is 0.99.
Determine the following if the applied voltage is 48 mV and the load is 2.2 k.
a. re.
b. Zi.
c. Ic.
d. Vo.
e. Av.
f. Ib.
5.5 Common-Emitter Fixed-Bias Configuration

11. For the network of Fig. 5.151:
a. Determine Zi and Zo.
b. Find Av.
c. Repeat parts (a) and (b) with ro = 20 k.
12. For the network of Fig. 5.152, determine VCC for a voltage gain of Av = - 160.
12 V
VCC
4.7 kΩ
2.2 kΩ
220 kΩ Io 1 MΩ
Vo
Vo
β = 90
Vi Zo Vi ro = ∞ Ω
Ii β = 60
ro = 40 kΩ
Zi
FIG. 5.151 FIG. 5.152


a. Calculate IB, IC, and re.
b. Determine Zi and Zo.
c. Calculate Av.
d. Determine the effect of ro = 30 k on Av.
14. For the network of Fig. 5.153, what value of RC will cut the voltage gain to half the value
obtained in problem 13?
12 V PROBLEMS 363
5.6 kΩ
Io
Vo
Vi Zo
Ii β = 100
390 kΩ gos = 25 μS
Zi
8V
FIG. 5.153
Problem 13.
5.6 Voltage-Divider Bias
a. Determine re.
b. Calculate Zi and Zo.
c. Find Av.
d. Repeat parts (b) and (c) with ro = 25 k.
VCC = 16 V
3.9 kΩ
39 kΩ Io
Vo
1 μF 1 μF
Zo
Vi
β = 100
Ii ro = 50 kΩ
4.7 kΩ
Zi
1.2 kΩ 10 μF
FIG. 5.154
Problem 15.
16. Determine VCC for the network of Fig. 5.155 if Av = - 160 and ro = 100 k.
a. Determine re.
b. Calculate VB and VC.
VCC = 20 V
c. Determine Zi and Av = Vo>Vi.
VCC
3.3 kΩ 4.7 kΩ
82 kΩ 220 kΩ
VC
Vo Vo
CC CC
VB
Vi β = 100 Vi β = 180
CC gos = 20 μS CC gos = 30 μS
Zi
5.6 kΩ 56 kΩ
1 kΩ CE 2.2 kΩ CE
FIG. 5.155 FIG. 5.156

364 BJT AC ANALYSIS 18. For the network of Fig. 5.157:
a. Determine re.
b. Find the dc voltages VB, VCB, and VCE.
c. Determine Zi and Zo.
d. Calculate Av Vo>Vi.
Vo Zo
β = 70
ro = 60 k⍀
24 V
3.3 k⍀ 2.2 k⍀
12 V
Vi
27 k⍀
68 k⍀ Zi
FIG. 5.157
Problem 18.
5.7 CE Emitter–Bias Configuration

a. Determine re.
b. Find Zi and Zo.
c. Calculate Av.
d. Repeat parts (b) and (c) with ro = 20 k.
20. Repeat Problem 19 with RE bypassed. Compare results.
21. For the network of Fig. 5.159, determine RE and RB if Av = - 10 and re = 3.8 . Assume that
Zb = bRE.
20 V
20 V
2.2 kΩ 8.2 kΩ
Io
390 kΩ RB
Vo Vo
β = 140 β = 120
Vi Vi
ro = 100 kΩ gos = 10 μS
Ii
1.2 kΩ Zo RE
Zi
FIG. 5.158 FIG. 5.159


a. Determine re.
b. Find Zi and Av.
a. Determine re.
b. Calculate VB, VCE, and VCB.
d. Calculate Av Vo>Vi.
e. Determine Ai Io>Ii.
22 V PROBLEMS 365
5.6 kΩ
330 kΩ Io
16 V
Vo
Ii CC
Io
Vi β = 80
CC ro = 40 kΩ 430 k⍀
4.7 k⍀
Zi Vo
1.2 kΩ
Vi β = 200
gos = 20 μS
120 k⍀
0.47 kΩ CE 1.2 k⍀
FIG. 5.160 FIG. 5.161

5.8 Emitter-Follower Configuration 16 V

a. Determine re and bre.
b. Find Zi and Zo.
c. Calculate Av. 270 kΩ
Vi β = 110
ro = 50 kΩ
Ii
Vo
Io
Zi
2.7 kΩ
Zo
FIG. 5.162
Problem 24.
b. Find Av.
c. Calculate Vo if Vi = 1 mV.
a. Calculate IB and IC. VCC = 20 V
b. Determine re.
d. Find Av.
12 V
56 kΩ
Ii
β = 120
Vi β = 200
ro = 40 kΩ Vi
gos = 20 μS
Ii
Vo Vo
390 kΩ Io Io
Zi 8.2 kΩ
5.6 kΩ 2 kΩ
Zo
−8 V
FIG. 5.163 FIG. 5.164

366 BJT AC ANALYSIS 5.9 Common-Base Configuration
27. For the common-base configuration of Fig. 5.165:
a. Determine re.
b. Find Zi and Zo.
c. Calculate Av.
*28. For the network of Fig. 5.166, determine Av.
8V
3.6 kΩ
Io
Vo
+6 V −10 V
β = 75
gos = 5 μS
6.8 kΩ 4.7 kΩ
Ii Io
Vi
Vi Vo
Ii
3.9 kΩ
Zi α = 0.998 Zo
gos = 10 μS
−5 V
FIG. 5.165 FIG. 5.166

5.10 Collector Feedback Configuration

29. For the collector feedback configuration of Fig. 5.167:
a. Determine re.
b. Find Zi and Zo.
c. Calculate Av.
*30. Given re = 10 , b 200, Av = - 160, and Ai = 19 for the network of Fig. 5.168, deter-
mine RC, RF, and VCC.
a. Derive the approximate equation for Av.
b. Derive the approximate equations for Zi and Zo.
c. Given RC = 2.2 k, RF = 120 k, RE = 1.2 k, b 90, and VCC = 10 V, calculate
the magnitudes of Av, Zi, and Zo using the equations of parts (a) and (b).
12 V VCC
Io
3.9 kΩ RC
220 kΩ RF
Vo Vo
Zo re = 10 Ω
Vi Vi
β = 200
β = 120
Ii ro = 80 kΩ
ro = 40 kΩ
Zi
FIG. 5.167 FIG. 5.168

5.11 Collector DC Feedback Configuration

b. Find Av.
9V PROBLEMS 367
Io
1.8 kΩ
39 kΩ 22 kΩ
Vo
1 μF
10 μ F
Zo
Ii
β = 80
Vi
gos = 22 μS
1 μF
Zi
FIG. 5.169
Problems 32 and 33.
33. Repeat problem 32 with the addition of an emitter resistor RE 0.68 k.
5.12–5.15 Effect of RL and Rs and Two-Port Systems Approach

*34. For the fixed-bias configuration of Fig. 5.170:
a. Determine AvNL, Zi, and Zo.
b. Sketch the two-port model of Fig. 5.63 with the parameters determined in part (a) in place.
c. Calculate the gain AvL = Vo>Vi.
d. Determine the current gain AiL = Io>Ii.
18 V
3.3 kΩ
680 kΩ
1.8 μF Io
Vo
1.8 μF
Vi β = 100
Ii RL 4.7 kΩ
Zo
Zi
FIG. 5.170
Problems 34 and 35.
35. a. Determine the voltage gain AvL for the network of Fig. 5.170 for RL = 4.7 k, 2.2 k, and
0.5 k. What is the effect of decreasing levels of RL on the voltage gain?
b. How will Zi, Zo, and AvNL change with decreasing values of RL?
b. Sketch the two-port model of Fig. 5.63 with the parameters determined in part (a) in place.
c. Determine Av = Vo>Vi.
d. Determine Avs = Vo>Vs.
e. Change Rs to 1 k and determine Av. How does Av change with the level of Rs?
f. Change Rs to 1 k and determine Avs. How does Avs change with the level of Rs?
g. Change Rs to 1 k and determine AvNL, Zi, and Zo. How do they change with the change in Rs?
h. For the original network of Fig. 5.171 calculate Ai Io>Ii.
368 BJT AC ANALYSIS 12 V
Io
3 kΩ
1 MΩ
1 μF
Vo
Ii Rs 1 μF
Vi
β = 180
+ 0.6 kΩ
Zo
Vs Zi
–
FIG. 5.171
Problem 36.

b. Sketch the two-port model of Fig. 5.63 with the parameters determined in part (a) in
place.
c. Determine AvL and Avs.
d. Calculate AiL.
e. Change RL to 5.6 k and calculate Avs. What is the effect of increasing levels of RL on the
gain?
f. Change Rs to 0.5 k (with RL at 2.7 k) and comment on the effect of reducing Rs on
Av s .
g. Change RL to 5.6 k and Rs to 0.5 k and determine the new levels of Zi and Zo. How are
the impedance parameters affected by changing levels of RL and Rs?
24 V
4.3 kΩ
560 kΩ
10 μ F Io
Vo
Ii Rs 10 μF
Vi
β = 80
+ 1 kΩ
RL 2.7 kΩ
Vs Zo
Zi
–
FIG. 5.172
Problem 37.
38. For the voltage-divider configuration of Fig. 5.173:

b. Sketch the two-port model of Fig. 5.63 with the parameters determined in part (a) in
place.
c. Calculate the gain AvL.
d. Determine the current gain AiL.
e. Determine AvL, AiL, and Zo using the re model and compare solutions.
39. a. Determine the voltage gain AvL for the network of Fig. 5.173 with RL = 4.7 k, 2.2 k,
and 0.5 k. What is the effect of decreasing levels of RL on the voltage gain?
b. How will Zi, Zo, and AvNL change with decreasing levels of RL?
PROBLEMS 369
FIG. 5.173
Problems 38 and 39.
40. For the emitter-stabilized network of Fig. 5.174:

b. Sketch the two-port model of Fig. 5.63 with the values determined in part (a).
d. Change Rs to 1 k. What is the effect on AvNL, Zi, and Zo?
e. Change Rs to 1 k and determine AvL and Avs. What is the effect of increasing levels of Rs
on AvL and Avs?
f. Determine Ai Io>Ii.
Io
Ii
FIG. 5.174
Problem 40.

b. Sketch the two-port model of Fig. 5.63 with the values determined in part (a).
d. Change Rs to 1 k and determine AvL and Avs. What is the effect of increasing levels of Rs
on the voltage gains?
e. Change Rs to 1 k and determine AvNL, Zi, and Zo. What is the effect of increasing levels of
Rs on the parameters?
f. Change RL to 5.6 k and determine AvL and Avs. What is the effect of increasing levels of
RL on the voltage gains? Maintain Rs at its original level of 0.6 k.
Io
g. Determine Ai = with RL = 2.7 k and Rs = 0.6 k.
Ii
370 BJT AC ANALYSIS
Ii
Io
FIG. 5.175
Problem 41.
*42. For the common-base network of Fig. 5.176:

a. Determine Zi, Zo, and AvNL.
b. Sketch the two-port model of Fig. 5.63 with the parameters of part (a) in place.
d. Determine AvL and Avs using the re model and compare with the results of part (c).
e. Change Rs to 0.5 k and RL to 2.2 k and calculate AvL and Avs. What is the effect of
changing levels of Rs and RL on the voltage gains?
f. Determine Zo if Rs changed to 0.5 k with all other parameters as appearing in Fig. 5.176.
How is Zo affected by changing levels of Rs?
g. Determine Zi if RL is reduced to 2.2 k. What is the effect of changing levels of RL on the
input impedance?
h. For the original network of Fig. 5.176 determine Ai Io>Ii.
FIG. 5.176
Problem 42.
5.16 Cascaded Systems

*43. For the cascaded system of Fig. 5.177 with two identical stages, determine:
a. The loaded voltage gain of each stage.
b. The total gain of the system, Av and Avs.
c. The loaded current gain of each stage.
d. The total current gain of the system AiL = Io >Ii.
e. How Zi is affected by the second stage and RL.
f. How Zo is affected by the first stage and Rs.
g. The phase relationship between Vo and Vi.
Ii Rs 1 μF V 1 μF Io PROBLEMS 371
i Vo
CE amplifier CE amplifier
+ 0.6 kΩ
Zi = 1 kΩ Zi = 1 kΩ
Vs RL 2.7 kΩ
Zo = 3.3 kΩ Zo = 3.3 kΩ Zo
– Zi
Av NL = – 420 Av NL = – 420
Zo Zi
1 2
FIG. 5.177
Problem 43.
*44. For the cascaded system of Fig. 5.178, determine:

a. The loaded voltage gain of each stage.
b. The total gain of the system, AvL and Avs.
c. The loaded current gain of each stage.
d. The total current gain of the system.
e. How Zi is affected by the second stage and RL.
f. How Zo is affected by the first stage and Rs.
g. The phase relationship between Vo and Vi.
Ii Rs Vi 10 μF Io Vo
Emitter - follower CE amplifier
+ 1 kΩ 10 μF
Zi = 50 kΩ Z i = 1.2 kΩ
Vs RL 2.2 kΩ
Zo = 20 Ω Zo = 4.6 kΩ
– Zi Zo
Av ≅ 1 Av = – 640
NL NL
Zo Zi
1 2
FIG. 5.178
Problem 44.
45. For the BJT cascade amplifier of Fig. 5.179, calculate the dc bias voltages and collector current
for each stage.
46. a. Calculate the voltage gain of each stage and the overall ac voltage gain for the BJT cascade
amplifier circuit of Fig. 5.179.
b. Find AiT = Io >Ii.
Io
Ii
FIG. 5.179
Problems 45 and 46.
372 BJT AC ANALYSIS 47. For the cascode amplifier circuit of Fig. 5.180, calculate the dc bias voltages VB1, VB2, and VC2.
*48. For the cascode amplifier circuit of Fig. 5.180, calculate the voltage gain Av and output voltage Vo.
49. Calculate the ac voltage across a 10-k load connected at the output of the circuit in Fig. 5.180.
+20 V
1.5 kΩ
1 μF
7.5 kΩ
Vo
50 μ F Q2
β = 200
6.2 kΩ
10 μ F Q1
Vi β = 100
10 mV
3.9 kΩ
1 kΩ 100 μF
FIG. 5.180
Problems 47 and 49.
5.17 Darlington Connection
50. For the Darlington network of Fig. 5.181:
a. Determine the dc levels of VB1, VC1, VE2, VCB1, and VCE2.
b. Find the currents IB1, IB2, and IE2.
c. Calculate Zi and Zo.
d. Determine the voltage gain Av Vo/Vi and current gain Ai Io>Ii.
Vi β1 = 50, β 2 = 120
Ii VBE = VBE = 0.7 V
1 2
Io
10 μF
FIG. 5.181
Problems 50 through 53.
51. Repeat problem 50 with a load resistor of 1.2 k.
52. Determine Av Vo>Vs for the network of Fig. 5.181 if the source has an internal resistance of
1.2 k and the applied load is 10 k.
53. A resistor RC 470 is added to the network of Fig. 5.181 along with a bypass capacitor
CE 5 mF across the emitter resistor. If bD 4000, VBET = 1.6 V, and ro1 = ro2 = 40 k
for a packaged Darlington amplifier:
a. Find the dc levels of VB1, VE2, and VCE2.
b. Determine Zi and Zo.
c. Determine the voltage gain Av Vo>Vi if the output voltage Vo is taken off the collector
terminal via a coupling capacitor of 10 mF.
5.18 Feedback Pair PROBLEMS 373
54. For the feedback pair of Fig. 5.182:
a. Calculate the dc voltages VB1, VB2, VC1, VC2, VE1, and VE2.
b. Determine the dc currents IB1, IC1, IB2, IC2, and IE2.
c. Calculate the impedances Zi and Zo.
d. Find the voltage gain Av = Vo>Vi.
e. Determine the current gain Ai = Io>Ii.
Io
68 Ω
Ii
Zo
Zi
FIG. 5.182
Problems 54 and 55.
55. Repeat problem 54 if a 22- resistor is added between VE2 and ground.
56. Repeat problem 54 if a load resistance of 1.2 k is introduced.
5.19 The Hybrid Equivalent Model

57. Given IE (dc) = 1.2 mA, b 120, and ro 40 k, sketch the following:
a. Common-emitter hybrid equivalent model.
b. Common-emitter re equivalent model.
c. Common-base hybrid equivalent model.
d. Common-base re equivalent model.
58. Given hie = 2.4 k, hfe = 100, hre = 4 * 10-4, and hoe = 25 mS, sketch the following:
a. Common-emitter hybrid equivalent model.
b. Common-emitter re equivalent model.
c. Common-base hybrid equivalent model.
d. Common-base re equivalent model.
59. Redraw the common-emitter network of Fig. 5.3 for the ac response with the approximate
hybrid equivalent model substituted between the appropriate terminals.
60. Redraw the network of Fig. 5.183 for the ac response with the re model inserted between the
appropriate terminals. Include ro.
61. Redraw the network of Fig. 5.184 for the ac response with the re model inserted between the
appropriate terminals. Include ro.
62. Given the typical values of hie = 1 k, hre = 2 * 10-4, and Av = - 160 for the input con-
figuration of Fig. 5.185:
a. Determine Vo in terms of Vi.
b. Calculate Ib in terms of Vi.
c. Calculate Ib if hreVo is ignored.
d. Determine the percentage difference in Ib using the following equation:
Ib(without hre) - Ib(with hre)
% difference in Ib = * 100%
Ib(without hre)
e. Is it a valid approach to ignore the effects of hreVo for the typical values employed in this
example?
Vo
Vo
FIG. 5.183 FIG. 5.184

FIG. 5.185
Problems 62 and 64.
63. Given the typical values of RL = 2.2 k and hoe = 20 mS, is it a good approximation to
ignore the effects of 1>hoe on the total load impedance? What is the percentage difference in
total loading on the transistor using the following equation?
RL - RL 7 (1>hoe)
% difference in total load = * 100%
RL
64. Repeat Problem 62 using the average values of the parameters of Fig. 5.92 with Av = - 180.
65. Repeat Problem 63 for RL = 3.3 k and the average value of hoe in Fig. 5.92.
5.20 Approximate Hybrid Equivalent Circuit
66. a. Given b 120, re 4.5 , and ro = 40 k, sketch the approximate hybrid equivalent
circuit.
b. Given hie = 1 k, hre = 2 * 10-4, hfe = 90, and hoe = 20 mS, sketch the re model.
67. For the network of Problem 11:
a. Determine re.
b. Find hfe and hie.
c. Find Zi and Zo using the hybrid parameters.
d. Calculate Av and Ai using the hybrid parameters.
e. Determine Zi and Zo if hoe = 50 mS.
f. Determine Av and Ai if hoe = 50 mS.
g. Compare the solutions above with those of Problem 9. (Note: The solutions are available in
Appendix E if Problem 11 was not performed.)
b. Calculate Av and Ai.
c. Determine re and compare bre to hie.
374
18 V PROBLEMS 375
2.2 kΩ
68 kΩ
Io
Vo
Ii
5 μF
Vi hfe = 180
Zo hie = 2.75 kΩ
5 μF
hoe = 25 μS
12 kΩ
Zi 1.2 kΩ 10 μF
FIG. 5.186
Problem 68.
*69. For the common-base network of Fig. 5.187:

b. Calculate Av and Ai.
c. Determine a, b, re, and ro.
hfb = −0.992
hib = 9.45 Ω
hob = 1 μ A/V
Ii
+ 10 μ F
Io
10 μF +
1.2 kΩ 2.7 kΩ
Vi + – Vo
Zi 4V 12 V Zo
– +
– –
FIG. 5.187
Problem 69.
5.21 Complete Hybrid Equivalent Model

*70. Repeat parts (a) and (b) of Problem 68 with hre = 2 * 10-4 and compare results.
a. Zi.
b. Av.
c. Ai = Io>Ii.
d. Zo.
*72. For the common-base amplifier of Fig. 5.189, determine:
a. Zi.
b. Ai.
c. Av.
d. Zo.
376 BJT AC ANALYSIS 20 V
2.2 kΩ
470 kΩ Io
Vo
Ii 5 μF
1 kΩ hfe = 140
+ Zo hie = 0.86 kΩ
+ 5 μF hre = 1.5 × 10− 4
hoe = 25 μS
Vs Vi
1.2 kΩ 10 μ F
–
Zi
–
FIG. 5.188
Problem 71.
hib = 9.45 Ω
hfb = −0.997
hob = 0.5 μ A/V
hrb = 1 × 10− 4
Ii
0.6 kΩ Io
5 μF + 5 μF +
+
1.2 kΩ 2.2 kΩ
Vs Vi Vo
Zi + – Zo
– 4V 14 V
– +
– –
FIG. 5.189
Problem 72.
5.22 Hybrid P Model
73. a. Sketch the Giacoletto (hybrid p) model for a common-emitter transistor if rb = 4 ,
Cp = 5 pF, Cu = 1.5 pF, hoe = 18 mS, b 120, and re = 14.
b. If the applied load is 1.2 k and the source resistance is 250 , draw the approximate
hybrid p model for the low- and mid-frequency range.
5.23 Variations of Transistor Parameters

For Problems 74 through 80, use Figs. 5.124 through 5.126.
74. a. Using Fig. 5.124, determine the magnitude of the percentage change in hfe for an IC change
from 0.2 mA to 1 mA using the equation
hfe(0.2 mA) - hfe(1 mA)
% change = ` ` * 100%
hfe(0.2 mA)
b. Repeat part (a) for an IC change from 1 mA to 5 mA.
75. Repeat Problem 74 for hie (same changes in IC).
76. a. If hoe = 20 mS at IC = 1 mA on Fig. 5.124, what is the approximate value of hoe at
IC = 0.2 mA?
b. Determine its resistive value at 0.2 mA and compare to a resistive load of 6.8 k. Is it a
good approximation to ignore the effects of 1>hoe in this case?
77. a. If hoe = 20 mS at IC = 1 mA of Fig. 5.124, what is the approximate value of hoe at
IC = 10 mA?
b. Determine its resistive value at 10 mA and compare to a resistive load of 6.8 k. Is it a
good approximation to ignore the effects of 1>hoe in this case?
78. a. If hre = 2 * 10-4 at IC = 1 mA on Fig. 5.124, determine the approximate value of hre at
0.1 mA.
b. For the value of hre determined in part (a), can hre be ignored as a good approximation if
Av = 210?
79. a. Based on a review of the characteristics of Fig. 5.124, which parameter changed the least PROBLEMS 377
for the full range of collector current?
b. Which parameter changed the most?
c. What are the maximum and minimum values of 1>hoe? Is the approximation 1>hoe 储 RL ⬵ RL
more appropriate at high or low levels of collector current?
d. In which region of current spectrum is the approximation hreVce ⬵ 0 the most appropriate?
80. a. Based on a review of the characteristics of Fig. 5.126, which parameter changed the most
with increase in temperature?
b. Which changed the least?
c. What are the maximum and minimum values of hfe? Is the change in magnitude signifi-
cant? Was it expected?
d. How does re vary with increase in temperature? Simply calculate its level at three or four
points and compare their magnitudes.
e. In which temperature range do the parameters change the least?
5.24 Troubleshooting
*81. Given the network of Fig. 5.190:
a. Is the network properly biased?
b. What problem in the network construction could cause VB to be 6.22 V and obtain the given
waveform of Fig. 5.190?
VCC = 14 V
RC 2.2 kΩ ve (V)
vi (mV)
R1 150 kΩ
10 μ F
0 t vo 0 t
10 μ F C2
VB = 6.22 V
β = 70 ve
C1
+
VBE = 0.7 V
Rs – 0 t
+ R2 39 kΩ
RE 1.5 kΩ 10 μ F
Vs
FIG. 5.190
Problem 81.

82. Using PSpice Windows, determine the voltage gain for the network of Fig. 5.25. Display the
input and output waveforms.
85. Using Multisim, determine the voltage gain for the network of Fig. 5.28.
86. Using Multisim, determine the voltage gain for the network of Fig. 5.39.
87. Using PSpice Windows, determine the level of Vo for Vi = 1 mV for the network of Fig. 5.69.
For the capacitive elements assume a frequency of 1 kHz.
by Edit Model. An Edit Model dialog box will appear in which Beta and Vto can be set LASTPROBLEMS
H1 HEAD 473
to 0.222 mA/V2 and ⴚ6 V, respectively. The value of Beta is determined using Eq. (6.17)
and the parameters of the network as follows:
IDSS 8 mA 8 mA
Beta = = = = 0.222 mA>V2
0 VP 0 2 0 -6 V 0 2 36 V2
Once the change is made, be sure to select Change Part Model before leaving the dialog
box. The JFET_N dialog box will appear again, but an OK, and the changes will be made.
The labels IDSS ⴝ 8 mA and Vp ⴝ ⴚ6 V are added using Place-Text. A blinking verti-
cal bar will appear marking the place where the label can be entered. Once entered, it can
easily be moved by simply clicking the area and dragging it to the desired position while
holding the clicker down.
Using the Indicator option on the first vertical toolbar displays the drain and source
voltages as shown in Fig. 7.74. In both cases the VOLTMETER_V option was chosen in
the Select a Component dialog box.
Selecting Simulate-Run or moving the switch to the 1 position results in the display of
Fig. 7.74. Note that VGS at -2.603 V is an exact match with the hand-calculated solution of
-2.6 V. Although the indicator is connected from source to ground, be aware that this is also
the gate-to-source voltage because the voltage drop across the 1-MÆ resistor is assumed to
be 0 V. The level of 11.405 V at the drain is very close to the hand-calculated solution of
11.42 V—in all, a complete verification of the results of Example 7.2.
PROBLEMS
●
7.2 Fixed-Bias Configuration
1. For the fixed-bias configuration of Fig. 7.75:
a. Sketch the transfer characteristics of the device.
b. Superimpose the network equation on the same graph.
c. Determine IDQ and VDSQ.
d. Using Shockley’s equation, solve for IDQ and then find VDSQ. Compare with the solutions of
part (c).
14 V
1.8 k⍀
FIG. 7.75
Problems 1 and 37.
2. For the fixed-bias configuration of Fig. 7.76, determine:

a. IDQ and VGSQ using a purely mathematical approach.
b. Repeat part (a) using a graphical approach and compare results.
c. Find VDS, VD, VG, and VS using the results of part (a).
3. Given the measured value of VD in Fig. 7.77, determine:
a. ID.
b. VDS.
c. VGG.
474 FET
SEMICONDUCTOR
BIASING
DIODES ⫺3 V
1.2 M⍀
IDSS = 8 mA
VD = 6 V VP = –4 V
+ VDS –
12 V 2.2 k⍀
ID
1 M⍀
–VGG
FIG. 7.76 FIG. 7.77

4. Determine VD and VGS for the fixed-bias configuration of Fig. 7.78.

5. Determine VD and VGS for the fixed-bias configuration of Fig. 7.79.
FIG. 7.78 FIG. 7.79

7.3 Self-Bias Configuration

6. For the self-bias configuration of Fig. 7.80:
a. Sketch the transfer curve for the device.
b. Superimpose the network equation on the same graph.
c. Determine IDQ and VGSQ.
d. Calculate VDS, VD, VG, and VS.
*7. Determine IDQ for the network of Fig. 7.80 using a purely mathematical approach. That is,
establish a quadratic equation for ID and choose the solution compatible with the network char-
acteristics. Compare to the solution obtained in Problem 6.
8. For the network of Fig. 7.81, determine:
a. VGSQ and IDQ.
b. VDS, VD, VG, and VS.
9. Given the measurement VS = 1.7 V for the network of Fig. 7.82, determine:
a. IDQ.
b. VGSQ.
c. IDSS.
d. VD.
e. VDS.
LASTPROBLEMS
H1 HEAD 475
3V
FIG. 7.80 FIG. 7.81 FIG. 7.82

Problems 6, 7, and 38. Problem 8. Problem 9.

a. ID.
b. VDS.
c. VD.
d. VS.
*11. Find VS for the network of Fig. 7.84.
⫺4 V
FIG. 7.83 FIG. 7.84

7.4 Voltage-Divider Biasing

a. VG.
b. IDQ and VGSQ.
c. VD and VS.
d. VDSQ.
13. a. Repeat Problem 12 with RS = 0.51 k⍀ (about 50% of the value of that of Problem 12).
What is the effect of a smaller RS on IDQ and VGSQ?
b. What is the minimum possible value of RS for the network of Fig. 7.85?
14. For the network of Fig. 7.86, VD = 12 V. Determine:
a. ID.
b. VS and VDS.
c. VG and VGS.
d. VP.
476 FET
SEMICONDUCTOR
BIASING 18 V
DIODES
ID
2 kΩ
VD = 12 V
+
VG
12 V VDS IDSS = 8 mA
680 kΩ +
VGS VS
–
–
110 kΩ
0.68 kΩ
FIG. 7.85 FIG. 7.86

15. Determine the value of RS for the network of Fig. 7.87 to establish VD = 10 V.
16 V
RD 2 k⍀
R1 36 k⍀
VD = 10 V
IDSS = 12 mA
VP = –8 V
R2 12 k⍀ RS
FIG. 7.87
Problem 15.
7.5 Common-Gate Configuration
a. IDQ and VGSQ.
b. VDS and VS.
*17. Given VDS = 4 V for the network of Fig. 7.89, determine:
a. ID.
20 V
b. VD and VS.
c. VGS.
1.2 kΩ
⫹2 V
FIG. 7.88 FIG. 7.89

7.6 Special Case: VGSQ ⴝ 0 V LASTPROBLEMS
H1 HEAD 477
18. For the network of Fig. 7.90.
a. Find IDQ.
b. Determine VDQ and VDSQ.
c. Find the power supplied by the source and dissipated by the device.
19. Determine VD and VGS for the network of Fig. 7.91 using the provided information.
18 V
RD 1.8 kΩ
ID
+ VD 4V
I DSS = 4 mA
VDS
VP = –2 V 1.8 k⍀ 1 k⍀
– 16 V
–
VGS
+ IDSS = 4 mA
3.6 k⍀ VP = –6 V
1.2 kΩ
1.2 k⍀
FIG. 7.90 FIG. 7.91

7.7 Depletion-Type MOSFETs

20. For the self-bias configuration of Fig. 7.92, determine:
a. IDQ and VGSQ.
b. VDS and VD.
a. IDQ and VGSQ.
b. VDS and VS.
FIG. 7.92 FIG. 7.93

7.8 Enhancement-Type MOSFETs

a. IDQ.
b. VGSQ and VDSQ.
c. VD and VS.
d. VDS.
23. For the voltage-divider configuration of Fig. 7.95, determine:
a. IDQ and VGSQ.
b. VD and VS.
478 FET
SEMICONDUCTOR
BIASING 24 V
DIODES
2.2 kΩ
10 MΩ ID
Q
VGS(Th) = 3 V
I D(on) = 5 mA
+ VGS(on) = 6 V
VGS
Q
–
6.8 MΩ
0.75 kΩ
FIG. 7.94 FIG. 7.95

7.10 Combination Networks

a. VG.
b. VGSQ and IDQ.
c. IE.
d. IB.
e. VD.
f. VC.
*25. For the combination network of Fig. 7.97, determine:
a. VB and VG.
b. VE.
c. IE, IC, and ID.
d. IB.
e. VC, VS, and VD.
f. VCE.
g. VDS.
VS ,VC
VG IB
VE
FIG. 7.96 FIG. 7.97

7.11 Design LASTPROBLEMS
H1 HEAD 479
*26. Design a self-bias network using a JFET transistor with IDSS = 8 mA and VP = - 6 V to have
a Q-point at IDQ = 4 mA using a supply of 14 V. Assume that RD = 3RS and use standard
values.
*27. Design a voltage-divider bias network using a depletion-type MOSFET with IDSS = 10 mA
and VP = - 4 V to have a Q-point at IDQ = 2.5 mA using a supply of 24 V. In addition, set
VG = 4 V and use RD = 2.5RS with R1 = 22 M⍀. Use standard values.
28. Design a network such as appears in Fig. 7.39 using an enhancement-type MOSFET with
VGS(Th) = 4 V and k = 0.5 * 10-3 A>V2 to have a Q-point of IDQ = 6 mA. Use a supply of
16 V and standard values.
7.12 Troubleshooting
*29. What do the readings for each configuration of Fig. 7.98 suggest about the operation of the
network?
FIG. 7.98
Problem 29.
*30. Although the readings of Fig. 7.99 initially suggest that the network is behaving properly,
determine a possible cause for the undesirable state of the network.
*31. The network of Fig. 7.100 is not operating properly. What is the specific cause for its failure?
FIG. 7.99 FIG. 7.100

480 FET
SEMICONDUCTOR
BIASING 7.13 p-Channel FETs
DIODES 32. For the network of Fig. 7.101, determine:
a. IDQ and VGSQ.
b. VDS.
c. VD.
a. IDQ and VGSQ.
b. VDS.
c. VD.
FIG. 7.101 FIG. 7.102

7.14 Universal JFET Bias Curve

34. Repeat Problem 1 using the universal JFET bias curve.

38. Perform a PSpice Windows analysis of the network of Problem 1.
39. Perform a PSpice Windows analysis of the network of Problem 6.
40. Perform a Multisim analysis of the network of Problem 16.
41. Perform a Multisim analysis of the network of Problem 33.

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48 SEMICONDUCTOR COMMON CATHODE

DIODES PIN # FUNCTION

1.18 COMPUTER ANALYSIS

FIG. 1.55 FIG. 1.56

1.4 Energy Levels

1.5 n-Type and p-Type Materials

1.6 Semiconductor Diode

1.7 Ideal versus Practical

1.8 Resistance Levels

1.9 Diode Equivalent Circuits

1.10 Transition and Diffusion Capacitance

1.11 Reverse Recovery Time

1.12 Diode Specification Sheets

1.15 Zener Diodes

1.16 Light-Emitting Diodes

FIG. 2.153 FIG. 2.154

6. Determine Vo and ID for the networks of Fig. 2.156.

*7. Determine the level of Vo for each network of Fig. 2.157.

*8. Determine Vo and ID for the networks of Fig. 2.158.

2.4 Parallel and Series–Parallel Configurations

*11. Determine Vo and I for the networks of Fig. 2.161.

FIG. 2.162 FIG. 2.163

2.5 AND/OR Gates

FIG. 2.164 FIG. 2.165

20. Determine the level of Vo for the gate of Fig. 2.166.

FIG. 2.166 FIG. 2.167

2.6 Sinusoidal Inputs; Half-Wave Rectification

FIG. 2.168 FIG. 2.169

FIG. 2.170 FIG. 2.171

2.7 Full-Wave Rectification

*39. For the network of Fig. 2.183:

*40. Design a clamper to perform the function indicated in Fig. 2.184.

*41. Design a clamper to perform the function indicated in Fig. 2.185.

FIG. 2.187 FIG. 2.188

2.11 Voltage-Multiplier Circuits

3.3 Transistor Operation

3.5 Common-Emitter Configuration

3.6 Common-Collector Configuration

3.7 Limits of Operation

3.9 Transistor Testing

4.21 COMPUTER ANALYSIS

FIG. 4.113 FIG. 4.114

Fixed-Bias Configuration Although the voltage-divider bias network is relatively

FIG. 4.115 FIG. 4.116

2. Given the information appearing in Fig. 4.119, determine:

FIG. 4.119 FIG. 4.120

4.4 Emitter-Bias Configuration

FIG. 4.123 FIG. 4.124

4.5 Voltage-Divider Bias Configuration

FIG. 4.125 FIG. 4.126

18. Given the information appearing in Fig. 4.127, determine:

4.6 Collector-Feedback Configuration

28. For the network of problem 27

FIG. 4.130 FIG. 4.131

FIG. 4.132 FIG. 4.133

4.7 Emitter-Follower Configuration

4.8 Common-Base Configuration

FIG. 4.136 FIG. 4.137 FIG. 4.138

4.9 Miscellaneous Bias Configurations

FIG. 4.139 FIG. 4.140

40. Given VC = 8 V for the network of Fig. 4.140, determine:

4.11 Design Operations

4.12 Multiple BJT Networks