TDA9103

DEFLECTION PROCESSOR FOR MULTISYNC MONITOR

..
HORIZONTAL T his IC, combined with TDA9205 (RG B preamp),
STV9420/21 or 22 (O.S.D. processor), ST7271 (micro

.. DUAL PLL CONCEPT

150kHz MAXIMUM FREQUENCY controller) and TDA8172 (vertical booster), allows to real-
ize very simple and high quality multimodes or multisync

.. SELF-ADAPTIVE (EX : 30 TO 85kHz)

X-RAY PROTECTION INPUT
DC ADJUSTABLE DUTY-CYCLE
monitors.

.. INTERNAL 1st PLL LOCK/UNLOCK IDENTIFICA-

TION

.. 4 OUTPUTS FOR S-CORRECTION

WIDE RANGE DC CONTROLLED H-POSITION
ON/OFF SWITCH (FOR PWR MANAGEMENT)
TWO H-DRIVE POLARITIES

..
VERTICAL

. VERTICAL RAMP GENERATOR

50 TO 150Hz AGC LOOP
SHRINK42
(Plastic Package)

. DC CONTROLLED V-AMP, V-POS, S-AMP AND S-

CENTERING
ON/OFF SWITCH ORDER CODE : TDA9103

.
B+ REGULATOR

.. INTERNAL PWM GENERATOR FOR B+ CURRENT

MODE STEP-UP CONVERTER
DC ADJUSTABLE B+ VOLTAGE
PIN CONNECTIONS

PLL2C 1 42 ISENSE

. OUTPUT PULSES SYNCHRONISED ON HORIZON-

TAL FREQUENCY
INTERNAL MAXIMUM CURRENT LIMITATION
H-DUTY

HFLY
2

3
41

40
COMP

REGIN

EWPCC
. VERTICAL PARABOLA GENERATOR WITH DC
CONTROLLED KEYSTONE AND AMPLITUDE
HGND

HREF
4

5
39

38
B+-ADJ

KEYST

.
S4 6 37 E/W-AMP
GENERAL S3 7 36 E/WOUT

.. ACCEPT POS. OR NEG. H AND V SYNC POLARI-

TIES
SEPARATED H AND V TTL INPUT
SAFETY BLANKING OUTPUT
S2

S1

C0
8

10
35

34

33
PLL1INHIB

VSYNC

V-POS

R0 11 32 VDCOUT
DESCRIPTION PLL1F 12 31 V-AMP
The TDA9103 is a monolithic integrated circuit assembled 13 30
HLOCK-CAP VOUT
in a 42 pins shrunk dual in line plastic package.
FH-MIN 14 29 VS-CENT
This IC controls all the functions related to the horizontal
and vertical deflection in multimodes or multisync monitors. H-POS 15 28 VS-AMP
As can be seen in the block diagram, the TDA9103 includes XRAY-IN 16 27 VCAP
the following functions :
HSYNC 17 26 VREF
- Positive or Negative sync polarities,
- Auto-sync horizontal processing, VCC 18 25 VAGCCAP
- H-PLL lock/unlock identification, GND 19 24 VGND
- Auto-sync Vertical processing, H-OUTEM 20 23 SBLKOUT
- East/West signal processing block,
9103-01.AI

H-OUTCOL 21 22 B+OUT
- B+ controller,
- Safety blanking output.

May 1996 1/27

TDA9103

PIN-OUT DESCRIPTION
Pin N° Name Function
1 PLL2C Second PLL Loop Filter
DC Control of Horizontal Drive Output Pulse Duty-cycle.
2 H-DUTY If this pin is grounded, the horizontal and vertical outputs are inhibited. By connecting a
capacitor on this pin a soft-start function may be realized on h-drive output.
3 H-FLY Horizontal Flyback Input (positive Polarity)
4 H-GND Horizontal Section Ground. Must be connected only to components related to H blocks.
5 H-REF Horizontal Section Reference Voltage. Must be filtered by capacitor to Pin 4
6 S4 Hor S-CAP Switching
7 S3 Hor S-CAP Switching
8 S2 Hor S-CAP Switching
9 S1 Hor S-CAP Switching
10 C0 Horizontal Oscillator Capacitor. To be connected to Pin 4.
11 R0 Horizontal Oscillator Resistor. To be connected to Pin 4.
12 PLL1F First PLL Loop Filter. To be connected to Pin 4.
First PLL Lock/Unlock Time Constant Capacitor. Capacitor filtering the frequency change
13 HLOCK-CAP detected on Pin13. When frequency is changing, a blanking pulse is generated on Pin 23, the
duration of this pulse is proportionnal to the capacitor on Pin 13. To be connected to Pin 4.
DC Control for Free Running Frequency Setting. Comming from DAC output or DC voltage
14 FH-MIN
generated by a resistor bridge connected between Pin 5 and 4.
15 H-POS DC Control for Horizontal Centering
16 XRAY-IN X-RAY Protection Input (with internal latch function)
17 H-SYNC TTL Horizontal Sync Input
18 VCC Supply Voltage (12V Typical)
19 GND Ground
20 H-OUTEM Horizontal Drive Output (emiter of internal transistor). See description on pages 15-16.
21 H-OUTCOL Horizontal Drive Output (open collector of internal transistor). See description on pages 15-16.
22 B+ OUT B+ PWM Regulator Output
Safety Blanking Output. Activated during frequency changes, when X-RAY input is
23 SBLK OUT
triggered or when VS is too low.
24 VGND Vertical Section Signal Ground
25 VAGCCAP Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator
26 VREF Vertical Section Reference Voltage
27 VCAP Vertical Sawtooth Generator Capacitor
28 VS-AMP DC Control of Vertical S Shape Amplitude
29 VS-CENT DC Control of Vertical S Centering
30 VOUT Vertical Ramp Output (with frequency independant amplitude and S-correction)
31 V-AMP DC Control of Vertical Amplitude Adjustment
32 VDCOUT Vertical Position Reference Voltage Output Temperature Matched with V-AMP Output
33 V-POS DC Control of Vertical Position Adjustment
34 VSYNC Vertical TTL Sync Input
35 PLL1INHIB TTL Input for PLL1 Output Current Inhibition (To be used in case of comp sync input signal)
36 E/WOUT East/West Pincushion Correction Parabola Output
37 E/W-AMP DC Control of East/West Pincushion Correction Amplitude
38 KEYST DC Control of Keystone Correction
39 B+ ADJ DC Control of B+ Adjustment
40 REGIN Regulation Input of B+ Control Loop
9103-01.TBL

41 COMP B+ Error Amplifier Output for Frequency Compensation and Gain Setting
42 ISENSE Sensing of External B+ Switching Transistor Emiter Current

2/27
 TDA9103

BLOCK DIAGRAM

HLOCK-CAP

H-OUTCOL
PLL1INHIB

H-OUTEM
H-DUTY
FH-MIN

PLL2C
H-POS
PLL1F

HFLY
R0
C0

S4
S3
S2

S1
35 15 12 11 10 14 13 3 1 2 20 21 6 7 8 9

INPUT 1s t P HASE 2nd P HASE P ULSE OUTP UT H

HS YNC 17 INTERFACE COMP VCO COMP S HAPER BUFFER FREQUENCY

23 S BLKOUT

LOCK
DETECT
39 B+-ADJ
XRAY-IN 16
VREF
HREF 5 42 IS ENSE
H-VREF
HGND 4
R
BANDGAP SAFETY EA 22 B+OUT
P ROCES S OR S
VREF 26
V-VREF
VGND 24 VCC Outputs
Inhibition 41 COMP

40 REGIN

P ARABOLA
GENERATOR 36 E/WOUT

INPUT VERTICAL S
VSYNC 34 INTERFACE OS CILLATOR CORRECTION
TDA9103
19 18 27 25 29 28 33 31 30 32 38 37
V-AMP

VDCOUT
VOUT
GND

VCC

VCAP

KEYST
VS-AMP

E/W-AMP
VAGCCAP

VS-CENT

V-POS

9103-02.EPS

3/27
TDA9103

QUICK REFERENCE DATA

Parameter Value Unit
Horizontal Frequency Range 15 to 150 kHz
Autosynch Frequency Range (for Given R0, C0) 1 to 3.7 FH
± Hor Sync Polarity Input YES
Compatibility with Composite Sync on H-SYNC Input YES (1)
Lock/Unlock Identification on 1st PLL YES
DC Control for H-Position YES
X-RAY Protection YES
Hor DUTY Adjust YES
Stand-by Function YES
Hor S-CAP Switching Control YES
Two Polarities H-Drive Outputs YES
Supply Voltage Monitoring YES
PLL1 Inhibition Possibility YES
Safety Blanking Output YES
Vertical Frequency Range 35 to 200 Hz
Vertical Autosync Range (for a Given Capacitor Value) 50 to 150 Hz
Vertical -S- Correction YES
Vertical -C- Correction YES
Vertical Amplitude Adjustment YES
Vertical Position Adjustment YES
Automatic B+ Adjustment Control Loop YES
B+ Adjustment YES
East/West Parabola Output YES
PCC (Pin Cushion Correction) Amplitude Adjustment YES
Keystone Adjustment YES
Reference Voltage YES (2)
Mode Detection NO

9103-02.TBL
Dynamic Focus NO
Blanking Output NO
Notes : 1. See application diagram.
2. One for Horizontal section and one for Vertical section.

4/27
 TDA9103

ABSOLUTE MAX RATING

Symbol Parameter Value Unit
VCC Supply Voltage (Pin 18) 13.5 V
VIN Max Voltage on Pins 2, 14, 15, 28, 29, 31, 33, 37, 38, 39 8 V
Pin 3 1.8
Pins 17, 34 6
Pin 40 8
Pin 42 8
Pin 16 5.5
VESD ESD Succeptibility
Human Body Model, 100pF Discharge through 1.5kΩ 2 kV
EIAJ Norm, 200pF Discharge through 0Ω 300 V
Tstg Storage Temperature -40, +150 °C

9103-03.TBL
Tj Max Operating Junction Temperature 150 °C
Toper Operating Temperature 0, +70 °C

THERMAL DATA

9103-04.TBL
Symbol Parameter Value Unit
Rth (j-a) Junction-Ambient Thermal Resistance Max. 65 °C/W

HORIZONTAL SECTION
Operating conditions
Symbol Parameter Test conditions Min. Typ. Max. Unit
VCO
R0min Oscillator Resistor Min Value Pin 11 6 kΩ
C0min Oscillator Capacitor Min Value Pin 10 390 pF
Fmax Maximum Oscillator Frequency 150 kHz
HsVR Horizontal Sync Input Voltage Range Pin 17 0 5.5 V
INPUT SECTION
MinD Minimum Input Pulses Duration Pin 17 0.7 µS
Mduty Maximum Input Signal Duty Cycle Pin 17 25 %
OUTPUT SECTION
I3m Maximum Input Peak Current on Pin 3 2 mA
IS1 to IS4 Maximum Current on S1 to S4 Outputs Pins 6 to 9 0.5 mA
VS1 to VS4 Maximum Voltage on S1 to S4 Outputs Pins 6 to 9 VCC V
HOI1 Horizontal Drive Output Max Current Pin 20, sourced current 20 mA
HOI2 Horizontal Drive Output Max Current Pin 21, sunk current 20 mA
9103-05.TBL

DC CONTROL VOLTAGES
DCadj DC Voltage Range on DC Controls VREF-H = 8V, Pins 2-14-15 2 6 V

5/27
TDA9103

Electrical Characteristics (VCC = 12V, Tamb = 25°C)

Symbol Parameter Test conditions Min. Typ. Max. Unit
SUPPLY AND REFERENCE VOLTAGES
VCC Supply Voltage Pin 18 10.8 12 13.2 V
ICC Supply Current Pin 18, See Figure 1 40 60 mA
VREF-H Reference Voltage for Horizontal Section Pin 5, I = 2mA 7.4 8 8.6 V
IREF-H Max Sourced Current on VREF-H Pin 5 5 mA
VREF-V Reference Voltage for Vertical Section Pin 26, I = 2mA 7.4 8 8.6 V
IREF-V Max Sourced Current on VREF-V Pin 26 5 mA
INPUT SECTION/PLL1
VINTH Hor Input Threshold Voltage Pin 17 Low level voltage 0.8 V
High level voltage 2 V
VVCO VCO Control Voltage Range VREF-H = 8V, Pin 12 1.6 6.2 V
VCOG VCO Gain, dF/dV Pin 12 R0 = 6.49kΩ, C0 = 680pF 15 kHz/V
Hph Horizontal Phase Adj Range (Pin 15) % of Hor period ±12.5 %
FFadj Free Running Frequency Adj Range (Pin 14) Without H-sync Signal ±20 %
S1th VCO Input Voltage for S1 Switching Pin 12 voltage, V REF-H = 8V 1.85 2 2.25 V
S2th VCO Input Voltage for S2 Switching Pin 12 voltage, V REF-H = 8V 2.25 2.4 2.65 V
S3th VCO Input Voltage for S3 Switching Pin 12 voltage, V REF-H = 8V 2.9 3 3.3 V
S4th VCO Input Voltage for S4 Switching Pin 12 voltage, V REF-H = 8V 3.5 3.7 3.9 V
F0 Free Running Frequency V14 = VREF/2 23.5 25 27.5 kHz
R0 = 6.49kΩ
C0 = 680pF
VS1D to Low Level Output Voltage on S1 to S4 Outputs Pins 6 to 9, I = 0.5mA 0.2 0.4 V
VS4D
CR PLL1 Capture Range (F0 = 27kHz) See conditions on Figure 1 kHz
Fh Min 28
Fh Max 94
PLLinh PLL 1 Inhibition (Pin 35) V
PLL ON V35 0.8
PLL OFF V35 2
SECOND PLL AND HORIZONTAL OUTPUT SECTION
FBth Flyback Input Threshold Voltage Pin 3 0.65 0.75 V
Hjit Horizontal Jitter 100 ppm
HDmin Minimum Hor Drive Output Duty-cycle Pin 20 or 21, V2 = 2V 30 35 %
HDmin Maximum Hor Drive Output Duty-cycle Pin 20 or 21, V2 = 6V 45 50 %
HDvd Horizontal Drive Low Level Output Voltage V21-V20, Iout = 20mA, 1.1 1.7 V
Pin 20 to GND
HDem Horizontal Drive High Level Output Voltage Pin 21 to VCC, IOUT = 20mA 9.5 10 V
(output on Pin 20)
XRAYth X-RAY Protection Input Threshold Voltage Pin 16 1.6 1.8 V
ISblkO Maximum Output Current on Safety Blanking I23 10 mA
Output
VSblkO Low-Level Voltage on Safety Blanking Output V23 with I23 = 10mA 0.25 0.5 V
Vphi2 Internal Clamping Voltage on 2nd PLL Loop Vmin 1.6 V
Filter Output (Pin 1) Vmax 3.2 V
9103-06.TBL

VOFF Pin 2 Threshold Voltage to Stop H-out, V-out V2 1 V

B+out and to Activate S-BLK.OFF Mode
when V2 < VOFF

6/27
 TDA9103

B+ SECTION
Operating Conditions
Symbol Parameter Test conditions Min. Typ. Max. Unit
EAOI Maximum Error Amplifier Output Current Sourced by Pin 41 0.5 mA
Sunk by Pin 41 2 mA

9103-07.TBL
FeedRes Minimum Feedback Resistor Resistor between Pins 40 5 kΩ
and 41

Electrical Characteristics (VCC = 12V, Tamb = 25°C)

Symbol Parameter Test conditions Min. Typ. Max. Unit
OLG Error Amplifier Open Loop Gain At low frequency 85 dB
(see Note 1)
UGBW Unity Gain Bandwidth (see Note 1) 6 MHz
IRI Regulation Input Bias Current Current sourced by 0.2 µA
Pin 40 (PNP base)
EAOI Maximum Guaranted Error Amplifier Current sourced by Pin 41 0.5 mA
Output Current Current sunk by Pin 41 2 mA
CSG Current Sense Input Voltage Gain Pin 42 3
MCEth Max Curent Sense Input Threshold Voltage Pin 42 1.2 V
ISI Current Sense Input Bias Current Current sunk by Pin 42 1 µA
(NPN base)
Tonmax Maximum External Power Transistor on Time % of H-period 75 %
@ f0 = 27kHz
B+OSV B+ Output Low Level Saturation Voltage V22 with I22 = 10mA 0.25 V
IVREF Internal Reference Voltage On error amp (+) input for 4.9 V

9103-08.TBL
V39 = 4V
VREFADJ Internal Reference Voltage Adjustment Range 2V < V39 < 6V ±14 %

EAST WEST PARABOLA GENERATOR

Electrical Characteristics (VCC = 12V, Tamb = 25°C)
Symbol Parameter Test conditions Min. Typ. Max. Unit
Vsym Parabola Symetry Adjustment Capability (for See Figure 2 ; internal V
Keystone Adjustment ; with Pin 38) voltage
V38 = 2V 3.2
V38 = 4V 3.5
V38 = 6V 3.8
Kadj Keystone Adjustment Capability See Figure 2 ; V37 = 4V
B/A ratio V38 = 2V 2.3
A/B ratio V38 = 6V 2.0
9103-09.TBL

Paramp Parabola Amplitude Adjustment Capability V38 = 4.3V, V28 = 2V V

Maximum Amplitude on Pin 36 V37 = 2V 3.3 3.8 4.3
Maximum Ratio between Max and Min 2V < V37 < 6V 2.4 3

7/27
TDA9103

VERTICAL SECTION
Operating Conditions

9103-10.TBL
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSVR Vertical Sync Input Voltage Range On Pin 34 0 5.5 V

Electrical Characteristics (VCC = 12V, Tamb = 25°C)

Symbol Parameter Test conditions Min. Typ. Max. Unit
IBIASP Pin 23-28-29 Bias Current (Current Sourced For V23-28-29 = 2V 2 µA
by PNP Base)
IBIASN Pin 31 Bias Current (Current Sunk by NPN For V31 = 6V 0.5 µA
Base)
VSth Vertical Sync Input Threshold Voltage Pin 34; High-level 2 V
Low-level 0.8 V
VSBI Vertical Sync Input Bias Current (Current V34 = 0.8V 1 µA
Sourced by PNP Base)
VRB Voltage at Ramp Bottom Point On Pin 27 2/8 VREF-V
VRT Voltage at Ramp Top Point (with Sync) On Pin 27 5/8 VREF-V
VRTF Voltage at Ramp Top Point (without Sync) On Pin 27 VRT-0.1 V
IR27 Output Current Range on Pin 27 during V28 = 2V (Note 2),
Ramp Charging Time. Current to Charge 2V < V27 < 5V
Capacitor between Pin 27 and Ground Min current 15 20 µA
Max current 100 135 µA
VSW Minimum Vertical Sync Pulse Width Pin 34 5 µS
VSmDut Vertical Sync Input Maximum Duty-cycle Pin 34 15 %
VSTD Vertical Sawtooth Discharge Time Duration On Pin 27, with 150nF cap 85 µS
VFRF Vertical Free Running Frequency (V28 = 2V) Measured on Pin 27 100 Hz
Cosc (Pin27) = 150nF
ASFR AUTO-SYNC Frequency Range With C27 = 150nF ±5% 50 150 Hz
(see Note 3)
RATD Ramp Amplitude Thermal Drift On Pin 30 (see Note 1) 100 ppm/°C
(0°C < Tamb < 70°C)
RAFD Ramp Amplitude Drift Versus Frequency V31 = 6V, C27 = 150nF 200 ppm/Hz
50Hz < F < 120Hz
Rlin Ramp Linearity on Pin 27 ∆I27/I 27 V28 = 2V, V25 = 4.3V 0.5 %
2.5V < V27 < 4.5V
Rload Minimum Load on Pin 25 for less than 1% 50 MΩ
Vertical Amplitude Drift
Vpos Vertical Position Adjustment Range Voltage V33 = 2V 3.2 3.3 V
on Pin 32 V33 = 4V 3.5 V
V33 = 6V 3.65 3.8 V
IVPOS Max Current on Vertical Position Control ±2 mA
Output (Pin 32)
Vor Vertical Output Voltage Range (on Pin 30) V31 = 2V 2 2.2 V
(Peak to Peak Voltage on Pin 30) V31 = 4V 3 V
V31 = 6V 3.75 4 V
VOUTDC DC Voltage on Vertical Output (Pin30) See Note 4 7/16 VREF-V
V0I Vertical Output Maximum Output Current On Pin 30 ±5 mA
dVS Max Vertical S-Correction Amplitude ∆V/V30pp at T/4 -4 %
(V28 = 2V Inhibits S-CORR; V28 = 6V gives ∆V/V30pp at 3T/4 +4 %
Maximum S-CORR) (see Figure 3)
9103-11.TBL

Ccorr C-Correction Adjustment Range Voltage on V29 = 2V 3 V

Pin 27 for Maximum Slope on the Ramp V29 = 4V 3.5 V
(with S-Correction) (see Figure 4) V29 = 6V 4 V
Notes : 1. These parameters are not tested on each unit. They are measured during our internal qualification procedure which includes
characterization on batches comming from corners of our processes and also temperature characterization.
2. When 2V are applied on Pin 28 (Vertical S-Correction control), then the S-Correction is inhibited, consequently the sawtooth have
a linear shape.
3. It is the frequency range for which the VERTICAL OSCILLATOR will automatically synchronize, using a single capacitor value on
Pin 27 and with a constant ramp amplitude.
4. Typically 3.5V for Vertical reference voltage typical value (8V).

8/27
 S6 12V
10nF 12V

1.8kΩ
6.49kΩ
680pF

15 kΩ
15 kΩ
15 kΩ
15 kΩ

4.7kΩ
1% 220nF 22nF
4.7 F
Figure 1 : Testing Circuit

35 15 12 11 10 14 13 3 1 2 20 21 6 7 8 9

INPUT 1st PHASE 2nd PHASE PULSE OUTPUT H

17 INTERFACE COMP VCO COMP SHAPER BUFFER FREQUENCY

4.7k Ω
23 12V

LOCK
DETECT
39
16
VREF
5 42
2.2 µF H-VREF
R 3.9k Ω
4 EA
SAFETY 22 12V
BANDGAP S
PROCESSOR 470pF
26
2.2 µF V-VREF 10kΩ
VCC Outputs
24 41
Inhibition
47kΩ
40

10k Ω
PARABOLA
GENERATOR 36

INPUT VERTICAL S
34 INTERFACE OSCILLATOR CORRECTION
TDA9103
19 18 27 25 29 28 33 31 30 32 38 37
150nF 470nF
12V S5 1% 1%

9/27
TDA9103

9103-54.EPS
TDA9103

Figure 2 : Keystone Adjustment

V36

A V38 = 2V B

V38 = 4V

V38 = 6V

V27
3.8
3.5
3.2

9103-03.AI
Figure 3 : S Amplitude Adjustment
V30

∆V

V30pp

0 T/4 T/2 3T/4 T ∆V increase when V28 increase.

9103-04.AI
∆V = 0 when V28 = 0.

Figure 4 : C Correction Adjustment

V27

4.0V
3.5V
3.0V
9103-05.AI

0 T

10/27

OPERATING DESCRIPTION
GENERAL CONSIDERATIONS
Power Supply
The typical value of the power supply voltage VCC
is 12V. Perfect operation is obtained if VCC is main-
tained in the limits : 10.8V → 13.2V.
In order to avoid erratic operation of the circuit
during the transient phase of VCC switching on, or
switching off, the value of VCC is monitored and the
outputs of the circuit are inhibited if it is too low.
In order to have a very good powersupplyrejection,
the circuit is internally powered by several internal
voltage references (The unique typical value of
which is 8V). Two of these voltage references are
externally accessible, one for the vertical part and
one for the horizontal part. These voltage refer-
ences can be used for the DC control voltages
applied on the concerned pins by the way of poten-
tiometers or digital to analog converters (DAC’s).
Furthermore it is possible to filter the a.m. voltage
references by the use of external capacitor con-
nected to ground, in order to minimize the noise
and consequently the ”jitter” on vertical and hori-
zontal output signals.
DC Control Adjustments
The circuit has 10 adjustment capabilities : 3 for the
horizontal part, 1 for the SMPS part, 2 for the E/W
correction, 4 for the vertical part.
The corresponding inputs of the circuit has to be
driven with a DC voltage typically comprised be-
tween 2 and 6V for a value of the internal voltage
reference of 8V.
More precisely, the control voltages have to be
maintained between VREF/4 and 3/4 ⋅ VREF. The
application of control voltages outside this range is
not dangerousfor the circuit but the good operation
is not guaranted (except for Pin 2 : duty cycle
adjusment. See outputs inhibition paragraph).
Figure 5 : Example of Practical DC Control
Voltage Generation
VREF
10kΩ
22kΩ DC Control Voltage
10kΩ
9103-06.AI
TDA9103
The input currents of the DC control inputs are
typically very low (about a few µA). Depending on
the internal structure of the inputs, the input cur-
rents can be positive or negative (sink or source).
HORIZONTAL PART
Input section
The horizontal input is designed to be sensitive to
TTL signals typically comprised between 0 and 5V.
The typical threshold of this input is 1.6V. This input
stage uses an NPN differential stage and the input
current is very low.
Concerning the duty cycle of the input signal, the
following signals may be applied to the circuit.
Figure 6
Z
T
Z
9103-07.AI
Using internal integration, both signals are recog-
nized on condition that Z/T ≤ 25%. Synchronisation
occurs on the leading edge of the rectified signal.
The minimum value of Z is 0.7µs.
Figure 7 : Input Structure
HSYNC 1.6V
9103-08.AI
PLL1
The PLL1 is composed of a phase comparator, an
external filter and a Voltage Controlled Oscillator
(VCO).
The phase comparatoris a ”phase frequency” type,
designed in CMOS technology. This kind of phase
detector avoids locking on false frequencies. It is
followed by a ”charge pump”, composed of 2 cur-
rent sources sink and source (I = 1mA typ.)
11/27
TDA9103

Figure 8 : Principle Diagram

C Lockdet Eini Filter R0 C0
13 35 12 11 10

LOCKDET

High
Horizontal INPUT CHARGE PLL
17 COMP1 VCO
Input INTERFACE PUMP INHIBITION
E2 Low Horizontal
Adjust
15 OSC

9103-09.AI
PHASE 3.2V
ADJUST

The dynamic behaviour of the PLL is fixed by an
external filter which integrates the current of the
charge pump. A ”CRC” filter is generally used.
PLL1 is inhibited by applying a high level on Pin 35
(PLLinhib) which is a TTL compatible input. The inhibi-
tion results from the opening of a switch located be-
tween the charge pump and the filter (see Figure 8).
The VCO uses an external RC network. It delivers
a linear sawtooth obtained by charge and dis-
charge of the capacitor, by a current proportionnal
to the current in the resistor. typical thresholds of
sawtooth are 1.6V and 6.4V.
Figure 9
PLL1F
12
9103-10.AI
The control voltage of the VCO is typically com-
prised between 1.6V and 6V. The theoretical fre-
quency range of this VCO is in the ratio 1 → 3.75,
but due to spread and thermal drift of external
components and the circuit itself, the effective fre-
quency range has to be smaller (e.g. 30kHz →
82kHz). Inthe absenceof synchronisationsignal the
control voltage is equal to 1.6V typ. and the VCO
oscillates on its lowest frequency (free frequency).
The synchro frequencyhas to be always higher than
the free frequency and a margin has to be taken. As
an example for a synchro range from 30kHz to
82kHz, the suggested free frequency is 27kHz. To
compensate for the spread of external components
and of the circuit itself, the free frequency may be
adjusted by a DC voltage on Pin 14 (Fmin adjust)
(see Figure10 for details).
The PLL1 ensures the coincidence between the
leading edge of the synchro signal and a phase
reference obtained by comparison between the
sawtooth of the VCO and an internal DC voltage

adjustable between 2.4V and 4V (by Pin 15). So a

±45° phase adjustment is possible.
Figure 10 : Details of VCO and Fhmin Adjustment

FHMINADJ
I0
14 6.4V
2
RS
a I0 FLIP FLOP

Loop
12
Filter 4 I0 1.6V
(0.8V < a < 1.2V)
2
11
(1.6V < V12 < 6V) 10 6.4V

R0 C0
9103-58.EPS

1.6V
0 0.75T T

12/27
 TDA9103

Figure 11 : Safety Functions Block Diagram

V CC Checking

V CC 30 -
SMPS Output
Inhibition
REF 30 +

XRAY Protection
XRAY 30 S
Q H Output
V CCoff 30 R Inhibition

PLL-Unloocked 30

V Output
Inhibition Inhibition

H-duty Cycle 30 -

1V 30 +

Flyback 30 - Blanking

9103-21.AI
0.7V 30 +

Figure 12 : LOCK/UNLOCK Block Diagram

From 20kΩ H-Lock CAP

A NOR2 23 SBLK OUT
Phase NOR1 13 B

9103-59.EPS
Comparator 6.5V
220nF

The TDA9103 also includes a LOCK/UNLOCK ent from VCO,

identification block which sense in real-time - Between 4 and 8V when H-SYNC frequency
wheather the PLL is locked on the incomming = VCO frequency but not in phase,
horizontal sync signal or not. The resulting informa- - Near to 8V when PLL is locked.
tion is available on safety blanking output (Pin 23) It is important to notice that Pin 13 is not an output
where it is mixed with others information (see Fig- pin and must only be used for filtering purpose (see
ure 11). The block diagram of the LOCK/UNLOCK Figure 12).
function is described in Figure 12.
The NOR1 gate is receiving the phase comparator Figure 13 : PLL1 Timing Diagram
output pulses (which also drives the charge pump). H Osc
When the PLL is locked, on point A there is a very Sawtooth
0.75T 0.25T
small negative pulse (100ns) at each horizontal
cycle, so after R-C filter, there is a high level on Pin 6.4V
13 which force SBLK to high level (provided other 2.4V<Vb<4V
inputs on NOR2 are also at low level). Vb
When the PLL is unlocked, the 100ns negative 1.6V
pulse on A becomesmuch larger and consequently
the average level on Pin 13 will decrease. When it Phase REF1
reaches 6.5V, point B goes to high level forcing
H Synchro
NOR2 open collector output to ”0”.
Phase REF1 is obtained by comparison between the sawtooth
The status of Pin 13 is approximately the following : and a DC voltage adjustable between 2.4V and 4V. The PLL1
9103-16.AI

- Near 0V when there is no H-SYNC, ensures the exact coincidence between the signals phase REF
and HSYNS. A ± 45° phase adjustment is possible.
- Between 0 and 4V with H-SYNC frequency differ-
13/27
TDA9103

PLL2
Figure 14 : Dual PLL Block Diagram
C Lockdet Eini Filter R0 C0
13 35 12 11 10

LOCKDET HFREQ

High
Horizontal INPUT CHARGE PLL Freq
17 COMP1 VCO FAJUST 14
Input INTERFACE PUMP INHIBITION Adjust
E2 Low Horizontal
Adjust
15 OSC

Adjust Cap PHASE 3.2V

Rapcyc PH12 ADJUST
2 1
High E2
RAP CHARGE
COMP2 GENPULSE
CYC PUMP
Low E1 FLYBACK 3 Flyback
VA VB

LOGI 21 SortCOLL
PWM

9103-15.AI
PWM BUFFER
20 SortEM

The PLL2 ensures the coincidence between the ±0.5mA (typ.) output current.
leading edge of the shaped flyback signal and a The flyback input is composed of an NPN transistor.
phase reference signal obtained by comparison of This input has to be current driven. The maximum
the sawtooth of the VCO and a constant DC voltage recommanded input current is 2mA (see Fig-
(3.2V) (see Figure 15). ure 16).
Figure 15 : PLL2 Timing Diagram
Figure 16 : Flyback Input Electrical Diagram
H Osc
Sawtooth
0.75T 0.25T
400Ω
HFLY 3 Q1
6.4V
20kΩ
3.2V

1.6V
9103-11.AI

GND 0V
Flyback
Shapped Output Section
Flyback
The H-drive signal is transmitted to the output
Phase REF2 through a shaping block ensuring a duty cycle
adjustable from 30% to 50%. In order to ensure a
H Drive
reliable operation of the scanning power part, the
Ts
output is inhibited in the following circumstances :
Duty Cycle - VCC too low.
Phase REF2 is obtained by comparison between the sawtooth and
- Xray protection activated.
a 3.2V (constant). The PLL2 ensures the exact coincidence - During the flyback.
9103-57.AI

between the signals phase REF2 and the flyback signal. The duty - Output voluntarily inhibited.
cycle of H-drive is adjustable between 30% and 50%.
The output stage is composed of a Darlington NPN
The phase comparator of PLL2 is similar to the one bipolar transistor. Both the collector and the emitter
of PLL1, it is followed by a charge pump with a are accessible.

14/27
 TDA9103

Figure 17 : Output stage simplified diagram, The reset of this protection is obtained by VCC
showing the two possibilities of switch off.
connection
21 VCC S Correction. S Outputs
In the case where the ”S correction” of the horizon-
tal scanning is performed using capacitors, it is
necessary to switch capacitors when the frequency
changes.
20 H-DRIVE For this the outputs S1, 2, 3 and 4 (Pins 9, 8, 7 and
16) give an indication about the horizontalfrequency
by monitoring thecontrolvoltage of the VCO (Pin 12).
The switching of the S outputs occurs for the fol-
V CC lowing value of the control voltage.
S1 2V
S2 2.4V
21 VCC S3 3V
H-DRIVE S4 3.7V

The use of comparators with hysteresis avoids

9103-12.AI / 9103-13.AI

erratic switching of the Sout outputs if the control

voltage of the VCO remains very close to a switch-
20 ing reference level.

The output Darlington is in off-state when the power SMPS

scanning transistor is also in off-state.
The maximum output current is 20mA, and the
correspondingvoltage drop of the output darlington
is 1.1V typically.
It is evident that the power scanning transistor
cannot be directly driven by the integrated circuit.
An interface has to be designed between the circuit
and the power transistor which can be of bipolar or
MOS type.
Outputs inhibition : the application of a voltage
lower than 1V (typ.) on Pin 2 (duty cycle adjust)
inhibits the horizontal, vertical and SMPS outputs.
This is not memorised.
X-ray protection : the activation of the X-ray protec-
tion is obtained by application of a high level on the
X-ray input (>1.6V). Consequences of X-ray pro-
tection are :
- Inhibition of H drive output.
- Inhibition of SPMS output.
- Activation of safety blanking output.
This unit generates the supply voltage for the hori-
zontal scanning system. This supply voltage is
approximately proportional to the H frequency in
order to keep the scanning amplitude constant
when the frequency changes. More precisely the
amplitude regulation is obtained by detecting and
regulating the ”flyback” amplitude or EHT value.
The power supply is a step-up converter and it uses
the ”current-mode” regulation principle.
The power supply works in synchronism with the
horizontal scanning. The switching power transis-
tor (external to the TDA9103) is switched on at the
beginning of the positive slope of the horizontal
sawtooth. It is switched off as required by the
integrated regulator. The current in the switching
power transistor is monitored and limited, and the
ratio Ton/Ton+Toff of the power transistor is limited
to 75% typically providing a very good reliability to
the power supply.

15/27
TDA9103

Figure 18 : SMPS Block Diagram

ISENSE
H-FREQ
42

H-amp Reg-in S
39 40 Basc Buffer 22 SMPS
+ OUT
- R
EA -
VREF RAP CYC +
Clamp

9103-18.AI
41
Compensation

Figure 19 : SMPS Timing Diagram

0.75T 0.25T

6.4V

H Osc
Sawtooth
1.6V

SMPS Drive

9103-19.AI
Error Amplifier
SMPS Current Output (1.2V Max)

Figure 20 : H Scanning Amplitude Regulation Example

Step-up Converter H S can ning P art

U0 H yoke
Usyst
TDA9103

VREF SWITCHING
HDRIVE
4.8V REGULATOR
Usyst is
a pproximatively
proportiona l
Hamp to Hfreq
Adjust
9103-20.EPS

Flyba ck Pe a k
Detection a nd Re gulation

The following functions are implemented in the
TDA9103 :
- A DC controlled variable gain amplifier allowing a
variation of ±14% of the voltage reference.
This is used to set the horizontal image ampli-
tude.
- An erroramplifier, the non inverting input of which
is connected to the above mentioned adjustable
voltage reference.
The inverting input and the output of the error
amplifier are externally accessible.
- A comparator which determines the conduction
of the external transistor by comparing the output
voltage of the error amplifier and the voltage
applied on Pin 42 (ISENSE), which is the image of
the current in the power transistor (current mode
principle).
- A flip-flop which memorizes the on or off state of
the power transistor.
- An output buffer stage (open collector).

16/27
 TDA9103

PARABOLA GENERATION FOR EAST-WEST
CORRECTION (see Figure 21)
Starting from the vertical ramp a parabola is gen-
erated for E/W correction.
The core of the parabola generator is an analog
multiplier which generates a current in the form :
I = k (VRAMP - VMID)2
Where VRAMP is the vertical ramp, typically com-
prised between 2 and 5V, VMID is a DC voltage with
a nominal value of 3.5V, but adjustable in the range
3.2V → 3.8V in order to generate a dissymmetric
parabola if required (keystone adjustment).
The current is converted into voltage through a
variable gain transresistance amplifier. The gain,
controlled by the voltage on Pin 37 (E/W-AMP) can
be adjusted in the ratio 3/1.
The parabola is available on Pin 36 by the way of
an emitter follower which has to be biased by an
external resistor (10kΩ). It must be AC coupled with
external circuitry.
The typical parabola amplitude (AC), with the DC
Figure 21 : Parabola Generation Principle
control voltages V37 and V38 set to 4V, is 2V.
It is important to note that the parasitic parabola
during the discharge of the vertical oscillator ca-
pacitor is suppressed.
VERTICAL PART (see Figure 22)
The vertical part generates a fixed amplitude ramp
which can be affected by a S correction shape.
Then, the amplitude of this ramp is adjusted to drive
an external power stage.
The internal reference voltage used for the vertical
part is available between Pin 26 and Pin 24. It can
be used as voltage reference for any DC adjusment
to keep a high accuracy to each adjustment. Its
typical value is :
V26 = VREF = 8V.
The charge of the external capacitor on Pin 27
(VCAP) generates a fixed amplitude ramp between
the internal voltages, VL (VL = VREF/4) and VH
(VH = 5/8 ⋅ VREF).

+
Analog.
Multiplier
I

Vertical Ramp
or 36
38 37
E/W-CENT E/W-AMP

9103-14.AI
Figure 22 : Vertical Part Block Diagram
Charge Current
R 19R Transconductance
Amplifier
VREF
VREF
Disch. 27
Osc 25
V-SYNC 34 SYNCHRO OSCIL
Cap Sampling
Cap

29 S-CENTER
28 S-AMP
S Correction

30 VERT-OUT

31
Parabola 36 EW-OUT
Generator VERT-AMP
9103-17.AI

38 37
KEYST EW-AMP

17/27
TDA9103
Function
When the synchronisation pulse is not present, an
internal current source sets the free running fre-
quency. For an external capacitor, COSC = 180nF,
the typical free running frequency is 84Hz.
Typical free running frequency can be calculated
by :
1
f0 (Hz) = 1.5 ⋅ 10−5 ⋅
COSC (nF)
A negative or positive TTL level pulse applied on
Pin 34 (VSYNC) can synchronise the ramp in the
frequency range [fmin, fmax]. This frequency range
dependson the external capacitor connectedon Pin
27. A capacitor in the range [150nF, 220nF] is re-
commanded for application in the following
range : 50Hz to 120Hz.
Typical maximum and minimum frequency, at 25°C
and without any correction (S correction or C cor-
rection), can be calculated by :
fmax = 2.5 ⋅ f0
fmin = 0.33 ⋅ f0
If S or C corrections are applied, these values are
slighty affected.
If an external synchronisation pulse is applied, the
internal oscillator is automaticaly caught but the
amplitude is no more constant. An internal correc-
tion is activated to adjust it in less than half a
second: the highest voltage of the ramp on Pin 27
is sampled on the sampling capacitor connected on
Pin 25 (VAGCCAP) at each clock pulse and a
transconductance amplifier generates the charge
current of the capacitor. The ramp amplitude be-
comes again constant.
It is recommanded to use a AGC capacitor with low
leakage current. A value lower than 100nA is man-
datory.
DC Control Adjustments
Then, a S correction shape can be added to this
ramp. This frequency independent S correction is
generated internally; its amplitude is DC adjustable
on Pin 28 (VSAMP) and it can be centered to gener-
ate C correction, according to the voltage applied
on Pin 29 (VSCENT).
It is non effective for VSAMP lower than VREF /4 and
maximum for VSAMP = 3/4 ⋅ VREF.
18/27
Endly, the amplitude of this S corrected ramp can
be adjusted by the voltage applied on Pin 31
(VAMP). The adjusted ramp is available on Pin 30
(VOUT) to drive an external power stage. The gain
of this stage is typically ±30% when voltage applied
on Pin 31 is in the range VREF/4 to 3/4 ⋅ VREF. The
DC value of this ramp is kept constant in the
frequency range , for any correction applied on it.
Its typical value is :
VDCOUT = VMID = 7/16 ⋅ VREF.
A DC voltage is available on Pin 32 (VDCOUT). It is
driven by the voltage applied on Pin 33 (VPOS). For
a voltage control range between VREF/4 and 3/4 ⋅
VREF, the voltage available on Pin 32 is :
VDCOUT = 7/16 ⋅ VREF ± 300mV.
So, the VDCOUT voltage is correlated with DC value
of VOUT. It increases the accuracy when tempera-
ture varies.
Basic Equations
In first approximation, the amplitude of the ramp on
Pin 30 (VOUT) is :
VOUT - VMID = (VCAP - VMID) [1 + 0.16 ⋅ (VAMP - VREF/2)]
with VMID = 7/16 ⋅ VREF ; typically 3.5V
VMID is the middle value of the ramp on Pin 27
VCAP = V27 , ramp with fixed amplitude.
On Pin 32 (VDCOUT), the voltage (in volts) is calcu-
lated by :
VDCOUT =VMID + 0.16 ⋅ (VPOS - VREF/2).
VPOS is the voltage applied on Pin 33.
The center of the S correction can be approxima-
tively calculated according to the voltage applied
on Pin 29 (VSCENT) :
VCENTER = VMID + 0.25 ⋅ (VSCENT - VREF/2)
This is an internal voltage used to adjust the C
correction. The S correction can be adjusted along
the ramp according to this parameter. It is ineffec-
tive when VSAMP is lower than VREF/4.
The current available on Pin 27
(when VSAMP = VREF /4) is :
IOSC = 3/8 ⋅ VREF ⋅ COSC ⋅ f
COSC : capacitor connected on Pin 27
f synchronisation frequency
The recommanded capacitor value on Pin 25
(VAGC) is 470nF. Its assumes a good stability of the
internal closed loop.
 TDA9103

INTERNAL SCHEMATICS
Figure 23 Figure 24

VREF
VCC
Q1 D25 Q8
VCC
Q4 D22 HDUTY 2
D24
1 PLL2C Q9

Q5 D23

Q6 Q6 M7

9103-23.AI
9103-22.AI

Figure 25 Figure 26
VCC

VCC Q15
D26 Q16

HFLY 3 Q13
D27 VCC
D29

5 HREF
D28
9103-24.AI

9103-25.AI
Figure 27 Figure 28

VCC
VCC
D31 Q33
S4/S3/S2/S1 D34
Pins 6-7-8-9
D30
10 C0
D35
M20

Q32
9103-27.AI
9103-26.AI

19/27
TDA9103

INTERNAL SCHEMATICS (continued)

Figure 29 Figure 30

M5 M4 M6
VCC
Q46
D10

R0 11 Q69 PLL1F 12 Q8
D9
Q7

9103-28.AI

9103-29.AI
Figure 31 Figure 32
VCC
VCC
D20
D13
Q15 14 FH-MIN
13 HLOCK-CAP D19

M11 D14
Q17
9103-30.AI

9103-31.AI
Figure 33 Figure 34

VCC
Q22
VCC
D27
Q21 D24
Q26 16 XRAY-IN
Q23 15 H-POS
D28
D25
9103-32.AI

9103-33.AI

Figure 35 Figure 36
VCC
D7

VCC 21 H-OUTCOLL
D6
D2
Q3
Q1 17 HSYNC Q4
VCC
D0
D8

20 H-OUTEM
D9
9103-35.AI
9103-34.AI

20/27
 TDA9103

INTERNAL SCHEMATICS (continued)

Figure 37 Figure 38
VCC

VCC NPN
NMOS
NMOS
VAGCCAP 25 NPN

PMOS
PMOS NPN 26 VREF

9103-36.AI

9103-37.AI
Figure 39
VREF VCC

VREF
PNP PNP
VCC 12V
NPN

VCAP 27 PNP NPN

NPN NMOS

9103-38.AI
Figure 40 Figure 41
VREF VREF

PNP
VCC PNP

PNP
VS-AMP 28 PNP
VCC
NPN

NPN NPN VS-CENT 29 NPN NPN

9103-39.AI

9103-40.AI

21/27
TDA9103

INTERNAL SCHEMATICS (continued)

Figure 42 Figure 43
VCC VREF VCC

NPN
NPN 31 V-AMP
30 VOUT

PNP NPN

9103-41.AI

9103-42.AI
Figure 44 Figure 45
VCC VCC VREF

PNP
NPN

PNP 32 VDCOUT
V-POS 33 PNP

NPN PNP NPN NPN

9103-43.AI

9103-44.AI
Figure 46 Figure 47
VREF VCC
VCC VREF

PNP NPN

36 E/WOUT

NPN
VSYNC 34 PNP

NPN
9103-45.AI

9103-46.AI

22/27
 TDA9103

INTERNAL SCHEMATICS (continued)

Figure 48 Figure 49
VCC VREF VCC VREF

PNP PNP

PNP

E/W-AMP 37 NPN KEYST 38 PNP

NPN NPN NPN

9103-47.AI

9103-48.AI
Figure 50 Figure 51

Q23 VCC
VCC D21
D28
Q26
REGIN 40 Q20 Q19
Q24 39 B+-ADJ
D22
D27
9103-49.AI

9103-50.AI
Figure 52 Figure 53

VCC
Q16 VCC
D18
D13
41 COMP
I SENSE 42 Q10
Q14
D17
D12
Q15
9103-51.AI

9103-52.AI

23/27
 C23
220µF 63V VM J12

24/27
1
+
C22 T2
R63 1k Ω 100 µF J20
+12V G 5446-00 1
+
TDA9103

Q7 D3 BYT 13-800 J11

BC547 1
J1b J2b J3b Q6
1 2 3 4 1 2 3 4 1 2 3 4 5 6 7 C25 +
R64 R65 B+
R62 1k Ω 22 µF
IR430F 3.3k Ω 33k Ω 250V
0/5V to 2/6V INTERFACE HSIZE Q5
BC557
KEYST CCOR C24
+12V HDF BPLUS PINCSH SCOR 220pF
400V R66
HSHIFT FHMIN VSHIFT VSIZE R61
R60 1.5k Ω
1kΩ 33Ω
1W VP
HFLY HFLY

R10 3.9 kΩ
R13 3.9 kΩ
R16 3.9 kΩ
R19 3.9 kΩ
R22 3.9 kΩ
R25 3.9 kΩ
R28 3.9 kΩ

R1 3.9 kΩ
R4 3.9 kΩ
R7 3.9 kΩ
C47 R79
R72 1k Ω 10nF
APPLICATION DIAGRAM

C46 75k Ω
10nF
C33 R78 22k Ω J25
100pF
1

R3 10 kΩ
R6 1 0 kΩ
R9 1 0 kΩ
R20 120 kΩ
R23 120 kΩ

R1 2 10kΩ
R1 5 10kΩ
R1 8 10kΩ
R2 1 10kΩ
R2 4 10kΩ
R2 7 10kΩ
R3 0 10kΩ

R74 10kΩ
R73 10kΩ
R2 1 2 0kΩ
R5 1 2 0kΩ
R8 1 2 0kΩ
R11 12 0kΩ
R17 120 kΩ
R26 120 kΩ

R1 4 12 0kΩ
R29 120kΩ
B+ CONVERTER EHT FEEDBACK
HREF VREF

R75
+12V
3.3k Ω
C39 + IC1 VP
1µF R76 R52 R53 R55
C1 1kΩ
1 42 10k Ω 10k Ω 10k Ω J24
22nF R49 R58
R68 1M Ω Q8 1
47k Ω
2 41 TP9 BC547 2
1.5k Ω Q3 Q4 R57 1/2W R59
on off R67 22k Ω
+ 3
R71 C36 3 40 +
S1 1µF + C34 + C35 C45 12k Ω
10k Ω C29 470pF C21 BC547 BC547 2.2 Ω 1W E/W
J18 1µF 1µF 220pF 10 µF C44
4 39 220pF
HFLY 1 C29 C30 C37 1 µF
47 µF + + R48 R77 R50 R51 R54 R56 Q9
100nF 5 38 10k Ω 1kΩ 1kΩ 10k Ω 470 Ω 2.7k Ω TIP122
HREF C38 1µF
+
J17 6 37

1 E/W POWER STAGE

7 36
2
CS SWITCH
3 +12V
8 35
4 D4 C13 + C32

C48
1N4148 D1 470 µF 100nF J21
9 34 1N4004
C43 1µF -12V 1
C2 T

R80 2 .7 kΩ

1nF
+ TP11
10 D 33 R37 + C12
680pF 5% A 5.6k Ω 100 µF
R70 12kΩ 2
11 32 7 6 35V J23
9 C42 1µF 3
C3 1
R32 7.5k Ω 1 C10 1
10nF + 5
12 0 31 100nF 4 V YOKE 2
C7 R41 R39
C6 R36 12k Ω
4.7 µF 3 1.5 Ω 3
+ R31 1.8k Ω 220nF 13 30 220 Ω
C40 1 µF C11 C15 1/2W CON2
+ 470pF 220nF
14 29
C41 1 µF
R33 + -12V C14 C11
10k Ω 15 28 470 µF + 470pF
TP1 R40
XRAY IN C4 VERTICAL 1Ω
TP2 16 27 VREF DEFLECTION R36 5.6k Ω 1/2W
HSYNC TP3 150nF C27 STAGE
J2 17 26 +
C5 C28
+12V
47 µF +12V VP
18 25
J3 100nF
C8 + C9 470nF R47b
1 100 µF 100nF 19 24 +12V 33 Ω R47a
3W 47 Ω 3W T1 J22
R69
20 23 1
J19 TP5 TP4 3.9k Ω C20 +
TP8 HDRIVE 2
1 100 µF
21 22 3
R35 Q10 G 5576-01
BLK 1kΩ BC547 Q2
TP6 R44 10 Ω STD5N20
VSYNC R46
TP7 560 Ω
J5
Q1 R45
BC557 22k Ω C19
1nF HORIZONTAL
DRIVER
STAGE

9103-53.EPS

A demonstration board has been developped by
SGS-THOMSON and is available through your
usual SGS-THOMSON office.
This board has been designed in order to give first
the possibility to evaluate the TDA9103 in STAND
ALONE, and then to be easily connected to an
existing monitor.
In stand alone evaluation, for exemple, flyback
simulator is implemented in order to be able to
Figure 54
TDA9103
close the 2nd PLL loop, potentiometers are also
present to easily adjust all functions.
Then for testing in a real application, the upper part
of the board can be detached and the remaining
part can be connected to real application.
In addition to this, the application board has been
volontary designed separating clearly all the
blocks. This led to quite large PCB but give much
more space for measuring anything on the board.
9103-60.TIF
25/27
TDA9103

Figure 55

TDA9103

9103-61.EPS

26/27
 TDA9103

PACKAGE MECHANICAL DATA

42 PINS - PLASTIC PACKAGE
E
E1

A2
A1

A
L
B B1 e e1

e2

D
c
E

42 22

.015
0,38
Gage Plane

PMSDIP42.EPS
e3
1 21
e2
SDIP42

Millimeters Inches
Dimensions
Min. Typ. Max. Min. Typ. Max.
A 5.08 0.200
A1 0.51 0.020
A2 3.05 3.81 4.57 0.120 0.150 0.180
B 0.36 0.46 0.56 0.0142 0.0181 0.0220
B1 0.76 1.02 1.14 0.030 0.040 0.045
c 0.23 0.25 0.38 0.0090 0.0098 0.0150
D 37.85 38.10 38.35 1.490 1.5 1.510
E 15.24 16.00 0.60 0.629
E1 12.70 13.72 14.48 0.50 0.540 0.570
e 1.778 0.070
e1 15.24 0.60
e2 18.54 0.730
SDIP42.TBL

e3 1.52 0.060
L 2.54 3.30 3.56 0.10 0.130 0.140

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility
for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result
from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.
Specifications mentioned in this publication are subject to change without noti ce. This publication supersedes and replaces all
information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life
support devices or systems without express written approval of SGS-THOMSON Microelectronics.

 1996 SGS-THOMSON Microelectronics - All Rights Reserved

Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips
I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to
the I2C Standard Specifications as defined by Philips.

SGS-THOMSON Microelectronics GROUP OF COMPANIES

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