Open ROADM-Draft Document: Open ROADM MSA 3.01 W-Port Digital Specification (200G-400G)

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2 MSA_3.01 W-Port Digital Specification

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10 Open ROADM MSA 3.01 W-Port Digital Specification
11 (200G-400G)
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13 Open ROADM-Draft document
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18 June 25, 2019
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25 www.Open ROADM.org
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31______________________________________________________________________________________
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32THIS SPECIFICATION IS PROVIDED "AS IS" WITH NO WARRANTIES WHATSOEVER,
33INCLUDING ANY WARRANTY OF MERCHANTABILITY, NONINFRINGEMENT, FITNESS
34FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF
35ANY PROPOSAL, SPECIFICATION OR SAMPLE. THE AUTHORS DISCLAIM ALL
36LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY PROPRIETARY
37RIGHTS, RELATING TO USE OF INFORMATION IN THIS SPECIFICATION. EACH
38MEMBER OF THE OPEN ROADM MSA AGREE TO GRANT NON-EXCLUSIVE, FAIR,
39REASONABLE AND NON-DISCRIMINITORY (FRAND) PATENT LICENSES TO MEMBES OF
40THE MSA TO ANY CLAIM IT OWNS OR HAS THE ABILTY TO LICENSE THAT ARE
41STANDAS ESSENTIAL (I.E., MANDATORY, NECESSARY, OR REQUIRED) TO MAKE AND
42USE A PRODUCT COMPLIANT WITH THESE SPECIFICATIONS UNDER THE FOLLOWING
43REQUIRED CONDITIONS:
44A) THE PATENT LICENSE ONLY COVERS PREEXISTING PATENT CLAIMS THAT ARE
45 STANDARDS ESSENTIAL (I.E., MANDATORY, NECESSARY OR REQUIRED) TO MAKE
46 AND USE A PRODUCT COMPLIANT WITH THESE SPECIFICATIONS. THE PATENT
47 LICENSE DOES NOT INCLUDE CLAIMS DIRECTED TO NON-STANDARDS ESSENTIAL
48 DESIGN OR IMPLEMENTATION CHOICES; AND
49B) ANY PERSON OR ENTITY THAT INTENDS TO CLAIM THE BENEFIT OF THIS PATENT
50 LICENSE MUST: (1) IDENTIFY IN WRITING WHICH SPECIFICATION(S) APPLY TO ITS
51 PRODUCT(S) BEFORE SAID PRODUCTS ARE SOLD; AND (2) MAKE A RECIPROCAL
52 COMMITMENT IN WRITING TO LICENSE ITS OWN PATENT CLAIMS THAT ARE
53 STANDARDS ESSENTIAL (I.E., MANDATORY, NECESSARY OR REQUIRED) TO MAKE
54 AND USE A PRODUCT COMPLIANT WITH THESE SPECIFICATIONS UNDER FRAND
55 LICENSING TERMS BACK TO MEMBERS OF THE OPEN ROADM MSA.
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59TITLE: Open ROADM MSA 3.01 W-Port Digital Specification (200G-400G)
60
61
62SOURCE:
64Mike A. Sluyski
65Acacia Communications Inc.
663 Mill and Main
67Maynard, MA 01754, USA
68Phone: +1-978-938-4896 x773
69Email: msluyski@acacia-inc.com
70
71
72ABSTRACT: This document describes the Open ROADM W-Port Digital Specification
73for 200G, 300G, and 400G transport over coherent DP-mQAM optical links. The
74specification includes the processing functions of adapting a fully standardized FlexO-x
75[7] frame structure with a new open Forward Error Correction (oFEC) encoder and
76symbol frame format (FOICx-oFEC-DPmQAM).
77
78The oFEC engine is a block-based encoder and iterative Soft-Decision (SD) decoder.
79With 3 SD iterations the Net Coding Gain is 11.1 dB @ 10 -15 (DP-QPSK) and 11.6 dB @
8010-15 (DP-16QAM), with pre-FEC BER threshold of 2.0×10 -2. The combined latency of
81the encoder and decoder is less than 3 µs.
82
83An Open ROADM transponder/muxponder node may support up to 4 × 100G Client
84interfaces. The mapping and aggregation of these Client interfaces to a FlexO-x (x=2,3,4)
85frame structure is fully specified by ITU-T G.709/Y.1331 and G.709.1/Y.1331.1. The
86adaptation functions from the FlexO-x frame structure into the oFEC block and the line-
87side DSP symbol framing is described in this document.
88
3
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891 List of Figures.........................................................................................6

902 List of Tables...........................................................................................7
913 Document Revision History....................................................................8
924 Scope and Introduction...........................................................................9
935 Definitions.............................................................................................12
94 5.1 Terms defined in this document.........................................................................12
95 5.2 Abbreviations and Acronyms............................................................................12
96 5.3 Conventions.......................................................................................................13
976 References.............................................................................................14
987 FlexO-x frame structure.......................................................................15
99 7.1 FlexO-1 frame structure.....................................................................................15
100 7.2 FlexO-2 Frame Structure...................................................................................17
1038 FlexO-x-oFEC adaptation....................................................................21
104 8.1 Padding Insertion/Removal................................................................................22
105 8.2 FlexO-4 adaptation to oFEC input blocks.........................................................22
108 8.5 Frame Synchronous Scrambling........................................................................25
1099 Open Forward Error Correction (oFEC).............................................27
110 9.1 oFEC encoding codec........................................................................................27
111 9.1.1 Encoding.................................................................................................................................31
112 9.1.2 Encoder interface....................................................................................................................31
113 9.1.3 Formal encoder definition......................................................................................................33
114 9.2 Decoding............................................................................................................34
115 9.3 oFEC Interleaver................................................................................................35
116 9.3.1 oFEC Interleaver architecture.................................................................................................35
117 9.3.2 Intra-block interleaving..........................................................................................................35
118 9.3.3 Inter-block interleaving..........................................................................................................36
11910 Symbol Mapping and Polarization Distribution...............................40

120 10.1 Symbol mapping................................................................................................40
121 10.1.1 DP-16QAM Symbols.........................................................................................................40
122 10.1.2 DP-8QAM Symbols...........................................................................................................41
123 10.1.3 DP-QPSK Symbols............................................................................................................42
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12411 DSP Framing.....................................................................................43
125 11.1 DSP super-frame................................................................................................43
126 11.2 DSP sub-frame...................................................................................................44
127 11.3 FAW Sequence..................................................................................................46
128 11.4 Training Sequence.............................................................................................47
129 11.5 Pilot Sequence....................................................................................................48
13012 Frame Expansion Rate......................................................................53
13113 Appendix A – TRPN/MUXP/SWITCH client interface examples...54
132 13.1 Transponder (TRPN).........................................................................................55
133 13.2 Muxponder (MUXP)..........................................................................................55
134 13.3 Client interface bit rates.....................................................................................55
135
136
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1371 List of Figures

138FIGURE 1: OPEN ROADM ARCHITECTURE REFERENCE..............................................................................................9
139FIGURE 2: FLEXO-X-OFEC-M FUNCTIONAL MODEL..................................................................................................10
140FIGURE 3: DIGITAL PORT FUNCTIONS FOR A SINGLE FLEXO-X-OFEC SIGNAL.................................................................11
141FIGURE 4: FLEXO FRAME STRUCTURE...................................................................................................................15
142FIGURE 5: FLEXO MULTI-FRAME FORMAT..............................................................................................................16
143FIGURE 6: FLEXO-2 FRAME STRUCTURE................................................................................................................17
144FIGURE 7: INTERLEAVED FLEXO FRAME TO FLEXO-2 FRAME STRUCTURE.....................................................................18
145FIGURE 8: FLEXO-3 FRAME STRUCTURE................................................................................................................18
146FIGURE 9: INTERLEAVED FLEXO FRAME TO FLEXO-3 FRAME STRUCTURE.....................................................................19
147FIGURE 10: FLEXO-4 FRAME STRUCTURE..............................................................................................................19
148FIGURE 11: INTERLEAVED FLEXO FRAME TO FLEXO-4 FRAME STRUCTURE...................................................................20
149FIGURE 12: N X FLEXO TO FLEXO-X-OFEC ADAPTION PROCESS.................................................................................21
150FIGURE 13: DIGITAL PROCESSES OF FLEXO-X TO FLEXO-X-OFEC ADAPTATION.............................................................22
151FIGURE 14: FLEXO-4 TO OFEC INPUT BLOCK ADAPTATION.......................................................................................23
154FIGURE 17: FRAME SYNCHRONOUS SCRAMBLER.....................................................................................................26
155FIGURE 18: OFEC BLOCK ENCODER AND OFEC INTERLEAVER....................................................................................27
156FIGURE 19: STRUCTURE OF AN OPENFEC..............................................................................................................29
157FIGURE 20: SEQUENCING OF BITS WITHIN AN INPUT BLOCK......................................................................................32
158FIGURE 21: BIT NUMBERING WITHIN AN OUTPUT BLOCK..........................................................................................33
159FIGURE 22: INTER-BLOCK INTERLEAVING...............................................................................................................38
160FIGURE 23: DSP SYMBOL MAPPING AND POLARIZATION DISTRIBUTION.......................................................................40
161FIGURE 24: DSP FRAME GENERATION..................................................................................................................43
162FIGURE 25: DSP SUPER-FRAME..........................................................................................................................44
163FIGURE 26: DSP SUB-FRAMES 2 TO 48 OF THE DSP SUPER-FRAME...........................................................................45
164FIGURE 27: PILOT SYMBOL (DP-16QAM MODULATION SHOWN).............................................................................48
165FIGURE 28: PILOT SEED AND SEQUENCING............................................................................................................48
166
167
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1682 List of Tables

169TABLE 1: REVISION HISTORY.................................................................................................................................8
170TABLE 2: OFEC ADAPTATION RATES.....................................................................................................................22
171TABLE 3: SOURCE POSITIONS (ROW, COL) FOR INTRA-BLOCK INTERLEAVING.................................................................36
172TABLE 4: INTERLEAVER SUBSETS..........................................................................................................................37
173TABLE 5: DP-16QAM SYMBOL AMPLITUDE MAP...................................................................................................41
174TABLE 6: 8QAM SYMBOL AMPLITUDE MAP...........................................................................................................42
175TABLE 7: DP-QPSK SYMBOL AMPLITUDE MAP.......................................................................................................42
176TABLE 8: FAW/TS/PS PATTERN.........................................................................................................................43
177TABLE 9: FAW SEQUENCE.................................................................................................................................46
178TABLE 10: TRAINING SYMBOL SEQUENCE..............................................................................................................47
179TABLE 11: PILOT SEQUENCE...............................................................................................................................48
180TABLE 12: PILOT SEQUENCE...............................................................................................................................52
181TABLE 13: FLEXO/OFEC EXPANSION RATES...........................................................................................................53
182TABLE 14: OPEN ROADM 3.0 TRANSPONDER (TRPN) FUNCTIONS..........................................................................55
183TABLE 15: OPEN ROADM 3.0 MUXPONDER (MUXP) FUNCTIONS...........................................................................55
184TABLE 16 CLIENT INTERFACE TYPES AND PAYLOAD BIT RATES....................................................................................56
185TABLE 17: LINE TYPES AND FRAME BIT RATES.........................................................................................................56
186
187
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1883 Document Revision History

189Table 1 provides this document revision history.
190
Document
Date Revision Comments
Revision
Initial Draft – documents client mapping and multiplexing into
3.0 9/17/18 FlexO container, DSP frame format, and openFEC
encoding/decoding functions.
06/06/19 Maintenance update. Incorporated reviewer’s comments
including proposals for distinguishing the essential port
3.01 function (which has a node-internal digital service interface and
a node-external optical transmission interface) and an Open
ROADM node specification.
191 Table 1: Revision History
192
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1934 Scope and Introduction

194Open ROADM 3.0 defines specifications [1] for 100-400G single-wavelength optical
195ports (W-Ports) for muxponder/transponder/switch (MUXP, TRPN, SWITCH) node
196functions and for optical ports (MW, WR ports) of optical switching (ROADM)
197equipment (reference Figure 1).
198
SDN SDN
NETCONF NETCONF
DCN DCN
Eth Eth
OAMP
OSC
Eth Pluggable
Pluggable
client
line optics
optics
Ethernet
Switch
OSC
OpenROADM
Eth Shelf Processor
MW Ports YANG
WR Ports W Ports
OSC
Eth
Pluggable
Pluggable
client
line optics
optics
Single Wavelength
Cross Connect
OSC
Eth
199
200 Figure 1: Open ROADM Architecture reference
201
202This specification defines the port function1 of a 200-400G W-Port, i.e. the protocols,
203data structures, and algorithms for end-to-end interworking between two (200-400G) W-
204Ports [1] that are connected via an Open ROADM optical layer network. The intra-
205system service interface(s) of this port function are fully specified in existing standards
206(e.g. the mapping and aggregation of client interface signals via OTUCn (n=2, 3, or 4) to
207a FlexO-x (x=n) frame structure by ITU-T G.709/Y.331 and G.709.1/Y.1331.1).
208
209Note: this specification makes no assumption about the allocation of functions on line
210cards or optical modules (albeit, a typical module will provide a muxceiver function for
211OTN and Ethernet signals beyond 100G)
212
213Appendix A includes examples of the digital layer signal formats which might be present
214in a TRPN/MUXP/SWITCH node that is connected, mapped or aggregated for optical
215transport across the W-Ports. The physical interfaces and any terminated client port
191 In OTN terminology this document would somewhat ambiguously be called an interface specification.
20Here we prefer to call it a port function specification, i.e. a layered description of the processing between an
21abstract system-internal service interface and a concrete network side system interface (located at a system
22boundary).
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216protocols identified in Appendix A are for informational purposes only. They are not
217considered relevant to the W-Port function.
218
219The digital interface type of a (200-400G W-Port is called FlexO-x-oFEC (x=2, 3, or 4
220for 200G, 300G, and 400G respectively), and any signal that can be adapted (or mapped)
221to a FlexO-x information structure can be transported via the FlexO-x-oFEC port.
222
223Open ROADM node (TRPN/MUXP/SWITCH) can further bond a number m of W-Ports
224into a FlexO-x-oFEC-m interface group to transport signals larger than 400G.
225
226The information processing for a FlexO-x-oFEC-m interface group (as defined in this
227specification) is represented by the lower part of the functional model shown in Figure 2.
228One OTUCn signal (consisting of n OTUC instances) is mapped into the payloads of n
229FlexO frame structures, each FlexO frame structure payload area containing the bits of
230one OTUC signal. Up to this point, all functions are well defined in existing standards.
231
232The scope of this specification is how the node internal set of n FlexO signals are mapped
233into m (m = [n/x]) FlexO-x-oFEC signals, each FlexO-x-oFEC signal containing "x"
234(frame/multi-frame aligned interleaved) FlexO signals (x ≥ 1). Each FlexO-x-oFEC
235structure is then modulated onto one FOICx-oFEC-DP-nQAM, which is transported via
236one media element (OTSi).
237
ODUk ODUk
ODUCn/ODUk
(GMP)
ODUCn
OTUCn/ODUCn
OTUCn
FlexO/OTUCn
FlexO-x-oFEC FlexO-x-oFEC
OTSi/FlexO OTSi/FlexO
OTSI OTSI
OTSiG
238
239 Figure 2: FlexO-x-oFEC-m functional model
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240The digital formatting and processing done by the FlexO-x-oFEC port function for the
241Open ROADM MSA 3.0 200-400G coherent interface is shown in Figure 3.
242
Functionality defined in this document
FlexO FlexO-x oFEC-x Coder Payload FlexO-x-oFEC
oFEC Coder DP-16QAM: 1376256b

DP-8QAM: 1032192b
Insert 576 Symbols 32/31
(BMP)
FlexO
DP-QPSK: 688128b H
FAW, Counter,
Pilot insert with
Padding
172032 Reserved 172608
spacing 31
178176 X pol
interleave
400G - 116 rows (4640 x 257b) 1192480b 1193472b 3552 ENC0 4096 Symbols
400G – 992b Scrambler oFEC Interleaver Symbol
10b
300G - 87 rows (3480 x 257b) 894360b Scrambler 7104b 344064 Polarization

300G – 744b 895104b Size = 172032b Map Distribution
FOICx-oFEC-DPmQAM
200G - 58 rows (2320 x 257b) 596240b 3552 ENC1 4096
200G – 496b 596736b V FAW, Counter,
Pilot insert with
172032 Reserved 172608 178176 Y pol
(BMP)
FlexO
168x DP-16QAM DP-16QAM (8x) spacing 31

Symbols
126x: DP-8QAM DP-8QAM (6x)
84x: DP-QPSK DP-QPSK (4x)
243 Per ITU-T G.709.1/Y.1331
244 Figure 3: Digital port functions for a single FlexO-x-OFEC signal
245
246The mapping processes defined in Section 10 of this document are analogous to Clauses
24712 and 13 of ITU-G.709.3/Y.1331.3, which describe the adaptation of n×FlexO (n=2,4)
248frame/multi-frame aligned signals adapted to the FlexO-x-SC (x=2,4) frame structure. It
249should also be noted that the DSP frame format described in G.709.3/Y.1331.3 Section
25014 (i.e. FlexO-x-DSH) is structurally consistent with the FlexO-x-oFEC frame at the
251oFEC block output.
252
253Editor’s Note: A future amendment to ITU-T G.709.3 could consider the addition of both
254oFEC and the FlexO group adaptation to oFEC described in this document for longer
255reach applications (e.g. metro use cases up to 450km).
256
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2575 Definitions
258This document uses the following terms and definitions.
2595.1 Terms defined in this document
260  openFEC (oFEC) - a block-based encoder and iterative Soft Decision
261 (SD) decoder. With 3 SD iterations the Net Coding Gain is 11.1 dB @
262 10-15 (DP-QPSK) and 11.6 dB @ 10-15 (DP-16QAM), with pre-FEC BER
263 threshold of 2.0×10-2.
264  FlexO-x-oFEC2 - an information structure consisting of a G.709.1
265 FlexO-x (x=2,3,4) frame structure protected with oFEC.
266  FlexO-x-oFEC signal3 instance - Refers to an individual Flexo-x-oFEC
267 instance that is part of a FlexO-x-oFEC-m interface group
268  FlexO-x-oFEC-m signal group - Refers to the group of m FlexO-x-
269 oFEC signals.
270  FOICx-oFEC-DP-nQPSK4 - Refers to a single FlexO-x-oFEC signal
271 within a FlexO-x-oFEC-m signal group operating over a dual
272 polarization coherent interface with DP-QPSK modulation.
273  FOICx-oFEC-DP-nQAM5 - Refers to a single FlexO-x-oFEC signal
274 within a FlexO-x-oFEC-m signal group operating over a dual
275 polarization coherent interface with DP-nQAM modulation (n=8,16).
2765.2 Abbreviations and Acronyms
277 This document uses the following abbreviations and acronyms.
278 AM Alignment Marker
279 BMP Bit-synchronous mapping Procedure
280 CRC Cyclic Redundancy Check
281 DSP Digital Signal Processor
282 DP Dual Polarization
283 DP-nQAM Coherent interface using DP-nQAM
284 DWDM Dense Wave Division Multiplexing
285 FEC Forward Error Correction
286 FlexO Flexible Optical Transport Network
287 FOIC FlexO Interface
288 GE Gigabit Ethernet
289 LSB Least Significant Bit
302 The oFEC FlexO notation defined here is intentionally chosen to mimic existing G.709.1 and G.709.3
31naming conventions but is not ITU-T standard FlexO terminology.
323 In addition to a port function and processing view associated with a FlexO-x-oFEC interface, there is the
33dual view of a FlexO-x-oFEC signal or data format. Hence, generally, “FlexO-x-oFEC is a prefix for
34objects like “interface,” or “port”, or “signal” or “data”. The same statements apply to other FlexO related
35terms.
364 The general type would be FOICx.k for k lane multilane format, but here k=1 and therefore omitted.
375 The general type would be FOICx.k for k lane multilane format, but here k=1 and therefore omitted.
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290 MSA Multi-Source Agreement
291 MSB Most Significant Bit
292 ODTUG Optical Data Tributary Unit Group
293 ODTUGk/Cn Optical Data Tributary Unit Group-k/Cn
294 ODTUjk Optical Data Tributary Unit j into k
295 ODTUk/Cn.ts Optical Data Tributary Unit k/Cn with ts tributary slots
296 ODU Optical Data Unit
297 ODUk/Cn Optical Data Unit-k/Cn
298 ODUk/Cn.ts Optical Data Unit k/Cn fitting in ts tributary slots
299 ODUk/CnP Optical Data Unit-k/Cn Path monitoring level
300 ODUk/CnT Optical Data Unit-k/Cn Tandem connection monitoring level
301 OH Overhead
302 OTLk.n Group of n Optical Transport Lanes that carry one OTUk
303 OTLC.n Group of n Optical Transport Lanes that carry one OTUC of an
304 OTN Optical Transport Network
305 OTU Optical Transport Unit
306 OTUk/Cn Optical Transport Unit-k/Cn
307 PIC Photonic Integrated Circuit
308 QAM Quadrature Amplitude Multiplexing
309 QPSK Quadrature Phase Shift Keying
310 RES Reserved for future international standardization
311 ROADM Reconfigurable Add Drop Multiplexor
312 RS Reed-Solomon
313 WDM Wave Division Multiplexing
3145.3 Conventions
315 This document uses the following conventions:
316  Transmission order - The order of transmission of information in all the
317 diagrams is first from left to right and then from top to bottom unless
318 explicitly called out as different. The most significant bit (bit 1) is illustrated
319 at the left in all the diagrams (e.g. Row 1, Column 1).
320  Reserved bit(s) - The value of a reserved bit or reserved bit for future
321 standardization shall be set to “0”.
322  Non-Sourced bit(s) - The value of any non-sourced bit shall read back as “0”.
323
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3246 References
325 [1] Open ROADM MSA specification ver 3.00
326 [2] Open ROADM MSA specification version 2.00
327 [3] Open ROADM Yang Data models - https://github.com/OpenROADM/Open
328 ROADM_MSA_Public
329 [4] IEEE Std. 802.3TM-2018, IEEE Standard for Information Technology –
330 Telecommunications and Information Exchange Between Systems – Local and
331 Metropolitan Area Networks – Specific Requirements Part 3: Carrier Sense
332 Multiple Access With Collision Detection (CSMA/CD) Access Method and
333 Physical Layer Specifications.
334 [5] IEEE P802.3cn Task Force – Future work proposals
335 [6] ITU-T G.709/Y.1331 (06/2018), Interfaces for the optical transport network
336 [7] ITU-T G.709.1/Y1331.1 (06/2018), Flexible OTN short-reach interfaces
337 [8] ITU-T G.709.2/Y.1331.2 (07/2018), OTU4 long-reach interface
338 [9] ITU-T G.709.3/Y.1331.3 (11/2018), Flexible OTN long-reach interfaces
339 [10] ITU-T G.798 (08/2018), Characteristics of transport equipment Description
340 methodology and generic functionality.
341 [11] ITU-T G.870/Y.1352 (2016) Terms and definitions for optical networks
342 [12] Telcordia NEBSTM Requirements: Physical Protection, Telcordia Technologies
343 Generic Requirements, GR-63-CORE Issue 3, March 2006.
344 [13] G694.1: Spectral grids for WDM applications: DWDM Frequency grid.
345 [14] G.698.2: Amplified multichannel DWDM applications with single channel
346 optical interfaces.
347
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3487 FlexO-x frame structure

349The Open ROADM 3.0 FlexO-x frame structure is defined prior to oFEC coder
350adaptation and oFEC processing. Aspects of the FlexO-x frame structure that are specific
351to FlexO-x-oFEC are identified, otherwise the FlexO-x overhead is common to the
352requirements defined in ITU-T G.709.1.
3537.1 FlexO-1 frame structure
354The FlexO (100G) frame structure is defined in G.709.1 and copied in Figure 4 for
355reference. FlexO is a block format of 5140 bit columns × 128 rows.
356
5140
1
rows Columns
1 AM PAD OH Payload (3860 bits)
2 Payload (5140 bits)
3
. Frame
.
. Payload area
128 Payload (5140 bits)

357
358 Figure 4: FlexO frame structure
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
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381ITU-T G.709.1 further defines an 8-frame multi-frame structure shown in Figure 5.
382
5140
Columns
1
rows
1 AM PAD OH
.. .
Frame 1
65 FS
128
1 AM PAD OH
.. .
Frame 2
65 FS
128
1 AM PAD OH
.. .
Frame 8
65
128
383
384 Figure 5: FlexO multi-frame format
385
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386The multi-frame contains seven Fixed Stuff locations (FS) in the payload area of the
387FlexO multi-frames, each containing 1,280 bits. These FS locations are located in row 65,
388columns 1 to 1,280 of the first seven frames within the multi-frame. The last frame within
389the multi-frame does not contain FS.
390 The FS bits are filled with all zeros and not checked at the receiver sink function.
391
392The FlexO multi-frame payload, excluding the FS locations, consists of 5,244,160 bits
393(655,520 bytes) out of the total 5,263,360 bits (657,920 bytes) per FlexO multi-frame.
394
395Alignment Markers (AM), Padding (PAD) and OverHead (OH) are inserted in the first
396row of each FlexO frame. The FlexO payload and overhead area is fully protected with
397oFEC, which is defined in Section 9.
398
3997.2 FlexO-2 Frame Structure
400The FlexO-2 frame structure is a block format of 10280 bit columns × 128 rows with
401960b columns of AM, 960b columns of PAD, and 640b of OH. Parity is added by the
402oFEC block and interleaver stages downstream of the FlexO-2 frame structure.
403
404The FlexO-2 frame structure is shown in Figure 6.
10280
2560
2561
Columns
1
rows 960b 960b 640

1 AM
AM PAD OH
2
3
. Frame 1
. Payload area
.
128
405
406 Figure 6: FlexO-2 frame structure
407Two frame/multi-frame aligned 100G FlexO instances are 10-bit interleaved into the
408FlexO-2 frame structure in a similar fashion as defined by FlexO-2-SC (ITU-T G.709.3
409clause 12).
410
411
412
413
414The interleaving process is shown in Figure 7.
17
48
columns columns
1280
1280
5140
5140
480
960
480
960
1
1
rows rows
1 AM PAD OH
1 AM PAD OH
2 2
. .
. Payload area . Payload area
128 128
FlexO #A FlexO #B
10280
2560
2561
Columns
1
rows
1 AM
AM PAD OH
2
3
. Frame 1
. Payload area
.
128
415
416 Figure 7: interleaved FlexO frame to FlexO-2 frame structure
417The FEC OH defined for FlexO-2-SC is not required for FlexO-2 and will be defined as
418reserved (RES). The FlexO-3 AM, PAD, and OH fields are the interleaved FlexO
419instances AM, PAD, and OH.
421The FlexO-3 frame structure is 10280b x 192 rows with 1440b columns of AM, 1440b
422columns of PAD, and 960b of OH. Parity is added by the oFEC block and interleaver
423stages downstream of the FlexO-3 frame structure.

10280
3840
3841
Columns
1
rows 1440 1440 960b

1 AM
AM PAD OH
2
3
. Frame 1
. Payload area
.
192
425
427Three frame/multi-frame aligned 100G FlexO instances are 10-bit interleaved into the
428FlexO-3 frame structure in similar fashion as defined by the FlexO-2-SC (ITU-T G.709.3
429clause 12).
18
50
430This interleaving process is shown in Figure 9.
columns columns columns
1280
1280
1280
5140
5140
5140
480
960
480
960
480
960
1
1
rows rows rows
1 AM PAD OH
1 AM PAD OH
1 AM PAD OH
2 2 2
. . .
. Payload area . Payload area . Payload area
128 128 128

FlexO #A FlexO #B FlexO #C
10280
3840
3841
Columns
1
rows
1 AM
AM PAD OH
2
3
. Frame 1
. Payload area
.
431 192
432 Figure 9: Interleaved FlexO frame to FlexO-3 frame structure
433The FlexO-3 AM, PAD, and OH fields are the interleaved FlexO instances AM, PAD,
434and OH.
436The FlexO-4 frame structure is 10280b x 256 rows with 1920b columns of AM, 1920b
437columns of PAD, and 1280b of OH. Parity is added by the oFEC block and interleaver
438stages downstream of the FlexO-4 frame structure.

10280
5120
5121
Columns
1
rows 1920b 1920b 1280b

1 AM
AM PAD OH
2
3
. Frame 1
. Payload area
.
256
440
442Four frame/multi-frame aligned 100G FlexO instances are 10-bit interleaved into the
443FlexO-4 frame structure in similar fashion as defined by the FlexO-4-SC (ITU-T G.709.3
444clause 13).
19
52
445This process is shown in Figure 11.
columns columns columns columns
1280
1280
1280
1280
5140
5140
5140
5140
480
960
480
960
480
960
480
960
1
1
rows rows rows rows
1 AM PAD OH
1 AM PAD OH
1 AM PAD OH
1 AM PAD OH
2 2 2 2
. . . .
. Payload area . Payload area . Payload area . Payload area
128 128 128 128

FlexO #A FlexO #B FlexO #C FlexO #C
10280
5121
5120
Columns
1
rows
1 AM
AM PAD OH
2
3
. Frame 1
. Payload area
.
446 256
447 Figure 11: Interleaved FlexO frame to FlexO-4 frame structure
448The FEC OH defined for FlexO-4-SC is not required for FlexO-4 and will be defined as
449reserved (RES). The FlexO-4 AM, PAD, and OH fields are the interleaved FlexO
450instances AM, PAD, and OH.
451
20
54
4528 FlexO-x-oFEC adaptation

453A logical flow diagram of the FlexO-x to FlexO-x-oFEC adaptation process is shown in
454Figure 12.
455
FlexO FlexO
10b
10b
FlexO-x
PAD
Scrambler
OFEC
FlexO-x-oFEC
FlexO-x-oFEC-
DP-nQAM
456
457 Figure 12: n x FlexO to FlexO-x-oFEC adaption process
458
459
460
461
462
463
464
465
466
467
468
469
470
471
21
56
472The FlexO-x frame structure is adapted to the oFEC Coder block by adding padding after
473every n × 10280 bit rows. The data stream is then scrambled and passed to the oFEC
474encoder. Table 2 shows the relationships between the oFEC-x Coder Payload and the
475FlexO-x frame structure. The FlexO-x-oFEC is aligned and synchronized to the DSP
476frame, therefore the number of PAD bits, oFEC block and payload bits per DSP frame is
477modulation dependent.
478
oFEC-x
FlexO-x-
PAD coder oFEC Modulation
FlexO-x Rows oFEC
(bits) payload Blocks Format
(bits)
(bits)
FlexO-4-oFEC 116 rows, (4640×257 bits) 992 1,193,472 168 1,376,256 DP-16QAM
FlexO-3-oFEC 87 rows, (3480×257 bits) 744 895,104 126 1,032,192 DP-8QAM
DP-QPSK
FlexO-2-oFEC 58 rows, (2320×257 bits) 496 596,736 84 688,128
479 Table 2: oFEC adaptation rates
480
481The digital formatting and processing done by the DSP to adapt the FlexO-x to the oFEC
482Coder is shown in Figure 13.
483
FlexO-x oFEC-x Coder Payload FlexO-x-oFEC

DP-8QAM: 1032192b
DP-QPSK: 688128b
1192480b Padding
400G - 116 rows (4640 x 257b) 1193472b 3552 ENC0 4096
400G – 992b Scrambler oFEC Interleaver
300G - 87 rows (3480 x 257b) 894360b 895104b Scrambler 7104b
300G – 744b Size = 172032b
200G - 58 rows (2320 x 257b) 596240b 3552 ENC1 4096
200G – 496b 596736b
168x DP-16QAM DP-16QAM (8x)

484 84x: DP-QPSK DP-QPSK (4x)
485 Figure 13: Digital processes of FlexO-x to FlexO-x-oFEC adaptation.
4868.1 Padding Insertion/Removal

487The oFEC block processing is aligned and synchronized to the DSP super-frame (See
488Section 11.1). Pad bits are appended to the Flex-O data to enable this alignment. The
489PAD is removed after the decoder on the receive interface. The PAD is an all-zero field
490that gets scrambled prior to encoding and removed after decoding and descrambling.
4918.2 FlexO-4 adaptation to oFEC input blocks
492For FlexO-4 116 rows (4,640×257 bit blocks) of information (1,192,480 bits) plus 992
493bits of pad (1,193,472 bits total) are scrambled to form the oFEC-4 coder payload
494structure. At the input of the oFEC coder the oFEC-4 payload structure is bitwise
495demultiplexed to two oFEC encoders, each of which operate on input blocks of 3,552 bits
496and produce output blocks of 4096 bits. To process the 1,193,472 bits each encoder
497operates on 168 input blocks of 7104 bits.
498
22
58
499Figure 14 shows the adaptation of the FlexO-4 frame structure to the oFEC input block
500structure and then to the encoder input block sequence.
501
Scrambler Reset
to 0xFFFF
10280
1920
3840
3841
5140
5141
1921
5120
5121
1
rows Columns
168 oFEC Coder Input
1 AM PAD OH Payload (5140 bits) 113
114
Blocks
2 1920b 1280b 20b Pad
3 Payload (10280 bits) 115

4 PAD (992b) 116
5 oFEC input block 1
Payload area 2
Scrambled Payload,
4640x257b 3
Payload
and information
PAD
256 rows (FlexO-4)
(1,192,480 bits) . 3480x257-bit

7104 bits blocks
.
.
116
.
.
. B1
119
120 PAD (992b) 116 B168
121 1
Payload (10280 bits) 2
116
...
PAD (992b) 116
256
1
1920b 1280b 20b Pad
116
Payload (10280 bits)
. PAD (992b)
.
. Payload area
502
503 Figure 14: FlexO-4 to oFEC input block adaptation

505For FlexO-3 87 rows (3,480 × 257 bit blocks) of information (894,360 bits) plus 744 bits
506of pad (895,104 bits total) are scrambled and then bitwise demultiplexed to two oFEC
507encoders, each of which operate on input blocks of 3552 bits and produce output blocks
508of 4,096 bits. To process the 895,104 bits each encoder operates on 126 input blocks of
5097104 bits.
510
511
512
513
514
515
516
517
518
519
23
60
522
Scrambler Reset
to 0xFFFF
10280
5141
5140
1920
3840
5120
1921
3841
5121
1
rows Columns
126 oFEC Coder
85
Input Blocks
2 1920b 1280b 20b Pad

4 PAD (744b) 87
5 oFEC input 1
block Payload 2 Scrambled Payload,
area 3480x257b 3
Payload
and information
PAD
192 rows (FlexO-3)
(894,360 bits) . 3480x257-bit

7104 bits blocks
.
.
87
.
.
. B1
89
91 PAD (744b) 87 B12 6
92 1
...
87
PAD (744b) 87
192
1
1920b 1280b 20b Pad 87
. PAD (744b)
.
. Payload area
523

526For FlexO-2 58 rows (2,320-bit × 257-bit blocks) of information (596,240 bits) plus 496
527bits of pad (596,736 bits total) are scrambled and then bitwise demultiplexed to two
528oFEC encoders, each of which operate on input blocks of 3,552 bits and produce output
529blocks of 4,096 bits. To process the 596,736 bits each encoder operates on 84 input
530blocks of 7104 bits.
531
532
533
534
535
536
537
24
62
540
541
Scrambler Reset
to 0xFFFF
10280
5141
1920
3840
5120
5140
1921
3841
5121
1
rows Columns
84 oFEC Coder
2 1920b 1920b 1280b 20b Pad 56 Input Blocks
4 PAD (496b) 58
5 oFEC input 1
block Payload 2
Scrambled Payload,
area 2320x257b 3
Payload
and information
PAD
(596,240 bits)
128 rows (FlexO-2)
. 3480x257-bit
.
7104 bits blocks
.
58
.
.
. B1
61
62 PAD (496b) 58 B84
63 1
...
128
PAD (496b) 58 58
AM PAD OH Payload (5140 bits)
1
1 2
1920b 1280b 20b Pad
58
.
PAD (496b)
.
. Payload area
542
543
5458.5 Frame Synchronous Scrambling

546The scrambler/descrambler is located before oFEC encoder on transmit, and after the
547oFEC decoder on receive. The operation of the scrambler shall be functionally equivalent
548to that of a frame-synchronous additive scrambler of sequence 65535 and the generating
549polynomial shall be:
16 12 3
550 x +x + x + x+1.
551
552
553
554
555The scrambler/descrambler resets to 0xFFFF at the start of each new oFEC input block
556structure. The scrambler runs continuously over the entire oFEC input block. Figure 17
557shows a functional diagram of the frame synchronous scrambler.
25
64
558
Data In
+ + +
D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q +
S S S S S S S S S S S S S S S S
oFRAME CLK Scrambled
Data out
559 RESET
560 Figure 17: Frame synchronous scrambler
561
26
66
5629 Open Forward Error Correction (oFEC)

563NOTE: This section of the document uses zero-based indexing for mathematical formula
564convenience.
565
566The oFEC encoding block shown in Figure 18 consists of two FEC encoders/decoders
567(ENC0 and ENC1) operating in parallel. 7,104 bits are bit de-interleaved/interleaved
568to/from each encoder/decoder. The encoder expansion ratio is 4096/3552.
569
570The oFEC encoder and oFEC interleaver datapath is shown in Figure 18. The 7104 bits
571from the scrambler are bit demultiplexed into two parallel 3552/4096 encoder engines.
572Even numbered bits (0 based) go to encoder 0 (ENC0), and odd numbered bits to encoder
5731 (ENC1).
574
oFEC-x Coder Payload FlexO-x-oFEC

DP-8QAM: 1032192b
DP-QPSK: 688128b
3552 ENC0 4096

Scrambler 7104b Scrambler oFEC Interleaver Symbol
3552 ENC1 4096 Size = 172032b Map

DP-QPSK (4x)
575 84x: DP-QPSK
576 Figure 18: oFEC block encoder and oFEC Interleaver
5779.1 oFEC encoding codec

578Note: The section below describe a single instance of the oFEC encoder engine, i.e. one
579of ENC0 or ENC1 in Figure 18.
580
581For the Open ROADM 3.1 applications two encoding engines operate in parallel, with
582each engine producing an oFEC codeword. A codeword in oFEC is a semi-infinite set of
583bits organized in a matrix with semi-infinite number of rows and N columns (N = 128).
584It has the property that each bit is part of two “constituent component codewords,” in
585which each constituent component codeword is a binary vector x of length 2N satisfying
586the parity check constraint xH = 0, where H is a (2N, 2N – k) binary parity check matrix,
587with 2N > k > N. Here k = 239, and each constituent component codeword has (2N – k) =
58817 parity bits. The fraction of bits that are parity bits is 17/128, the rate of the code is
589111/128 = 0.867, and the overhead is 17/111 = 15.3%.
590Specifically in oFEC, H is a parity check matrix of an extended BCH(256, 239) code.
591This BCH code has a minimum Hamming distance of 6. oFEC uses a BCH textbook
592encoding with a parity check matrix H that is specified below.
27
68
593The constituent component codewords are ordered as explained below to allow high
594speed parallel encoding and decoding. To define what bits are part of a given constituent
595component component codeword the following structure is used:
596
597  The infinite matrix of bits is partitioned in square blocks of B × B bits (B = 16),
598 arranged in rows and columns as shown in Figure 19. There are N/B blocks per
599 row (N/B = 8), and each square block is identified by a square block row number,
600 R, and a square block column number, C, where C= 0, 1, … , N/B–1, appearing
601 respectively on the left hand side and at the top of the figure.
602
603  Each bit inside a square block is identified by its row number, r, where r = 0, 1,
604 …, B – 1, and column number, c, where c = 0, 1, …, B – 1, where bit 0, 0 is at the
605 upper left corner of a block. Overall, each bit in the infinite matrix is identified by
606 a quadruple {R, C, r, c}.
607
608  The number of guard-block rows needs to be even with a value 2G, (e.g. G = 2, or
609 2G = 4 rows, in Figure 19)
610
28
70
611
612 Figure 19: Structure of an openFEC
613
614
615
616A row of bits is identified by (R, r), with a square block row number R and a bit row
617number r within that block, where r = 0, 1, …, B – 1. A constituent component codeword
29
72
618can be identified by the number of the row that contains all bits of the 2 nd half of the
619codeword. The kth bit (k = 0, 1, …, 2N – 1) of constituent component codeword (R, r) is
620the bit identified with the quadruple:
621  If k < N: { (R ^ 1) – 2G − 2 N/B + 2 [k/B] , [k/B] , (k % B) ^ r , r } (1)
622  If k ≥ N: { R, [(k – N)/B] , r , (k % B) ^ r } (2)
623Where
624  [ . ] denotes the floor operator,
625  (a % b) denotes the value of a modulo b, and
626  (a ^ b) represents the number with a binary representation equal to the bit-wise “exclusive or” of
627 the binary representations of the numbers a and b.
628These formulas are illustrated in Figure 19. The union of line segments (both vertical or
629horizontal) of a given color shows the bits forming a constituent component codeword
630but the ordering in the segments is not the ordering in the codeword.
631For example, consider the constituent component codeword (20, 0). The position of its
632bits in the semi-infinite matrix are indicated by the red line segments. Bits 0 to 15 are in
633column 0 of block (1, 0), bits 16 to 31 in column 0 of block (3, 1), …, and bits 112 to 127
634in column 0 of block (15, 7). The bit indices go up as one descends in the columns.
635Bits 128 to 255 are located in row 0 of blocks (20, 0) to (20, 7), and their indices go up as
636one moves to the right in a row.
637Bits 0 to 127 are referred to as the “front” of a constituent component codeword, and bits
638128 to 255 as the “back.”
639Note that each bit in the oFEC encoder belongs to the front of a constituent component
640codeword and to the back of another one. Also, if the back of a constituent component
641codeword is in an odd-numbered row of square blocks (yellow background), then its front
642is an even-numbered row of square blocks (blue background), and conversely.
643The square blocks located below the “front bits” and above the “back bits” of a given
644constituent component codeword are so called guard blocks, relative to the constituent
645component codeword of interest.
646Continuing the example, the bits of constituent component codeword (20, 15), identified
647by the orange line segments, are in the same blocks as the segments of constituent
648component codeword (20, 0). However, because “r” is 15 instead of 0 as in the previous
649example, the expressions “ ^ r” in formulas (1) and (2) become significant, and the bits
650are taken in reverse order in each block. For example, bits 0 to 15 in the front of
651codeword (20, 15) are bits 15 to 0 in column 15 of block (1, 0).
652Note: The oFEC code is a block-convolutional code, and its performance is
653characterized by its “error events.” Without the “ ^ r” permutation, there are about
654625,000 possible error events of weight 36 that can start at every decoding of a
655constituent component codeword. For comparison, a Product Code based on the same
656constituent component codeword has more than 3.3e13 codewords of weight 36. The
657presence of the “ ^ r” permutation can be observed to eliminate error events of weight
65836. Consequently, the minimum Hamming distance of the oFEC code is at least 42.
30
74
6599.1.1 Encoding
660Encoding is done sequentially, in order of increasing row index. At the time when a
661constituent component codeword (R, r) is being encoded, all constituent component
662codewords (R’, r’) with R’ < R – 2G must be already be encoded.
663To encode a constituent component codeword (R, r), form a vector x of length 2N where
664the front N bits are read from previously encoded bits in the infinite matrix according to
665formula (1) above. In the back, the first k – N (i.e., 111) bits are fresh information bits.
666The last 2N – k (i.e., 17) back bits are parity bits that can be calculated to satisfy xH = 0.
667After encoding, the N back bits are placed at their positions in the infinite matrix
668according to formula (2) above, and bits in those positions are output to an interleaver.
669Considering Figure 19, we see that G is large enough to allow the parallel encoding of 2
670B (G + 1) = 96 constituent component codewords, assuming the pipeline delay is small.
671This number is considerably reduced when the pipeline delay increases, which is
672typically the case in the decoder.
673
674One can also see that at most N/B (N/B + 2 G + 1) = 104 square blocks need to be kept in
675the encoder memory (excluding the current input). The square blocks that must be kept in
676memory in order to encode block rows 20 and 21 are surrounded by the dashed line in
677Figure 19.
678
679A large G allows for longer pipeline delays in the encoding and decoding operations, and
680allows for more parallel execution in the encoder and decoder, at the expense of
681increased memory.
6829.1.2 Encoder interface
683The encoder input consists of rectangular blocks of size (2B) × (2N – k) = 32 × 111 bits.
684The encoder input blocks are numbered 0, 1, 2, …. The input bits into the encoder are
685sequenced. The ith input bit is placed in the encoder input block [i / (32 × 111)] at the
686position indicated by the value i % (32 × 111) in Figure 20. Note that an encoder input
687block is divided in 16×16 bit blocks, except along the right edge where their size is
68816×15.
689
690
691
692
693
694
695
696
697
698
699
700
701Bit k = 0, 1, 2… of row p in encoder input block P is placed in position N + k of
702constituent component codeword (2 P + [p/B], p % B).
31
76
703
0 1 … 15 512… 1024 … 1536 … 2048 … 2560 … 3072 3073 … 3086
16 17 ... 31 . . . . . 3087 … 3101
32… . . . . . 3102 … 3599
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
240 .. . 255 … 767 … 1279 … 1791 … 2303 … 2815 3297 … 3311
256… 271 768 … 1280 … 1792 .. 2304… 2816.. 3312 … 3326
272 . . . . . 3327 …
. . . . . . .
. . . . . . .
. . . . . . .
. . . . . . .
496 511 …. 1023 … 1535 … 2047 … 2559 … 3071 3537 … 3551
704
705 Figure 20: Sequencing of bits within an input block
706The encoder output consists of rectangular blocks of size (2 B) × N = 32 × 128 bits. The
707encoder output blocks are numbered 0, 1, 2, …. Bit k = 0, 1, 2, ... of row p in rectangle P
708is the bit {2P + [p/B], [p/B], k/B, p % B} of the semi-infinite array.
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727The bits within an output block are sequenced according to Figure 21.
728
729
32
78
0 1 … 15 512… 1024 … 1536 … 2048 … 2560 … 3072 3584
16 17 ... 31 . . . . . . .
32… . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
240 .. . 255 … 767 … 1279 … 1791 … 2303 … 2815 … 3327 … 3839
256… 271 768 … 1280 … 1792 .. 2304… 2816.. 3328 3840
272 . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
. . . . . . . .
496 511 …. 1023 … 1535 … 2047 … 2559 … 3071 … 3583 … 4095
730
731 Figure 21: Bit numbering within an output block
7329.1.3 Formal encoder definition

733This section directly describes the encoder (ENC0 or ENC1) output bits as a function of
734the input bits, integrating the diverse elements that have been described in previous
735sections.
736An oFEC encoder is an entity that produces a binary output y(i) from a binary input u(i),
737where i = 0, 1, 2, ….
738The relationship between y and u is expressed through intermediate variables.
739In particular, there is a four dimensional array V(R, C, r, c), where R is an integer; C = 0,
7401, …,7; r = 0, 1, …,15; and c = 0, 1, …, 15.
741Associated with array V, there are constituent component codeword vectors WR,rw with
742elements WR,r(i), where R ≥ 0, r = 0, 1. 2….15, and i = 0, 1, …, 255.
743
744 V((R ^ 1) − 20 + 2 [k/16] , [k/16] , (k % 16) ^ r , r ) for k < 128
745For R ≥ 0, WR,r(k) =
746 V(R, [(k − 128)/16] , r , (k % 16) ^ r ) for 128 ≤ k < 256
747
748
749Where,
750  [ . ] denotes the floor operator,
751  (a % b) denotes the value of a modulo b, and
33
80
752  (a ^ b) represents the number with a binary representation equal to the bit-wise “exclusive or” of
753 the binary representations of the numbers a and b.
754The bits in the WR,r satisfy the following equalities:
755For R ≥ 0, r = 0, 1, …, 15 and k = 0, 1, …, 110
756 WR,r(128 + k) = u([R/2] × 32 × 111 + ((R % 2) × 16 + r ) × (16 – [k/96]) + [k/16] × 512 + k % 16)
757
758For R ≥ 20, WR,r H = 0, where H is a parity check matrix of an extended BCH(256, 239)
759code, using a textbook encoding; i.e., if x is a vector satisfying xH = 0, then
760 1. x has an even parity, and
761 2. if the first 255 bits of x are seen as the binary coefficients of a polynomial x(t) of
762 degree 254 (with bit 0 of x being the coefficient of power 254), with t being the
763 indeterminate, then this binary polynomial x(t) is divisible by the binary
764 codeword generator polynomial t16 + t14 + t13 + t11 + t10 + t9 + t8 + t6 +t5 + t +1.
765The output y satisfies the relationship
766For R ≥ 0; C = 0, 1, ..., 7; r = 0, 1, …, 15; and c = 0, 1, …, 15.
767 V (R, C, r, c) = y([R/2] × 32 × 128 + (R % 2) × 256 + C × 16 × 32 + r × 16 + c)
768It can be observed that 20 × 16 ×17 values are left undefined in WR,r and in V(R, C, r, c)
769for 0 ≤ R < 20, and thus also in the output y. This is by design; an implementation can
770choose any convenient values.
771However, for test vectors, the output needs to be totally specified. To that end, the
772following additional constraints are added:
773For 0 ≤ R < 20, WR,r H’ = 0, where H’ is a 256 × 17 binary matrix where the first 128
774rows are all zero and the last 128 rows are equal to the last 128 rows of H.
7759.2 Decoding
776Any of the iterative algorithms designed for turbo decoding of Product Codes can easily
777be adapted to decode oFEC codewords.
778
779For use with iterative decoding, observe that the bits in square block row will all have
780been decoded as front bits in later constituent component codewords after 2 (N/B + G +
7811) rows of blocks have been decoded. Specifically, in Figure 19, bits in square block row
782R = 0 will all have been decoded as front bits by the time block row 21 has been decoded.
783It then makes sense to decode the constituent component codewords in block row 0
784again.
785
786
787
788
789
34
82
7909.3 oFEC Interleaver
791The FEC datapath is shown in Figure 18. After oFEC encoding, mapping the bit stream is
792interleaved by a block interleaver. The interleaver block size is 172,032 bits (42 encoder
793output blocks, 21 from ENC0 and 21 from ENC1). The number of interleaver blocks per
794FlexO-x-oFEC structure is dependent on the modulation:
795
796  DP-16QAM = (1376256/172032) = 8
797  DP-8QAM = (1032192/172032) = 6
798  DP-QPSK = (688128/172032) = 4
7999.3.1 oFEC Interleaver architecture
800The 172,032 bits in an interleaver block are organized as an (84, 8) array of 16 bit × 16
801bit square blocks; see Figure 22 below. Note that the format is similar to the format used
802by the encoder and decoder. We then apply the two following mechanisms:
803 1. An intra-block interleaver that reorders the bits in each 16×16 square block to
804 ensure that the bits in each row and column of a square block at the encoder
805 output are remapped almost uniformly in the square block for transmission on
806 the line. That operation can be seen as happening on input to the interleaver.
807 2. An inter-block interleaver that attempts to have nearby symbols on the line
808 contain bits that are widely separated in the encoder output.
809
810The interleaver is full rate, but it is fed by two half rate encoders, ENC0 and ENC1.
811Successive rows of square blocks from ENC0 will be written in even block rows of the
812interleaver buffer (yellowish colors in Figure 22), whereas successive rows of square
813blocks from ENC1 will be written in odd block rows (pinkish colors). Consequently, the
814content of an interleaver buffer is the square block row by square block row interleaving
815of vertical segments of the semi-infinite matrices of encoders ENC0 and ENC1.
8169.3.2 Intra-block interleaving
817For the purpose of intra-block interleaving, the interleaver is considered to receive 16 ×
81816 square blocks of bits from the encoders, and each square block is considered
819separately.
820
821
822
823
824
825
826
827
35
84
828The intra-block interleaving is specified by the following Table 3, which indicates the
829row and column of the source bit for each destination bit in the square block. For
830example, bit (14, 15) [base 0] encoder output block is placed in row 1 of column 0 of the
831corresponding interleaver square block.
832
Regular
Num Flips 99 Num CW: 32000
521 1222 2177 3494 4834 5800 5561 4232 2562 1181 326
99.8 96.1 86.5 71.5 56.4 39.9 27.7 18.1 10.9 8.4 4.3
99.6 95.2 83.6 66.1 48.4 31.6 19.6 11.1 6.4 3.8 1.8
0.2 0.7 2.4 4 5.8 5.4 4.5 3.5 2.1 2.5 0.9
0.3 3.8 13 25.8 38.2 50.1 59.3 66.3 70.2 73.2 75
521 1743 3920 7414 12248 18048 23609 27841 30403 31584 31910
Dest dist
Num Flips 99 Num CW: 32000
90 163 287 578 866 1357 1885 2619 3347 3901 4126
100 100 100 99.3 97.9 94 86.1 74.1 60.6 46 33.2
100 99.4 99.7 97.8 94.6 89 77.6 65.3 51.1 36.7 25.3
0 0.6 0 1.4 2.8 3.4 6.1 6.2 6.1 5.6 4.5
833
834 Table 3: Source positions (row, col) for intra-block interleaving
835Note: The left entries of the pairs in this table form a Latin Square. The right entries
836almost form a Latin square, but they are duplicated in the first and last rows.
8379.3.3 Inter-block interleaving
838The intra-block permutation described in the previous section is applied to each square
839block in the buffer as it comes in from the encoder.
840
841
842
843
844
845
846
847
848
849
850
36
86
851In addition to partitioning the interleaver buffer as a function of the encoder, ENC0 or
852ENC1, it is also partitioned in an upper half of 42 block rows (light color tones) and a
853lower half of 42 block rows (dark color tones). Overall the buffer is then partitioned in 4
854subsets, each containing 21 × 8 square blocks or 336 × 128 bits.
855
Subset Row Blocks

number
0 0, 2, …, 40
1 1, 3, …, 41
2 42, 44, …, 82
3 43, 45, …, 83
856 Table 4: Interleaver subsets
857On output, groups of 8 bits are taken in turn from each subset, reading them out of a
858column of bits before proceeding to the next columns of bits. These output bits form the
859FlexO-x-oFEC structure.
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
37
88
877Specifically, as shown in Figure 22, the first 8 bits are read from the top of first column
878of subset 0, then the first 8 bits from the first column of subsets 1, 2, and 3. Those 32 bits
879are then followed by the taking the next 8 bits in the first column of each of the subsets 0,
8801, 2, and 3. After 42 such cycles of 4 × 8 bits each, the first bit column of the interleaver
881buffer will be completely read out, and the output process continues by reading bit
882columns 1 to 127.
883
0 1 2 3 4 5 6 7
0
21504-21511, 21536-21543, ...
1
0-7, 32-39,...
2
8-15, 40-47,...
...
64-71, 96-103,...
...
...
...
38
39
40
41
16-23, 48-55,...
42 24-31, 56-63,...
43
44
...
...
...
...
80
81
82
1304-1311, 1336-1343, ͙ 21471-21503
83 ͙ , 171992-172007, 172024-172031
884
885 Figure 22: Inter-block interleaving
886
887Note: Bits are read by columns, rather than rows because interleaver columns are much
888longer than rows, so bits in a column are spread over more constituent component
889codewords than bits in a row, which increases the tolerance to long bursts. The
890maximum correctable burst length, when used with a hard decoder, is a traditional
891measure of interleaver quality. In this case it can be shown to be 2,681 bits.
38
90
892The bits read out of the interleaver are passed to the modulator where they are used in
893groups of S = 4, 6 or 8, for QPSK, 8QAM and 16QAM respectively in both the H and V
894polarizations.
895Note: The output bits with even indexes are used to form symbols for the H polarization,
896whereas those in odd positions are formed to symbols in the V polarization. This
897simplifies the line BER estimation in each polarization. The H and V bits will appear at
898fixed positions in each square block in the decoder independently of the modulation.
899
39
92
90010 Symbol Mapping and Polarization Distribution

901This section describes the procedure for mapping encoded and interleaved oFEC Blocks
902to DP-QPSK and DP-nQAM constellation symbols for distribution on each (X/Y)
903polarizations. This procedure is illustrated in Figure 23 below.
904
FlexO-x-oFEC

DP-8QAM: 1032192b
DP-QPSK: 688128b H
172032
3552 ENC0 4096
7104b Scrambler oFEC Interleaver Symbol 344064 Polarization
3552 ENC1 4096 Size = 172032b Map Distribution
V
172032
DP-QPSK (4x)
905 84x: DP-QPSK
906 Figure 23: DSP symbol mapping and polarization distribution
907
90810.1 Symbol mapping
909Symbol mapping is modulation dependent. Each FlexO-x-oFEC structure is mapped to
910172032 symbols in each polarization.
911
91210.1.1 DP-16QAM Symbols
913The FlexO-4-oFEC bits denoted by ck (k=0…1376255) are mapped to DP-16QAM
914symbols (S).
915
916 S=[s 0 , s1 , … , s 172031] ,
917
918Where,
919
920  (c 8 i , c8 i +2 ¿maps to the in-phase (I) component of the X-pol of si
921  (c 8 i+ 4 , c8 i +6 ¿ maps to the quadrature-phase (Q) component of the X-pol of si
922  (c 8 i+1 , c 8 i+3 ¿maps to the I component of the Y-pol of si
923  (c 8 i+5 , c 8 i+7 ¿maps to the Q component of the Y-pol of si
924
925In each signaling dimension, the following mapping from binary label to relative symbol
926amplitude is defined as:
927 (0,0)→-3,(0,1)→-1,(1,1)→+1,(1,0)→+3
928
40
94
929This mapping per polarization is further detailed in Table 5 below.
930
( c 8 i , c 8i +2 , c 8 i+4 , c 8 i+6 )∨(c 8 i+1 , c 8 i+3 , c 8 i+5 , c8 i +7) I Q
(0,0,0,0) -3 -3
(0,0,0,1) -3 -1
(0,0,1,0) -3 3
(0,0,1,1) -3 1
(0,1,0,0) -1 -3
(0,1,0,1) -1 -1
(0,1,1,0) -1 3
(0,1,1,1) -1 1
(1,0,0,0) 3 -3
(1,0,0,1) 3 -1
(1,0,1,0) 3 3
(1,0,1,1) 3 1
(1,1,0,0) 1 -3
(1,1,0,1) 1 -1
(1,1,1,0) 1 3
(1,1,1,1) 1 1
931 Table 5: DP-16QAM symbol amplitude map
932
93310.1.2 DP-8QAM Symbols
934
935The FlexO-3-oFEC bits denoted by ck (k=0…1032191) are mapped to DP-8QAM
936symbols (S),
937
938 S=[s 0 , s1 , … , s 172031] ,
939
940Where,
941
942  (c 6 i , c6 i +2 , c 6 i+ 4 ¿maps to the in-phase/quadrature-phase (I/Q) component of the X-
943 pol of si
944  (c 6 i+1 , c 6 i+3 , c6 i +5 ¿ maps to the I/Q component of the Y-pol of si
945
946
947
948
949
950
951
952
953In each polarization, we define the following map from binary label to relative symbol
954amplitudes:
41
96
955
( c 6 i , c 6 i+2 , c 6 i+4 )∨(c 6 i+1 , c6 i +3 , c 6 i+5 ) I Q
(0,0,0) 0 -1
(0,0,1) -1.366 -1.366
(0,1,0) -1.366 1.366
(0,1,1) -1 0
(1,0,0) 1.366 -1.366
(1,0,1) 1 0
(1,1,0) 0 1
(1,1,1) 1.366 1.366
956 Table 6: 8QAM symbol amplitude map
957
95810.1.3 DP-QPSK Symbols
959The FlexO-3-oFEC bits denoted by ck (k=0…688127) are mapped to DP-QPSK symbols
960(S),
961
962 S=[s 0 , s1 , … , s 172031] ,
963
964Where,
965
966  (c 4 i ¿maps to the in-phase (I) component of the X-pol of si
967  (c 4 i +2 ¿ maps to the quadrature-phase (Q) component of the X-pol of si
968  (c 4 i +1 ¿ maps to the I component of the Y-pol of si
969  (c 4 i +3 ¿ maps to the Q component of the Y-pol of si
970
971In each polarization, we define the following map from binary label to relative symbol
972amplitudes:
973
( c 4 i , c 4 i +2 )∨( c 4 i+1 , c 4 i+3 ) I Q
(0,0) -1 -1
(0,1) -1 1
(1,0) 1 -1
(1,1) 1 1
974 Table 7: DP-QPSK symbol amplitude map
975
42
98
97611 DSP Framing

977This section describes the DSP framing format. The DSP super-frame consists of 48 DSP
978sub-frames. The DSP frame length expressed in symbols is modulation independent. The
979frame format is defined for each polarization (X/Y).
980
Insert 576 Symbols 32/31
H FAW, Counter,
Pilot insert with
172032 Reserved 172608
spacing 31
178176 X pol
Symbols
Symbol Polarization
344064 FOICx-oFEC-DPmQAM
Map Distribution
V FAW, Counter,
Pilot insert with
172032 Reserved 172608
spacing 31
178176 Y pol
Symbols
981
982 Figure 24: DSP Frame generation
98311.1 DSP super-frame
984A DSP super-frame is defined as a set of 178176 symbols in each X/Y polarization. A
985DSP sub-frame consists of 3712 symbols. The DSP super-frame thus consists of 48 DSP
986sub-frames.
987Pilot Symbols (PS) are inserted every 32 symbols starting with the first symbol of the
988first DSP sub-frame. Each DSP sub-frame starts with an 11 symbol training sequence.
989The first symbol of the training sequence is a Pilot Symbol. The first DSP sub-frame of
990the super-frame also includes the DSP super-frame Frame Alignment Word (FAW).
991As illustrated in Figure 24 above, once the datastream has been mapped into symbols and
992distributed onto each polarization pilot symbols, training symbols, Frame Alignment
993Word (FAW), and other overhead are added to create the DSP super-frame/sub-frame
994structure. Pilot symbols, Training symbols, and FAW symbols are always mapped to the
995outer constellation points of the optical signal.
996
Parameter DP-16QAM DP-8QAM DP-QPSK
Constellation
Map
FAW 22 Symbols 22 Symbols 22 Symbols

TS 11 symbols per 11 symbols per 11 symbols per
DSP sub-frame DSP sub-frame DSP sub-frame
PS Every 32 symbols Every 32 symbols Every 32 symbols
997 Table 8: FAW/TS/PS pattern
998
43
100
99911.2 DSP sub-frame
1000Each DSP super-frame is divided into 48 DSP sub-frames and each DSP sub-frame
1001consists of 3,712 symbols.
1002
1003The first DSP sub-frame of the DSP super-frame includes a 22 symbol Frame Alignment
1004Word (FAW) used for alignment to the oFEC blocks. 74 additional symbols are reserved
1005for future use/innovation.
1006
1007The first DSP sub-frame includes:
1008  22 symbol super-frame Frame Alignment Word (FAW) used for super-frame
1009 delineation and alignment to the oFEC block. 74 additional symbols are
1010 reserved for future use/innovation. The FAW sequence is different between
1011 X and Y polarizations.
1012  74 symbols are reserved to be used for future proofing and for innovation.
1013 These symbols should be randomized to avoid strong tones.
1014  11 symbols available for link training. The first Training Symbol (TS) is
1015 shared as a Pilot Symbol (PS) in each DSP sub-frame.
1016  116 Pilot Symbols.
1017Every subsequent DSP sub-frame (sub-frames 2-48 of a DSP super-frame) include:
1018  11 symbols available for link training. The first Training Symbol (TS) is
1019 shared as a Pilot Symbol (PS) in each DSP sub-frame.
1020  116 Pilot Symbols
1021
1022 Figure 25: DSP super-frame
1023
44
102
1024
1025 Figure 26: DSP sub-frames 2 to 48 of the DSP super-frame
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
104611.3 FAW Sequence
1047
45
104
1048The required sequence and constellation corner relative symbol amplitude for the
104916QAM FAW is shown in Table 9.
1050
16QAM 8QAM QPSK
Inde
FAW (X) FAW (Y) FAW (X) FAW (Y) FAW (X) FAW (Y)
x
1 3-3j 3+3j 1.366-1.366j 1.366+1.366j 1-1j 1+1j
-
2 3+3j -3+3j 1.366+1.366j 1+1j -1+1j
1.366+1.366j
3 3+3j -3-3j 1.366+1.366j -1.366-1.366j 1+1j -1-1j
-
4 3+3j -3+3j 1.366+1.366j 1+1j -1+1j
1.366+1.366j
5 3-3j 3-3j 1.366-1.366j 1.366-1.366j 1-1j 1-1j
6 3-3j 3+3j 1.366-1.366j 1.366+1.366j 1-1j 1+1j
7 -3-3j 3-3j -1.366-1.366j 1.366-1.366j -1-1j 1-1j
8 3+3j 3-3j 1.366+1.366j 1.366-1.366j 1+1j 1-1j
9 -3-3j -3-3j -1.366-1.366j -1.366-1.366j -1-1j -1-1j
-
10 -3+3j 3-3j 1.366-1.366j -1+1j 1-1j
1.366+1.366j
-
11 -3+3j 3+3j 1.366+1.366j -1+1j 1+1j
1.366+1.366j
-
12 3-3j -3+3j 1.366-1.366j 1-1j -1+1j
1.366+1.366j
-
13 -3-3j -3+3j -1.366-1.366j -1-1j -1+1j
1.366+1.366j
14 -3-3j 3+3j -1.366-1.366j 1.366+1.366j -1-1j 1+1j
-
15 -3+3j -3-3j -1.366-1.366j -1+1j -1-1j
1.366+1.366j
16 3+3j 3+3j 1.366+1.366j 1.366+1.366j 1+1j 1+1j
17 -3-3j -3-3j -1.366-1.366j -1.366-1.366j -1-1j -1-1j
-
18 3-3j -3+3j 1.366-1.366j 1-1j -1+1j
1.366+1.366j
-
19 -3+3j 3-3j 1.366-1.366j -1+1j 1-1j
1.366+1.366j
20 3+3j -3-3j 1.366+1.366j -1.366-1.366j 1+1j -1-1j
21 -3-3j 3-3j -1.366-1.366j 1.366-1.366j -1-1j 1-1j
- -
22 -3+3j -3+3j -1+1j -1+1j
1.366+1.366j 1.366+1.366j
1051
1052 Table 9: FAW Sequence
1053
1054
1055
1056
46
106
1057
1058
105911.4 Training Sequence
1060
106216QAM TS is shown in Table 10. The constellation corner relative symbol amplitude for
1063the 8QAM TS and QPSK TS should be scaled per Table 6 and Table 7 respectively.
1064
16QAM 8QAM QPSK
Inde Training Training
Training (Y) Training (X) Training (Y) Training (Y)
x (X) (X)
1* -3+3j -3-3j -1.366+1.366j -1.366-1.366j -1+1j -1-1j
2 3+3j -3-3j 1.366+1.366j -1.366-1.366j 1+1j -1-1j
3 -3+3j 3-3j -1.366+1.366j 1.366-1.366j -1+1j 1-1j
4 3+3j -3+3j 1.366+1.366j -1.366+1.366j 1+1j -1+1j
5 -3-3j -3+3j -1.366-1.366j -1.366+1.366j -1-1j -1+1j
6 3+3j 3+3j 1.366+1.366j 1.366+1.366j 1+1j 1+1j
7 -3-3j -3-3j -1.366-1.366j -1.366-1.366j -1-1j -1-1j
8 -3-3j -3+3j -1.366-1.366j -1.366+1.366j -1-1j -1+1j
9 3+3j 3-3j 1.366+1.366j 1.366-1.366j 1+1j 1-1j
10 3-3j 3+3j 1.366-1.366j 1.366+1.366j 1-1j 1+1j
11 3-3j 3-3j 1.366-1.366j 1.366-1.366j 1-1j 1-1j
1065
1066 Table 10: Training symbol sequence
1067*The first symbol of the Training Sequence is processed as a pilot

1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
47
108
108411.5 Pilot Sequence
1085Training symbols and pilot symbols shall be set at the outer 4 points of the DP-nQAM
1086constellation.
1087The Pilot is a fixed PRBS10 mapped to the QPSK sequence with different seed values for
1088X/Y.
1089  Seeds are selected so that pilots are DC balanced

1090  Seeds are selected so that the 1st symbol in the training sequence is also the first
1091 symbol in the pilot sequence
1092  The seed is reset at the head of every DSP super-frame
2x115=230
2x115=230 bits
bits are
are
PRBS10
PRBS10 mapped
mapped toto outer
outer
with
with seed
seed == 0x19E
0x19E constellation
constellation points
points
2x115=230
2x115=230 bits
bits are
are
PRBS10
PRBS10 mapped
mapped toto outer
outer
with
with seed
seed == 0x0D0
0x0D0 constellation
constellation points
points
1094 Figure 27: Pilot Symbol (DP-16QAM modulation shown)
1095
1096
Generator polynomial Seed X Seed Y
x 10+ x 8 + x 4 + x 3 +1 0x19E 0x0D0
1097 Table 11: Pilot Sequence
1098
1099
48
110
Out X Out Y
0 0
Output -3+3i -3-3i
1 0
1 0
Seed X = 0x19E 0 1 1 0 0 1 1 1 1 0 +3+3i -3 -3i
1 0
Seed Y = 0x0D0 0 0 1 1 0 1 0 0 0 0 1 1
+3 -3i +3-3i
0 0
0 1
-3+3i +3 +3i
1 1
1 0
+3-3i -3-3i
0 0
1 1
+3-3i +3+3i
0 1
. .
. .
1100 . .
1101 Figure 28: Pilot Seed and Sequencing
110316QAM PS is shown in Table 12. The constellation corner relative symbol amplitude for
1104the 8QAM PS and QPSK PS should be scaled per Table 6 and Table 7 respectively.
1105
1106The complete table is shown below:
1107
16QAM 8QAM QPSK
Index Pilot X Pilot Y Pilot X Pilot Y Pilot X Pilot Y
-
1 -3+3i -3-3i -1.366-1.366i -1+1i -1-1i
1.366+1.366i
2 3+3i -3-3i 1.366+1.366i -1.366-1.366i 1+1i -1-1i
3 3-3i 3-3i 1.366-1.366i 1.366-1.366i 1-1i 1-1i
-
4 -3+3i 3+3i 1.366+1.366i -1+1i 1+1i
1.366+1.366i
5 3-3i -3-3i 1.366-1.366i -1.366-1.366i 1-1i -1-1i
6 3-3i 3+3i 1.366-1.366i 1.366+1.366i 1-1i 1+1i
7 -3-3i -3+3i -1.366-1.366i -1.366+1.366i -1-1i -1+1i
8 3+3i -3+3i 1.366+1.366i -1.366+1.366i 1+1i -1+1i
-
9 -3+3i -3-3i -1.366-1.366i -1+1i -1-1i
1.366+1.366i
10 3+3i 3+3i 1.366+1.366i 1.366+1.366i 1+1i 1+1i
11 3+3i 3+3i 1.366+1.366i 1.366+1.366i 1+1i 1+1i
12 -3-3i -3-3i -1.366-1.366i -1.366-1.366i -1-1i -1-1i
13 3+3i 3+3i 1.366+1.366i 1.366+1.366i 1+1i 1+1i
14 3-3i 3+3i 1.366-1.366i 1.366+1.366i 1-1i 1+1i
15 3+3i 3-3i 1.366+1.366i 1.366-1.366i 1+1i 1-1i
16 3-3i 3+3i 1.366-1.366i 1.366+1.366i 1-1i 1+1i
17 3+3i 3+3i 1.366+1.366i 1.366+1.366i 1+1i 1+1i
18 3-3i -3+3i 1.366-1.366i -1.366+1.366i 1-1i -1+1i
-
19 -3+3i -3-3i -1.366-1.366i -1+1i -1-1i
1.366+1.366i
20 -3-3i 3-3i -1.366-1.366i 1.366-1.366i -1-1i 1-1i
21 3+3i 3-3i 1.366+1.366i 1.366-1.366i 1+1i 1-1i
-
22 -3+3i 3+3i 1.366+1.366i -1+1i 1+1i
1.366+1.366i
49
112
16QAM 8QAM QPSK
-
23 -3+3i -3+3i -1.366+1.366i -1+1i -1+1i
1.366+1.366i
24 3-3i 3-3i 1.366-1.366i 1.366-1.366i 1-1i 1-1i
-
25 -3+3i 3-3i 1.366-1.366i -1+1i 1-1i
1.366+1.366i
-
26 -3+3i 3+3i 1.366+1.366i -1+1i 1+1i
1.366+1.366i
-
27 -3+3i -3+3i -1.366+1.366i -1+1i -1+1i
1.366+1.366i
-
28 -3+3i 3+3i 1.366+1.366i -1+1i 1+1i
1.366+1.366i
29 -3-3i 3+3i -1.366-1.366i 1.366+1.366i -1-1i 1+1i
30 3-3i 3-3i 1.366-1.366i 1.366-1.366i 1-1i 1-1i
31 -3-3i -3+3i -1.366-1.366i -1.366+1.366i -1-1i -1+1i
32 3+3i -3-3i 1.366+1.366i -1.366-1.366i 1+1i -1-1i
-
33 -3+3i 3-3i 1.366-1.366i -1+1i 1-1i
1.366+1.366i
-
34 -3+3i -3-3i -1.366-1.366i -1+1i -1-1i
1.366+1.366i
-
35 -3+3i -3-3i -1.366-1.366i -1+1i -1-1i
1.366+1.366i
36 3-3i 3-3i 1.366-1.366i 1.366-1.366i 1-1i 1-1i
37 3-3i 3-3i 1.366-1.366i 1.366-1.366i 1-1i 1-1i
38 -3-3i -3-3i -1.366-1.366i -1.366-1.366i -1-1i -1-1i
39 -3-3i 3+3i -1.366-1.366i 1.366+1.366i -1-1i 1+1i
40 3-3i -3-3i 1.366-1.366i -1.366-1.366i 1-1i -1-1i
41 -3-3i 3-3i -1.366-1.366i 1.366-1.366i -1-1i 1-1i
42 3-3i 3-3i 1.366-1.366i 1.366-1.366i 1-1i 1-1i
-
43 -3+3i -3-3i -1.366-1.366i -1+1i -1-1i
1.366+1.366i
-
44 -3+3i -3-3i -1.366-1.366i -1+1i -1-1i
1.366+1.366i
45 -3-3i 3+3i -1.366-1.366i 1.366+1.366i -1-1i 1+1i
-
46 -3+3i -3+3i -1.366+1.366i -1+1i -1+1i
1.366+1.366i
47 -3-3i 3+3i -1.366-1.366i 1.366+1.366i -1-1i 1+1i
48 3+3i -3+3i 1.366+1.366i -1.366+1.366i 1+1i -1+1i
49 3+3i 3-3i 1.366+1.366i 1.366-1.366i 1+1i 1-1i
-
50 -3+3i -3+3i -1.366+1.366i -1+1i -1+1i
1.366+1.366i
51 3-3i 3+3i 1.366-1.366i 1.366+1.366i 1-1i 1+1i
52 3-3i -3+3i 1.366-1.366i -1.366+1.366i 1-1i -1+1i
53 3-3i -3+3i 1.366-1.366i -1.366+1.366i 1-1i -1+1i
54 -3-3i 3+3i -1.366-1.366i 1.366+1.366i -1-1i 1+1i
55 3-3i -3+3i 1.366-1.366i -1.366+1.366i 1-1i -1+1i
56 3+3i -3+3i 1.366+1.366i -1.366+1.366i 1+1i -1+1i
50
114
16QAM 8QAM QPSK
-
57 -3+3i -3-3i -1.366-1.366i -1+1i -1-1i
1.366+1.366i
58 -3-3i 3-3i -1.366-1.366i 1.366-1.366i -1-1i 1-1i
59 3-3i 3-3i 1.366-1.366i 1.366-1.366i 1-1i 1-1i
60 3+3i -3+3i 1.366+1.366i -1.366+1.366i 1+1i -1+1i
61 3-3i 3+3i 1.366-1.366i 1.366+1.366i 1-1i 1+1i
62 -3-3i -3-3i -1.366-1.366i -1.366-1.366i -1-1i -1-1i
63 3-3i 3+3i 1.366-1.366i 1.366+1.366i 1-1i 1+1i
-
64 -3+3i -3+3i -1.366+1.366i -1+1i -1+1i
1.366+1.366i
65 3-3i 3-3i 1.366-1.366i 1.366-1.366i 1-1i 1-1i
66 3+3i 3+3i 1.366+1.366i 1.366+1.366i 1+1i 1+1i
67 3-3i -3-3i 1.366-1.366i -1.366-1.366i 1-1i -1-1i
-
68 -3+3i 3-3i 1.366-1.366i -1+1i 1-1i
1.366+1.366i
69 3-3i -3+3i 1.366-1.366i -1.366+1.366i 1-1i -1+1i
-
70 -3+3i -3+3i -1.366+1.366i -1+1i -1+1i
1.366+1.366i
71 3+3i -3+3i 1.366+1.366i -1.366+1.366i 1+1i -1+1i
72 -3-3i -3-3i -1.366-1.366i -1.366-1.366i -1-1i -1-1i
73 -3-3i -3+3i -1.366-1.366i -1.366+1.366i -1-1i -1+1i
74 3-3i 3+3i 1.366-1.366i 1.366+1.366i 1-1i 1+1i
-
75 -3+3i -3-3i -1.366-1.366i -1+1i -1-1i
1.366+1.366i
76 3-3i -3-3i 1.366-1.366i -1.366-1.366i 1-1i -1-1i
-
77 -3+3i -3-3i -1.366-1.366i -1+1i -1-1i
1.366+1.366i
78 -3-3i 3+3i -1.366-1.366i 1.366+1.366i -1-1i 1+1i
79 3+3i -3-3i 1.366+1.366i -1.366-1.366i 1+1i -1-1i
80 3+3i -3-3i 1.366+1.366i -1.366-1.366i 1+1i -1-1i
81 3+3i 3-3i 1.366+1.366i 1.366-1.366i 1+1i 1-1i
82 -3-3i -3-3i -1.366-1.366i -1.366-1.366i -1-1i -1-1i
83 -3-3i 3+3i -1.366-1.366i 1.366+1.366i -1-1i 1+1i
84 3+3i -3-3i 1.366+1.366i -1.366-1.366i 1+1i -1-1i
85 3-3i -3-3i 1.366-1.366i -1.366-1.366i 1-1i -1-1i
-
86 -3+3i -3-3i -1.366-1.366i -1+1i -1-1i
1.366+1.366i
87 3+3i 3-3i 1.366+1.366i 1.366-1.366i 1+1i 1-1i
88 3-3i -3+3i 1.366-1.366i -1.366+1.366i 1-1i -1+1i
89 -3-3i -3+3i -1.366-1.366i -1.366+1.366i -1-1i -1+1i
90 3-3i 3-3i 1.366-1.366i 1.366-1.366i 1-1i 1-1i
91 3-3i 3+3i 1.366-1.366i 1.366+1.366i 1-1i 1+1i
-
92 -3+3i 3-3i 1.366-1.366i -1+1i 1-1i
1.366+1.366i
51
116
16QAM 8QAM QPSK
93 -3-3i 3-3i -1.366-1.366i 1.366-1.366i -1-1i 1-1i
94 3+3i -3+3i 1.366+1.366i -1.366+1.366i 1+1i -1+1i
95 -3-3i 3-3i -1.366-1.366i 1.366-1.366i -1-1i 1-1i
96 -3-3i 3-3i -1.366-1.366i 1.366-1.366i -1-1i 1-1i
97 3+3i -3+3i 1.366+1.366i -1.366+1.366i 1+1i -1+1i
-
98 -3+3i 3-3i 1.366-1.366i -1+1i 1-1i
1.366+1.366i
99 3-3i -3-3i 1.366-1.366i -1.366-1.366i 1-1i -1-1i
100 -3-3i 3+3i -1.366-1.366i 1.366+1.366i -1-1i 1+1i
101 3+3i -3-3i 1.366+1.366i -1.366-1.366i 1+1i -1-1i
-
102 -3+3i -3+3i -1.366+1.366i -1+1i -1+1i
1.366+1.366i
103 -3-3i -3+3i -1.366-1.366i -1.366+1.366i -1-1i -1+1i
104 -3-3i 3+3i -1.366-1.366i 1.366+1.366i -1-1i 1+1i
105 3+3i -3+3i 1.366+1.366i -1.366+1.366i 1+1i -1+1i
106 3-3i 3-3i 1.366-1.366i 1.366-1.366i 1-1i 1-1i
107 3+3i 3+3i 1.366+1.366i 1.366+1.366i 1+1i 1+1i
-
108 -3+3i -3+3i -1.366+1.366i -1+1i -1+1i
1.366+1.366i
109 -3-3i 3+3i -1.366-1.366i 1.366+1.366i -1-1i 1+1i
-
110 -3+3i -3-3i -1.366-1.366i -1+1i -1-1i
1.366+1.366i
111 -3-3i -3+3i -1.366-1.366i -1.366+1.366i -1-1i -1+1i
-
112 -3+3i 3-3i 1.366-1.366i -1+1i 1-1i
1.366+1.366i
-
113 -3+3i -3+3i -1.366+1.366i -1+1i -1+1i
1.366+1.366i
114 3+3i 3+3i 1.366+1.366i 1.366+1.366i 1+1i 1+1i
115 3+3i 3-3i 1.366+1.366i 1.366-1.366i 1+1i 1-1i
116 -3-3i 3-3i -1.366-1.366i 1.366-1.366i -1-1i 1-1i
1108 Table 12: Pilot Sequence
1109
52
118
111012 Frame Expansion Rate

1111The oFEC optical signal is ~63.139467923 GBaud. Table 13 provides detail on expansion
1112for each functional block.
1113
Parameters Mapping
FEC Payload FlexO

FEC algorithm oFEC
FEC payload size (k) 3,552
FEC block size (n) 4,096
The number of FEC blocks in super frame 168(16QAM)/126(8QAM)/84(QPSK)
1,193,472(16QAM)
The total payload size 895,104(8QAM)
596,736(QPSK)
PAD before FEC 992(16QAM)/744(8QAM)/496(QPSK)
1,192,480b (16QAM) 4,640x257b
The total payload size based on 257b 894,360b (8QAM) 3,480x257b
596,240b (QPSK) 2,320x257b
PAD after FEC 0
1,376,256(16QAM)
The total bits 1,032,192(8QAM)
688,128(QPSK)
Total number of symbols per before DSP frame OH 172,032
The number of FAW symbols 22
The number of RES symbols 74
The number of Training Symbols 480
The number of Pilot Symbols (PS) 5,568
The total symbol of super-frame 178,176
DSP sub-frame symbols 3,712
The number of DSP sub-frames per super-frame 48
Modulation format 16QAM / 8QAM / QPSK
Baud rate ~63.139467923 GBaud*
1114 Table 13: FlexO/oFEC expansion rates
1115*63.139467923 (GBaud) = 447237897785.775×(514/544)×(37296/37265)×(4096/3552)×(899/896)×(32/31)/8
1116
53
120
111713 Appendix A – TRPN/MUXP/SWITCH client interface examples

1118
1119This Appendix A is provided for informational purposes only. There are no limitations or
1120assumptions about the allocation of functions on line cards or optical modules, however,
1121the most common configuration/implementations for a 200-400G Open ROADM
1122TRPN/MUXP/SWITCH node, are likely to include support of n (n=2,3,4) 100G OTN or
1123100GE Client ports. The Client ports are individually terminated and adapted for
1124transport over the FlexO-x-oFEC W-Port interface.
1125
1126The Client interface signaling is expected to conform to existing protocol standards (e.g.
1127G.709[6], G.709.1[7], and IEEE 802.3TM-2018[4]) and operate over standard physical layer
1128interface(s). The termination, mapping and/or aggregation of these payloads into the
1129FlexO-x frame structure is also fully specified in existing standards (e.g. the mapping and
1130aggregation of client interface signals via OTUCn (n=2,3,4) to a FlexO-x (x=n) frame
1131structure is fully specified by ITU-T G.709/Y.1331 and G.709.1/Y.1331.1). These
1132functions are not repeated here. What is included in this appendix are examples of several
1133common TRPN/MUXP/SWITCH configurations, for a FlexO-x-oFEC W-Port.
1134
1135Open ROADM 200-400G Transponder/Muxponder/Switch (TRPN/MUXP/SWITCH)
1136can support multiple Client interface types.
1137
1138OTN:
1139  OTUC/OTU4 (100G)
1140  OTUC2 (200G)
1141  OTUC3 (300G)
1142  OTUC4 (400G)
1143Ethernet:
1144  400GBASE-R
1145  200GBASE-R
1146  100GBASE-R
1147
1148A coherent transponder/muxponder/switch (TRPN/MUXP/SWITCH) function may
1149support the following sub functions:
1150
1151  Termination/generation of the Client interface PMD, PMA, and PCS layers.
1152  Performance monitoring, error detection and signaling.
1153  Mapping/de-mapping of Client interface data to/from an OTUCn
1154  Mapping/de-mapping one OTUCn signal (consisting of n×OTUC instances) into
1155 the payload of n FlexO signals.
1156  Interleave/de-interleave of n×FlexO (frame/multi-frame aligned) signals to a
1157 FlexO-x frame structure (x=2,3,4).
1158  FlexO-x-oFEC processing.
1159  Symbol mapping/de-mapping, polarization distribution, and optical framing.
54
122
1160  Modulation/demodulation of the symbol stream to/from a FOICx-oFEC-DP-
1161 nQAM signal.
116213.1 Transponder (TRPN)
1163Table 14 shows various Client interface types and number of instances supported by a
1164TRPN function by capacity:
1165
Client interfaces Line Interface
Capacity Mode 400GBASE-R 200GBASE-R OTUC4 OTUC3 OTUC2
(400G) (300G) (200G)
400G Transponder 1 FOIC4-oFEC-DP-16QAM
200G Transponder 1 FOIC2-oFEC-DP-QPSK
200G Transponder 1 FOIC2-oFEC-DP-QPSK
1166 Table 14: Open ROADM 3.0 Transponder (TRPN) functions
1167Note: For 100G Transponders reference Open ROADM 2.0 [2]

116813.2 Muxponder (MUXP)
1169An Open ROADM 3.0 200-400G MUXP may support aggregation of Client interfaces up
1170to its specified output bandwidth. The Client interface signals may or may not be
1171synchronous (from a common clock source). Client interfaces are mapped/multiplexed
1172per ITU-T G.709 into an OTUCn (n=2,3,4). Support of mixed traffic and/or traffic
1173originating from different sources can also be supported. Table 15 shows common
1174examples of MUXP Client interface combinations.
1175
Capacity Mode
Client Interfaces Line Interface
200GBASE-R 100GBASE-R OTUC/OTU4
400G Muxponder 2 FOIC4-oFEC-DP-16QAM
300G Muxponder 1 1 FOIC3-oFEC-DP-8QAM
200G Muxponder 2 FOIC2-oFEC-DP-QPSK

200G Muxponder 2 FOIC2-oFEC-DP-QPSK
1176 Table 15: Open ROADM 3.0 Muxponder (MUXP) functions
117713.3 Client interface bit rates

1178This section references ITU-T G.709[6],[7] to identify various Client interfaces, and their
1179nominal bit rate. The Client interface can be locally or externally originated. Examples
1180include:
1181
1182  A single externally originated ODUCn signal coming from a single 100G FlexO-
1183 n-RS, or from a group of m bonded FlexO-x-RS ports, i.e from a FlexO-x-RS-m
1184 group (mx=n).
1185  A single locally originated ODUCn carrying 100G or 400G Ethernet payloads.
1186  A single locally originated ODU4 signal coming from an OTN framer/mapper.
55
124
1187  100GE, 200GE, or 400GE signals coming from an Ethernet switch/router
1188 interface.
Client
Nominal bit rate tolerance
Interface
OTUC1 239/226 × 99.5328 Gbit/s = 105.258138053 Gbit/s ± 20 ppm
OTUC2 2 × 239/226 × 99.5328 Gbit/s = 210.516276106 Gbit/s ± 20 ppm
OTU4 239/227 × 99.5328 Gbit/s = 104.7944458 Gbit/s ± 20 ppm
100GE 100 Gbit/s = 103.125 Gbit/s (66b/66b) ± 100 ppm
200GE 2×20479/20480 × 103.125 Gbit/s = 206.239929199 Gbit/s ± 100 ppm
400GE 4×20479/20480 × 103.125 Gbit/s = 412.4798583984 Gbit/s ± 100 ppm
1189 Table 16 Client interface types and payload bit rates
1190For Open ROADM, the TRPN/MUXP/SWITCH function client interface(s) may or may
1191not include FEC. When FEC is present the FEC is terminated at the Client interface sink
1192function (e.g. PMD, PMA and lower layer PCS) before being processed to a FlexO-x-
1193oFEC signal.
1194
1195Table 17 defines the FlexO-x frame structure rates for the possible FlexO-x-oFEC signals
1196prior to the addition of any oFEC overhead (reference Section 7 details).
1197
FlexO-x frame
Nominal bit rate tolerance
structure
FlexO-2 (200G) 2 × (239/226) × (4112/4097) × 99.5328 Gbit/s = 211.287021564 Gbits/s ± 20 ppm
1198 Table 17: Line types and frame bit rates
1199
1200End of Document
56

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2 MSA_3.01 W-Port Digital Specification

891 List of Figures.........................................................................................6

11910 Symbol Mapping and Polarization Distribution...............................40

1371 List of Figures

1682 List of Tables

1883 Document Revision History

1934 Scope and Introduction

FlexO FlexO-x oFEC-x Coder Payload FlexO-x-oFEC

oFEC Coder DP-16QAM: 1376256b

300G - 87 rows (3480 x 257b) 894360b Scrambler 7104b 344064 Polarization

168x DP-16QAM DP-16QAM (8x) spacing 31

243 Per ITU-T G.709.1/Y.1331

244 Figure 3: Digital port functions for a single FlexO-x-OFEC signal

3487 FlexO-x frame structure

128 Payload (5140 bits)

rows 960b 960b 640

414The interleaving process is shown in Figure 7.

424The FlexO-3 frame structure is shown in Figure 8.

rows 1440 1440 960b

128 128 128

432 Figure 9: Interleaved FlexO frame to FlexO-3 frame structure

439The FlexO-4 frame structure is shown in Figure 10.

rows 1920b 1920b 1280b

128 128 128 128

447 Figure 11: Interleaved FlexO frame to FlexO-4 frame structure

4528 FlexO-x-oFEC adaptation

FlexO-3-oFEC 87 rows, (3480×257 bits) 744 895,104 126 1,032,192 DP-8QAM

oFEC Coder DP-16QAM: 1376256b

168x DP-16QAM DP-16QAM (8x)

484 84x: DP-QPSK DP-QPSK (4x)

485 Figure 13: Digital processes of FlexO-x to FlexO-x-oFEC adaptation.

4868.1 Padding Insertion/Removal

3 Payload (10280 bits) 115

(1,192,480 bits) . 3480x257-bit

Payload (10280 bits)

5048.3 FlexO-3 adaptation to oFEC input blocks

3 Payload (10280 bits) 86

(894,360 bits) . 3480x257-bit

5258.4 FlexO-2 adaptation to oFEC input blocks

Payload (10280 bits)

5458.5 Frame Synchronous Scrambling

560 Figure 17: Frame synchronous scrambler

5629 Open Forward Error Correction (oFEC)

oFEC Coder DP-16QAM: 1376256b

3552 ENC0 4096

168x DP-16QAM DP-16QAM (8x)

576 Figure 18: oFEC block encoder and oFEC Interleaver

5779.1 oFEC encoding codec

7329.1.3 Formal encoder definition

Subset Row Blocks

856 Table 4: Interleaver subsets

90010 Symbol Mapping and Polarization Distribution

oFEC Coder DP-16QAM: 1376256b

906 Figure 23: DSP symbol mapping and polarization distribution

97611 DSP Framing

98311.1 DSP super-frame

FAW 22 Symbols 22 Symbols 22 Symbols

1067*The first symbol of the Training Sequence is processed as a pilot

1089  Seeds are selected so that pilots are DC balanced

1094 Figure 27: Pilot Symbol (DP-16QAM modulation shown)

1101 Figure 28: Pilot Seed and Sequencing

111012 Frame Expansion Rate