Microprocessor: - This is a normal CPU (Central Processing Unit) as you can • Less flexible since the additional circuits

e additional circuits which is residing Pins10-17 PORT 3. Similar to port 1, each of these pins can serve as
find in a PC. Communication with external devices is achieved via a data bus, inside the microcontroller is fixed for a particular general input or output. Besides, all of them have alternative function
hence the chip mainly features data and address pins as well as a couple of control microcontroller
pins. • Limited number of instructions with few addressing modes
Microcontroller: - A single chip used to control other devices. A microcontroller Classification of Microprocessors
already contains all components which allow it to operate standalone, and it has Based on application Pin 10 RXD. Serial asynchronous communication input or Serial
been designed in particular for monitoring and/or control tasks. • General-purpose microprocessor- used in general synchronous communication output.
Bit: A bit is a single binary digit. computer system and can be used by programmer for any Pin 11 TXD. Serial asynchronous communication output or Serial
Word: A word refers to the basic data size or bit size that can be processed by the application. Examples, 8085 to Intel Pentium. synchronous communication clock output.
arithmetic and logic unit of the processor. A 16-bit binary number is called a word • Microcontroller- microprocessor with built-in memory Pin 12 INT0.External Interrupt 0 input
in a 16-bit processor. and ports and can be programmed for any generic control Pin 13 INT1. External Interrupt 1 input
Bus: A bus is a group of wires/lines that carry similar information. application. Example, 8051. Pin 14 T0. Counter 0 clock input
System Bus: The system bus is a group of wires/lines used for communication • Special-purpose processors- designed to handle special Pin 15 T1. Counter 1 clock input
between the microprocessor and peripherals. functions required for an application. Examples, digital Pin 16 WR. Write to external (additional)
Memory Word: The number of bits that can be stored in a register or memory signal processors and application-specific integrated circuit RAM
element is called a memory word. (ASIC) chips. • Pin 17 RD. Read from external RAM
Address Bus: It carries the address, which is a unique binary pattern used to Based on instruction set architecture
identify a memory location or an I/O port. For example, an eight-bit address bus • RISC- Reduced Instruction Set Architecture
has eight lines and thus it can address 2^8 = 256 different locations. The locations The hardware is made simpler by having instructions composed of
in hexadecimal format can be written as 00H – FFH. several steps for loading, evaluating and storing operations. • Pin 18, 19 XTAL2, XTAL1. Internal oscillator
Data Bus: The data bus is used to transfer data between memory and processor or • CISC – Complex Instruction Set Architecture input and output. A quartz crystal which specifies operating
between I/O device and processor. For example, an 8-bit processor will generally The hardware is made complex such that you need simpler instructions frequency is usually connected to these pins.
have an 8-bit data bus and a 16-bit processor will have 16-bit data bus. to carry out an operation.
Control Bus: The control bus carry control signals, which consists of signals for CISC
selection of memory or I/O device from the given address, direction of data • Instruction takes one or two cycles
transfer and synchronization of data transfer in case of slow devices. • Only load/store instructions are used to access memory • Pin 20 GND. Ground.
Instruction Set: A group of commands that a specific microprocessor can • Instructions executed by hardware • Pin 21-28 Port 2. If there is no intention to use external
understand. • Instructions executed by the micro program memory then these port pins are configured as general
• Fixed format instruction inputs/outputs. In case external memory is used, the higher
• Few addressing modes address byte, i.e. addresses A8-A15 will appear on this
port. Even though memory with capacity of 64Kb is not
• Few instructions
used, which means that not all eight port bits are used for
• Most of the have multiple register banks
its addressing, the rest of them are not available as
• Highly pipelined
inputs/outputs.
• Complexity is in the compiler
• Pin 29 PSEN. If external ROM is used for storing program
RISC
then a logic zero (0) appears on it every time the
• Instruction takes multiple cycles
microcontroller reads a byte from memory.
• In additions to load and store instructions, memory access
• Pin 30 ALE. Prior to reading from external memory, the
is possible with other instructions also.
microcontroller puts the lower address byte (A0-A7) on P0
• Variable format instructions
and activates the ALE output. After receiving signal from
• Many addressing modes
the ALE pin, the external latch latches the state of P0 and
• Complex instruction set uses it as a memory chip address. Immediately after that,
• Single register bank the ALE pin is returned its previous logic state and P0 is
………………………………………………………………………………… • Less pipelined now used as a Data Bus.
• Complexity in the microprogram • Pin 31 EA. By applying logic zero to this pin, P2 and P3
are used for data and address transmission with no regard to
Based on Memory and bus Usage: whether there is internal memory or not. It means that even
Von-Nuemann Architecture – The program and data are stored in the there is a program written to the microcontroller, it will not
same memory and are therefore accessed with the same bus. be executed. Instead, the program written to external ROM
will be executed. By applying logic one to the EA pin, the
microcontroller will use both memories, first internal then
external (if exists).
• Pin 32-39 PORT 0. Similar to P2, if external memory is
not used, these pins can be used as general inputs/outputs.
Otherwise, P0 is configured as address output (A0-A7)
when the ALE pin is driven high (1) or as data output (Data
Bus) when the ALE pin is driven low (0).
Harvard Architecture – The program and data are stored in separate • Pin 40 VCC. +5V power supply.
MICROCONTROLLER FEATURES memory spaces and are accessed separately. PORT 0
Processor Core: The CPU of the controller. It contains the arithmetic logic
unit, the control unit, and the registers (stack pointer, program counter,
accumulator register, register file, . . .).
Memory: The memory is sometimes split into program memory and data
memory. In larger controllers, a DMA (Direct Memory Access) controller
handles data transfers between peripheral components and the memory.
Interrupt Controller: Interrupts are useful for interrupting the normal program
flow in case of (important) external or internal events. In conjunction with sleep
modes, they help to conserve power.
Timer/Counter: Most controllers have at least one and more likely 2-3 Von Neumann
Timer/Counters, which can be used to timestamp events, measure intervals, or • It uses single memory space for both instructions and data.
count events. • It is not possible to fetch instruction code and data
Many controllers also contain PWM • Execution of instruction takes more machine cycle
(pulse width modulation) outputs, which • Uses CISC architecture PORT 0 as an Input Port
can be used to drive motors or for safe • Instruction pre-fetching is a main feature Let us assume that control is ‘0’. When the port is used as an input port, ‘1’ is
breaking (antilock brake system, ABS). • Also known as control flow or control driven computers written to the latch. In this situation both the output MOSFETs are ‘off’. Hence
Furthermore, the PWM output can, in • Simplifies the chip design because of single memory space the output pin have floats hence whatever data written on the pin is directly read
conjunction with an external filter, be Harvard by read pin.
used to realize a cheap digital/analog • It has separate program memory and data memory PORT 0 as an Output Port
converter. Digital I/O: Parallel digital • Instruction code and data can be fetched simultaneously Suppose we want
I/O ports are one of the main features of • Execution of instruction takes less machine cycle towrite1on pin of Port 0, a
microcontrollers. The number of I/O • Uses RISC architecture ‘1’ written to the latch
pins varies from 3-4 to over 90, • Instruction parallelism is a main feature which turns ‘off’ the
depending on the controller family and lower FET while due to
• Also known as data flow or data driven computers
the controller type. ‘0’ control signal upper
E.g. General-purpose microcontrollers,
MICROCONTROLLER COMPONENTS FET also turns off as
• Chip design is complex due to separate memory space E.g.
Analog I/O: Apart from a few small controllers, most microcontrollers have shown in fig. above. Here
8085, 8086, MC6800
integrated analog/digital we want logic ‘1’ on pin
Features of 8051 microcontroller
converters, which differ in the number of channels (2-16) and their resolution (8- but we getting floating
 8-bit CPU
12 bits). The value so to convert that
analog module also generally features an analog comparator. In some cases, the  16-bit Program Counter
floating value into logic
microcontroller  16-bit address bus
‘1’ we need to connect the
includes digital/analog converters.  8-bit Processor Status Word (PSW)- a word that describes pull up resistor parallel to
Interfaces: Controllers generally have at least one serial interface which can be fully the condition of the processor at all times upper FET. This is the
used to download the  8-bit Stack Pointer reason why we needed to
program and for communication with the development PC in general. Since serial  Internal RAM of 128bytes connect pull up resistor to
interfaces  Special Function Registers (SFRs) of 128 bytes port 0 when we want to
can also be used to communicate with external peripheral devices, most  32 I/O pins arranged as four 8-bit ports (P0 - P3) initialize port 0 as an
controllers offer several  Two 16-bit timer/counters: T0 and T1Features of 8051 output port .If we want to
and varied interfaces like SPI and SCI. microcontrollers write ‘0’ on pin of port 0 ,
Many microcontrollers also contain integrated bus controllers for the most  Two external and three internal vectored interrupts when ‘0’ is written to the
common (field)busses.  One full duplex serial I/O latch, the pin is pulled
IIC and CAN controllers lead the field here. Larger microcontrollers may also  40 pin microcontrollers down by the lower FET.
contain PCI, Hence the output becomes
USB, or Ethernet interfaces. zero.
Watchdog Timer: Since safety-critical systems form a major application area of PORT 1
microcontrollers, it
is important to guard against errors in the program and/or the hardware. The
watchdog timer is
used to reset the controller in case of software “crashes”.
Debugging Unit: Some controllers are equipped with additional hardware to
allow remote debugging
of the chip from the PC. So there is no need to download special debugging
software,
which has the distinct advantage that erroneous application code cannot overwrite
the debugger.
Microcontroller
• Microprocessor contains ALU, General purpose registers,
stack pointer, program counter, clock timing circuit,
interrupt circuit USED AS OUTPUT PORT
• It has many instructions to move data between memory and No need to connect additional pull up resistor like port 0. It has internally
CPU provided pull up resistor. The pin is pulled up or down through internal pull-up
• Few bit handling instruction when we want to initialize as an output port.
• Less number of pins are multifunctional PORT 1 AS INPUT
• Single memory map for data and code (program) To use port-1 as input port, ‘1’ has to be written to the latch. In this input mode
• Access time for memory and IO are more when ‘1’ is written to the pin by the external device then it is read fine. But when
• Microprocessor based system requires additional hardware ‘0’ is written to the pin by the external device then the external source must sink
• More flexible in the design point of view current due to internal pull-up. If the external device is not able to sink the current
• Large number of instructions with flexible addressing the pin voltage may rise, leading to a possible wrong reading.
modes PORT 2
Microprocessor
• Microcontroller contains the circuitry of microprocessor,
and in addition it has built in ROM, RAM, I/O Devices,
Timers/Counters etc.
• It has few instructions to move data between memory and Pins 1-8 PORT 1. Each of these pins can be configured as an
CPU input or an output.
• It has many bit handling instructions Pin 9 RESET. A logic one on this pin disables the
• More number of pins are multifunctional microcontroller and clears the contents of most registers. In other
• Separate memory map for data and code (program) words, the positive voltage on this pin resets the microcontroller. By
• Less access time for built in memory and IO. applying logic zero to this pin, the program starts execution from the
• It requires less additional hardware beginning.

We use for higher external address byte or a normal input/output port The I/O
operation is similar to Port-1. Port-2 latch remains stable whenPort-2 pin are used
for external memory access.
Here again due to internal pull-up there is limited current driving capability.
PORT 3
Each pin of Port-3 can be individually programmed for I/O operation or for
alternate function.
The alternate function can be activated only if the corresponding latch has been
written to '1'. To use
the port as input port, '1' should be written to the latch. This port also has internal
pull-up and limited
current driving capability.
8051 MEMORY ARCHITECTURE
8051 employs Harvard architecture. The memory is organized logically into
program memory and data memory separately. The program memory is read-only
type; the data memory is organized as read-write memory.
INTERNAL DATA MEMORY AND SPECIAL FUNCTION REGISTER
(SFR)MAP
8051 MEMORY ARCHITECTURE
Register Banks: (Store program instructions) 00h to 1Fh.
The lower 32 bytes are divided into 4 separate banks. Each
register bank has 8 registers of one byte each, R0 through R7
(R0, R1, R2, R3, R4, R5, R6, and R7)
A register bank is selected depending upon two banks select
bits; RS1, RS0 bits of PSW. On reset, the default Register
Bank 0 will be selected.
Bit Addressable RAM: 20h to 2Fh. Next 16bytes are bit
addressable. The
8051 supports a special feature which allows access to bit
variables. In total, 128bits (16X8) are available in bit
addressable area. Each bit can be accessed and modified by
suitable instructions. The bit addresses are from 00H (LSB of
the first byte in 20H) to 7FH (MSB of the last byte in 2FH).
The special function registers (SFRs) are mapped in the upper 128
bytes of internal data memory address. Hence there is an address
overlap between the upper 128 bytes of data RAM and SFRs. The
upper 128 bytes of data RAM are present only in the 8052
family.
The lower128 bytes of RAM (00H - 7FH) can be accessed both by
direct or indirect addressing while the upper 128 bytes of RAM (80H
- FFH) are accessed by indirect addressing.
SPECIAL FUNCTION REGISTERS
Processor Status Word (PSW) Address=D0H
PSW register stores the important status conditions of the
microcontroller. It also stores the bank select bits (RS1 & RS0)
for register bank selection.
THE PIN CONNECTION FOR EXTERNAL CODE AND DATA
MEMORY
The Pin Connection for External Code and Data Memory
The lower order address and data bus are multiplexed. De-
multiplexing is done by the latch. Initially the address will
appear in the bus and this latched at the output of latch using
ALE signal. The output of the latch is directly connected to
the lower byte address lines of the memory. Later data will
be available in this bus. Still the latch output is the address.
The higher byte of address bus is directly connected to the
memory. The number of lines connected depends on the
memory size.
The RD and WR (both active low) signals are connected to
RAM for reading and writing the data.
PSEN of microcontroller is connected to the output enable of the
ROM to read the data from the memory.
External program memory is fetched if either of the
following two conditions are satisfied.
…EA (Enable Address) is low. The microcontroller by default
starts searching for program from external program memory.
…PC is higher than FFFH for 8051. Otherwise, once the
program size exceeds internal memory the microcontroller will
automatically switch to external memory.
MEMORY INTERFACE TIMING DIAGRAM
STACK
The stack is a section of RAM used by the CPU to store
information temporarily. This information could be data or an
address. The CPU needs this storage area since there are only
a limited number of registers.
If the stack is a section of RAM, there must be registers inside the CPU to point to
it. The register used to access the stack is called the SP (stack pointer) register.
The storing of a CPU register in the stack is called a PUSH, and pulling the
contents off the stack back into a CPU register is called a POP. In other words, a
register is pushed onto the stack to save it and popped off the stack to retrieve it.
The job of the SP is very critical when push and pop actions are performed.
8051 STACK ACTION
In 8051 internal RAM space can be used as stack.
The address of the stack is contained in a register called stack
pointer.
Instructions PUSH and POP are used for stack operations.
When a data is to be placed on the stack, the stack pointer
increments before storing the data on the stack so that the stack
grows up as data is stored (pre-increment).
As the data is retrieved from the stack the byte is read from the
stack, and then SP decrements to point the next available byte
of stored data (post decrement).
TIMER/COUNTER IN 8051 (USES)
Time reference
Creating delay
Periodic interrupt generation
Waveform generation
Event counters
Baud Rate generators
TIMER MODES
TIMER MODE 0
The lower 5 bits of TLX and 8 bits of THX are used for the 13 bit count.
Upper 3 bits of TLX are ignored. The input pulse is obtained from the
previous stage. If TR1/0 bit is 1 and Gate bit is 0, the counter continues
counting up. If TR1/0 bit is 1 and Gate bit is 1, then the operation of the
counter is controlled by input. When the counter rolls over from all 0's to
all 1's, TFX flag is set and an interrupt is generated. This mode is useful to
measure the width of a given pulse fed to input.
Timer Mode-1
This mode is similar to mode-0 except for the fact that the Timer operates in 16-
bit mode.
Timer - Mode 2
It is an 8-bit timer that allows only values of 00 to FFH to be loaded into the
timer’s register TH.
After TH is loaded with 8-bit value, the 8051 gives a copy of it to TL.
Then the timer must be started. It is done by the instruction “SETB TR0”
for timer 0 and “SETB TR1” for timer1. This is like mode 1.
After timer is started, it starts to count up by incrementing the TL register. It
counts up until it reaches its limit of FFH. When it rolls over from FFH to 00. It
sets high the TF (timer flag). If we are using timer 0, TF0 goes high; if using TF1
then TF1 is raised. When Tl register rolls from FFH to 00 and TF is set to 1, TL is
reloaded automatically with the original value kept by the TH register. To repeat
the process, we must simply clear TF and let it go without any need by the
programmer to reload the original value. This makes mode 2 auto reload, in
contrast in mode 1 in which programmer has to reload TH and TL.
Timer Mode-3
Mode 3 is also known as a split timer mode. Timer 0 and 1 may be programmed
to be in mode 0, 1 and 2 independently of similar mode for another timer. This is
not true for mode 3; timers do not operate independently if mode 3 is chosen for
timer 0. Placing timer 1 in mode 3 causes it to stop counting; the control bit TR1
and the timer 1 flag TF1 are then used by Timer 0
Timer 1 in mode-3 simply holds its count. The effect is same as setting TR1=0.
Timer0 in mode-3 establishes TL0 and TH0 as two separate counters.
POWER SAVING MODES OF OPERATION
Idle Mode
Power Down mode.
The two power saving modes are entered by setting two bits IDL and PD in the
special function register (PCON) respectively.
The structure of PCON register is as follows.
PCON: Address 87H
Idle Mode
Idle mode is entered by setting IDL bit to 1 (i.e.IDL =0). The
off to CPU, but not to the interrupt, timer and serial port functions. The CPU
status is preserved entirely.
Ways to exit Idle Mode:
…Activation of any enabled interrupt will clear PCON.0 bit and hence the Idle
Mode is exited
…The program goes to the Interrupt Service Routine (ISR). After RETI is
executed at the end of the ISR, the next instruction will start from the one
following the instruction that enabled Idle Mode.
…A hardware reset exits the idle mode. The CPU starts from the instruction
following the instruction that invoked the 'Idle' mode.
DATA COMMUNICATION
The 8051 microcontroller is parallel device that transfers eight bits of data
simultaneously over eight data lines to parallel I/O devices.
SERIAL DATA COMMUNICATION
In SERIAL DATA 8-bit data is converted to serial bits using a parallel in serial
out shift register and then it is transmitted over a single data line. The data byte is
always transmitted with least significant bit first.
Communication Links
Simplex communication link: In simplex transmission, the line is dedicated for
transmission. The transmitter sends and the receiver receives the data.
Half duplex communication link: In half duplex, the communication link can be
used for either transmission or reception. Data is transmitted in only one direction
at a time.
Full duplex communication link: If the data is transmitted in both ways at the
same time, it is a full duplex i.e. transmission and reception can proceed
simultaneously. This communication link requires two wires for data, one for
transmission and one for reception.
Serial data communication uses two types of communication.
Synchronous serial data communication: In this transmitter and receiver
are synchronized. It uses a common clock to synchronize the receiver and the
transmitter. First the synch character is sent and then the data is transmitted.
Asynchronous Serial data transmission: In this, different clock sources are
used for transmitter and receiver. In this mode, data is transmitted with start
and stop bits. A transmission begins with start bit, followed by data and then
stop bit. For error checking purpose parity bit is included just prior to stop bit.
In Asynchronous serial data communication, a single byte is transmitted at a
time.
REGISTERS IN SERIAL COMMUNICATION
SBUF Register: Serial Buffer (SBUF) register is an 8-
bit register. It has separate SBUF registers for data
transmission and for data reception. For a byte of data to
be transferred via the TXD line, it must be placed in
SBUF register (Write only). Similarly, SBUF holds the
8-bit data received by the RXD pin and read to accept
the received data (Read Only).
SCON register: The contents of the Serial Control
(SCON) register are shown below. This register contains
mode selection bits, serial port interrupt bit (TI and RI)
and also the ninth data bit for transmission and reception
(TB8 and RB8).
Data Transmission
Transmission of serial data begins at any time when data is written to SBUF. Pin
P3.1 (Alternate function bit TXD) is used to transmit data to the serial data
network. TI is set to 1 when data has been transmitted. This signifies that SBUF is
empty so that another byte can be sent.
Data Reception
Reception of serial data begins if the receive enable bit is set to 1 for all modes.
Pin P3.0 (Alternate function bit RXD) is used to receive data from the serial data
network. Receive interrupt flag, RI, is set after the data has been received in all
modes. The data gets stored in SBUF register from where it can be read.
BASICS OF INTERRUPTS
During program execution if peripheral devices needs service from
microcontroller, device will generate interrupt and gets the service from
microcontroller. When peripheral device activates the interrupt signal, the
processor branches to a program called interrupt service routine. After executing
the interrupt service routine, the processor returns to the main program.
Steps taken by processor while processing an interrupt:
It completes the execution of the current instruction.
PSW is pushed to stack.
Program Counter content is pushed to stack.
Interrupt flag is reset.
Program Counter is loaded with ISR address.
ISR will always ends with RETI (Return from Interrupt) instruction. The
execution of RETI instruction results in the following.
POP the current stack top to the Program Counter.
POP the current stack top to PSW.
Classification of interrupts
External and internal interrupts
External interrupts are those initiated by peripheral devices
through the external pins of the microcontroller.
Internal interrupts are those activated by the internal
peripherals of the microcontroller like timers, serial
controller etc.
Maskable and non-maskable interrupts
The category of interrupts which can be disabled by the
processor using a program is called maskable interrupts.
Non-maskable interrupts are those categories by which the
programmer cannot disable using program.
Vectored and non-vectored interrupt.
The starting address of the ISR is called interrupt vector. In
vectored interrupts the starting address is predefined. In
non-vectored interrupts, the starting address is provided by
the peripheral as follows:
Microcontroller receives an interrupt request from external
device.
Controller sends an acknowledgement (INTA) after
completing the execution of current instruction.
The peripheral device sends the interrupt vector to the
microcontroller.
Interrupt Enable Register(IE)
This is an 8 bit register used for enabling or disabling the interrupts. The structure
of IE register is shown below.
EA = 0 no interrupt is acknowledged.
= 1 each interrupt source is individually enabled or disabled
ET2 = 0/1 Disables or Enables Timer 2 overflow Int
ES = 0/1 Serial port Int is disabled/enabled ET1=0/1 Timer 1 overflow Int is
disabled/enabled. EX1=0/1 External Int 1(INT1) is disabled/enabled ETO=0/1
Disables Timer 0 overflow Int is disabled /enabledEXO=o/1 Disables/Enables
external Int(INT0)
INSTRUCTION SET ARCHITECTURE
An instruction set is the interface between a computer's software and its hardware,
and thereby enables the independent development of these two computing realms
Data Transfer Instructions
The Data Transfer Instructions are associated with transfer with data between
registers or external program memory or external data memory.
Arithmetic Instructions
Using Arithmetic Instructions, you can perform addition, subtraction,
multiplication and division. The arithmetic instructions also include increment by
one, decrement by one and a special instruction called Decimal Adjust
Accumulator.
Logical Instructions
The next group of instructions are the Logical Instructions, which perform
logical operations like AND, OR, XOR, NOT, Rotate, Clear and Swap. Logical
Instruction are performed on Bytes of data on a bit-by-bit basis.
Boolean or Bit Manipulation Instructions
As the name suggests, Boolean or Bit Manipulation Instructions will deal with
bit variables. We know that there is a special bit-addressable area in the RAM
and some of the Special Function Registers (SFRs) are also bit addressable.
Program Branching Instructions
The last group of instructions in the 8051 Microcontroller Instruction Set are the
Program Branching Instructions. These instructions control the flow of program
logic.