Lab # 9

Design and Implementation of BCD to 7-Segment

Decoder on FPGA

Objective
In this lab, we design and implement BCD to 7-segment decoder. Moreover, we learn how to use
the 7-segment display of Nexys2 FPGA board.

IN-LAB TASK 1:

Test the functionality Of a BCD to 7-Segment decoder IC (CD4511)

with common cathode 7-Segment display

On Proteus:
Post-lab Tasks

Verilog for BCD to 7 segment-decoder and its Test Bench:

 Conclusion:

we had two tasks that we had to perform. In task 1 we used common cathode to test the
functionality of BCD to 7- Segment decoder by simulating the circuit on Proteus. We also
observed the behavior of BCD to 7-Segment decoder on 7-Segment by choosing different
BCD values. In second task we write the BCD to 7 segment code on online compiler and
verify its values and we also wrote test bench. Then we gave different input combinations to
get the desired output.

Lab # 10

Design and implementation of a sequence detector using

Mealy/Moore Machine
Equations
Reduced from K-Maps:

Equation from A1:

~ABC+A~B

Equation from B1:

~A~BC+A~B~C+ABC

Equation from Y:
AB~C

In-lab+Post-lab
Moore FSM for Sequence Detection:
module mooredec(sequence_in,clock,reset,detector_out);
input clock;

input reset;

input sequence_in;

output reg detector_out;

parameter Zero=3'b000,

One=3'b001,

OneZero=3'b011,

OneZeroOne=3'b010,

OneZeroOneOne=3'b110;

reg [2:0] current_state, next_state;

always @(posedge clock, posedge reset)

begin

if(reset==1)

current_state <= Zero;

else

current_state <= next_state;

end

always @(current_state,sequence_in)

begin

case(current_state)

Zero:begin

if(sequence_in==1)
next_state = One;

else

next_state = Zero;

end

One:begin

if(sequence_in==0)

next_state = OneZero;

else

next_state = One;

end

OneZero:begin

if(sequence_in==0)

next_state = Zero;

else

next_state = OneZeroOne;

end

OneZeroOne:begin

if(sequence_in==0)

next_state = OneZero;

else

next_state = OneZeroOneOne;

end

OneZeroOneOne:begin

if(sequence_in==0)

next_state = OneZero;
 else

next_state = One;

end

default:next_state = Zero;

endcase

end

always @(current_state)

begin

case(current_state)

Zero: detector_out = 0;

One: detector_out = 0;

OneZero: detector_out = 0;

OneZeroOne: detector_out = 0;

OneZeroOneOne: detector_out = 1;

default: detector_out = 0;

endcase

end

endmodule

Test Bench File:

// Initialize Inputs

clock = 0;

forever #5 clock = ~clock;

end

initial begin

sequence_in = 0;

reset = 1;

// Wait 100 ns for global reset to finish

#30;

reset = 0;

#40;

sequence_in = 1;

#10;

sequence_in = 0;

#10;

sequence_in = 1;

#20;

sequence_in = 0;

#20;

sequence_in = 1;

#20;
 sequence_in = 0;

// Add stimulus here

end

endmodule

Conclusion:

In this lab, we knew about Mealy and Moore model. But we used Moore machine model in
this report. In lab task we converted decimal number (22) into binary number. We also
construct a code in Moore machine Model to detect a sequence. We also attached the output
and test bench file of the code.