This full text paper was peer-reviewed at the direction of IEEE Instrumentation and Measurement Society prior to the

acceptance and publication.

The Implementation of IEEE 1588 Clock

Synchronization Protocol Based on FPGA

Hongtao Yin, Ping Fu*, Jiaqing Qiao, Yuping Li

Automatic test and control institute
Harbin Institute of Technology
Harbin, China
fuping@hit.edu.cn

Abstract—IEEE 1588 defines a precision time protocol, which mechanism, PTP is more appropriate for precise measurement
is widely used in distributed test and measurement systems. It is and control in a local area network (LAN) [10-11]. PTP provides
very important to capture the timestamps of the location that can a mean by slave clocks, which can estimate their offset from
affect the synchronization accuracy seriously in the master clock to ensure every node in the distributed system,
synchronization process. In this paper, we proposed a method to achieve the precise synchronization [12]. PTP implementations
capture the timestamps based on specialized hardware Field typically have a clock servo which uses a series of time offset
Programmable Gate Array (FPGA) between the physical layer estimates coordinate the local slave clock with the reference
and MAC layer. We designed IEEE 1588 message detection master clock [13]. Precise time coordination with PTP relies on
module and frequency compensation clock to detect IEEE 1588
precise estimates of the send and receive times (time stamps) of
message and record the timestamps, respectively. This method
can eliminate the delay jitter which is caused by the network
messages exchanged between the master and slaves.
protocol stack to improve the synchronization accuracy. The test There is an open resource software Precision Time Protocol
experiments results show that 97.76% of the synchronization daemon (PTPd), which is a pure software implementation of
deviation is located within ±40nS. PTP [14] and can only achieve the precision of the time
coordination between networked test and measurement systems
Keywords—IEEE 1588; FPGA; Synchronization on the order of microseconds [15]. It can capture the timestamps
in the application layers of the network protocol stack, which
I. INTRODUCTION introduces large degrees of non-determinism in the time stamp
The capacity of many control applications in distributed latencies, known as jitter [16]. In order to achieve high precision
systems has been greatly enhanced such as measurement and time stamps, it should draw the support of specialized hardware
control system, network communication systems, certain interfaces in the physical layer of the network. Figure.1
telecommunication systems, and et al[1-2]. High-speed data illustrates the various places in a network communication
transmission between network nodes could not achieve high protocol where time stamping can occur. The synchronization
performance in measurement and control systems without the precision is affected by the location of time stamps
accuracy and precision of time synchronization because the significantly.
network has the character of uncertainty and lack of real time.
The system needs a unified reference time to coordinate with
other subsystems.
The network time synchronization technology, Network
Time Protocol (NTP) was proposed to solve the problem of
lack real time in the network. The moderate achievable
accuracy of NTP is the range of millisecond which is not
sufficient for measurement and control systems[3]. It needs
synchronized clocks for distributed and correlated data
collection[4-5]. Synchronized clocks are used to coordinate
medium access in real-time networks or highly dynamic
applications such as time trigger control in measurement and
control systems[6-8]. Accuracies in the millisecond or even
microsecond range are often desired and node number would
be hundreds. To meet these constraints, the Precision Time
Protocol (PTP) was designed.
PTP, formerly IEEE 1588, is normally preferred in Fig. 1. Possible locations and relevant implementations for time stamping in
Ethernet-based local networks, mainly for measurement and a network-communication protocol.
control networks[9]. Compared with NTP synchronization

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 The rest of this paper is organized as follows. Section II is a
brief introduction of the principle of IEEE 1588 (PTP). Section
III provides an overview of the PTP implementation with the
support of specialized hardware FPGA. Section IV describes
the logic design in FPGA. The software design in the
implementation is described in Section V. Section VI presents
test experiments results, followed by the conclusion in section
VII.
II. IEEE 1588 CLOCK SYNCHRONIZATION PRINCIPLE
The time synchronization is defined in IEEE 1588V2. IEEE
1588 follows a master-slave model and determines the only
one master clock, which owns the best stability, accuracy, and
can stand for the standard time source in the system, through
the best master clock algorithm. IEEE 1588 synchronizes clock
nodes in the networked system by broadcasting 4 basic PTP
messages, which are Sync message, Delay_Req message,
Follow_Up message and Delay_Resp message, based on user
datagram protocol (UDP). The slave clock calculates offset
from master clock and one_way_delay between master clock
and slave clock with receipt and transmission timestamps of
those PTP messages.
Fig. 2. Principle of Time Synchronization.
Figure 2 illustrates the method of time synchronization, Tm
stands for the master clock time and Ts stands for the slave
clock time. Master clock sends Sync message at each
synchronization cycle (typically 2S) and records the Sync
message transmission time Tm1. Slave clock records the
accepted time Ts1 when received Sync message. Then master
clock sends Tm1 in the Follow_Up messages to the slave clock.
Slave clock can calculate the delay from master clock to slave
clock (master_to_slave_delay ) according to Tm1 and Ts1.
master_to_slave_delay =Tm1 -Ts1
We suppose that the time deviation between master clock
and slave clock is Offset1 when slave clock received Sync
message, then:
Ts1 = Tm1 + Offset1 + master_to_slave_delay
In order to calculate the amount of delay from the slave
clock to master clock, slave clock needs to send Delay_Req
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message to master clock and record the sent time Ts2. Master
clock will record the received time Tm2 when received the
Delay_Req message. Then master clock sends Tm2 in the
Delay_Resp messages to the slave clock. Slave clock can
calculate the delay from slave clock to master clock
(slave_to_master_delay ) based on Tm2 and Ts2, namely:
slave_to_master_delay =Ts 2 -Tm 2 (3)
Assume that when master clock received Delay_Req
message, the time deviation between master clock and slave
clock is Offset2, then:
Tm 2 = Ts 2 − Offset2 + slave_to_master_delay (4)
Based on the hypothesis that networks delays and offset
between master clock and slave clock are symmetric, namely:
slave _ to _ master _ delay = master _ to _ slave _ delay
(5)
= one_way_delay
Offset1 = Offset2 = Offset (6)
Then according to equation(1)-(6), we can draw:
one_way_delay =
(Ts1
− Tm1 ) + (Tm 2 − Ts 2 )
(7)
2
Offset = (Ts1 − Tm1 ) − one_way_delay (8)
Then the slave clock can be synchronized to the master
clock with the offset.
A. Maintaining the Integrity of the Specifications
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III. FPGA-BASED PROTOCOL IMPLEMENTATION
In Section II, the synchronization algorithm is proposed
based on two assumptions, Offset1 is equal to Offset2 and
master_to_salve_delay is equal to slave_to_master_delay. In
fact, Offset1 and Offset2 are not equal which is caused by the
instability of crystal. In this paper, the effect brought by the
instability of crystal has been reduced by the frequency
(1) compensation clock module. The master_to_salve_delay is not
equal to slave_to_master_delay because the asymmetry of the
network transmission delays which includes delay jitter in the
protocol stack and in the network component.
Message transmission delay includes the delay in physical
(2) layer and communication stack. The delay in the physical layer
without storage transponder is generally stable but the delay in
the communication stack is not stable. If the location where the
timestamp is captured is closer to the physical layer, the
synchronization accuracy will be higher. In this paper, we
captured the timestamp between MAC layer and physical layer
with the help of FPGA. So the message transmission delay is
only caused by the physical network transmission, and it can
achieve sub-microsecond synchronization accuracy.
In our hardware design, an ARM processor is used as the
processing core and a FPGA is used to capture timestamps and
detect PTP messages, the hardware part would complete a
frequency adjustable real time clock, detect PTP messages,
record or insert timestamps. The software part runs on the
ARM platform equipped with Linux operation system to
manage the process of synchronization, calculate the offset and
adjust the hardware clock in FPGA, etc.

ARM
MAC Layer

Fig. 4. Overall structure of the FPGA module.

FPGA The receive/send message detection module can detect all

Message Detection the messages transmitted through the MII interface. When the
Module messages module detect the PTP messages, receive message
module detection module produces Rrdtime signal to read
received time in the clock module. Then the PTP messages and
received timestamps are stored in the message register FIFO.
Oscillato Receive message module generates receive message interrupt
Clock Module signal R0. Send message detection module produces a Trdtime
r
signal to read sent time in the clock module. Then the PTP
messages and sent timestamps are stored in the message
register FIFO. Send message module generates send message
Physical layer interrupt signal R1. When interrupt module detects signal R0 or
R1, it will generate an interrupt signal IRQ to inform ARM to
Fig. 3. Overall structure of the FPGA-based PTP implementation. read the messages and timestamps.

The structure of our model is shown in Figure 3. FPGA is
connected to the independent media Interface (MII) which is
between the Ethernet physical layer (PHY) and MAC layer it
can detect every message passing through the MII interface.
There are two modules in FPGA which are Message Detection
Module and Clock Module. When the message detection
module detects the PTP messages, FPGA will record the
received or sent time as the timestamps and store the PTP
messages in First Input First Output register (FIFO). Then
FPGA generates an interrupt signal to inform ARM to fetch the
timestamps. After gets the timestamps, the ARM calculates the
offset and FreqCompValue using the timestamps and then
sends them to FPGA to adjust the hardware clock. ARM and
FPGA realize data communication through the external bus
interface (EBI).
IV. THE LOGIC DESIGN OF THE FPGA
The logic design is accomplished in the FPGA, it is mainly
responsible for capturing the timestamps, detecting the PTP
messages and generating a frequency adjustable real-time clock.
The overall structure of the FPGA module is shown in Figure 4:
A. Receive/send Messages Module
Receive/send messages module are designed to detect and
store the PTP messages which are transmitted on the MII.
Because the two modules are almost the same, we only
introduce the receive messages module. The detection module
realizes PTP messages detection by listening and analyzing the
received and sent messages on the MII. The detection module
detects whether the message is PTP message by comparing
only the following fields in the transmitting messages.
(1) Type: this field explains the protocol type of the
Ethernet data packet. PTP adopts UDP/IP protocol, and its field
should be IP.
(2) IP version: PTP messages use IPV4 version.
(3) Protocol: PTP messages use UDP protocol, so this
field should be UDP.
(4) Destination Port Number: PTP messages are
transmitted by event port, which port number is 319.
If it is PTP Sync message or Delay_Req message, the
receive message module generates Rrdtime signal to read the
clock time as the timestamp and stores the message and
timestamp in FIFO1. FIFO1 will be cleared if an error occurred

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during the message transmission, otherwise the message and
timestamp in FIFO1 will be stored in FIFO2. Then the receive
message module generates interrupt signal R0. The module
design is shown in Figure 5.
Fig. 5. Receive message module.
B. The clock module
The function of the clock module is to generate an
adjustable frequency real-time clock. The structure of the real-
time clock is shown in Figure 6.
Fig. 6. Receive message module.
It is often to use a counter register to implement a clock,
which is driven by active crystal oscillator or passive crystal
oscillator. The character of these oscillators is low accuracy,
easy to be effected by the environment, low long-term stability,
and the frequency is not adjustable. As time passing and
ambient temperature changing, the frequency of the crystal will
changes, called crystal’s time drift and temperature drift. With
the help of frequency compensation technique, the crystal
frequency can get dynamic compensation, thus the frequency
can be kept in a stable value. The relatively poor performance
crystal can also be successfully used in high-precision clock
synchronization system.
The frequency compensation clock is composed of a clock
counter, an accumulator, and an addend register. The function
of accumulator is to divide frequency. The addend register is to
save the frequency compensation value FreqCompValue which
id got from ARM. These three parts are driven directly by
crystal which frequency is FreqOsc. During each oscillator
cycle, the value in the accumulator adds FreqCompVlue which
is stored in the addend register, and the result is written back to
the accumulator. If the add action causes overflow, the clock
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counter value adds an increment in the next oscillator cycle,
otherwise, the clock counter value keeps unchanged. The
number of the clock counter value increases in unit time is the
count frequency FreqCnt which is decided by FreqCompValue
and FreqOsc.
FreqOsc (9)
FreqDivRatio =
FreqCnt
2q (10)
FreqCompValue =
FreqDivRatio
Through formula (9) and (10), we can observe that when
the actual frequency changes, we must adjust FreqDivRation
by adjusting FreqCompValue to keep the FreqCnt unchanged.
V. SOFTWARE DESIGN
The software runs based on the UDP/IP protocol. We
download the software to ARM platform which is implemented
in Linux application programs. The software is designed
according to IEEE 1588 and runs the protocol engine while the
system is powered on, which will always be running unless a
system error occurs. The function definition and interface of
every unit is shown in figure 7.
Fig. 7. The overall structure of the software.
The software overall includes two parts, the application
program and kernel program. The application program and
kernel program communicate during the three modules. The
interface between the kernel and FPGA is the FPGA driver
module. So the protocol engine can access FPGA through Net
Layer module, Clock Servo module and FGPA Driver module.
In the main flow chart, as shown in Figure 8, we will
introduce the function of every module definitely.
 Fig. 9. Main flowchart of software implementation.

In the process of the IEEE 1588 implementation, the

location where the timestamps are captured is critical. The
closer the location distances from the bottom of the protocol
stack, the smaller the impact of the protocol stack on the
synchronization accuracy is. In order to avoid the effect
brought by the network, the master clock and slave clock are
connected by a crossover cable directly. In this test platform,
we take two methods respectively to implement IEEE 1588.
One method is the FPGA-based implementation designed in
this paper. In this method the timestamps are captured between
the physical layer and the MAC layer. The other method is the
pure software implementation and the timestamps are captured
Fig. 8. Main flowchart of software implementation.
in the application layer. The test results are shown in Figure 10.
The clock will be initialized first to give the variable
original value when the protocol engine runs. Then the clock
goes to listening state. If it does not receive synchronization
message in the certain time when it is in the listening state, it
will state as master clock. If it receives the synchronization
message, it will do BMC algorithm using the received message
to define the clock state. The format of the message is defined
in Msg Packer module. When the clock is in master state, it
sends synchronization message. If the clock is in slave state, it
receives the synchronization message from the master clock.
When FPGA detects the PTP messages, the Time Stamp
module will record the timestamps in the 1588 Clock module.
Then FPGA generate an interrupt signal to inform the software
part to fetch the timestamp. Net Layer module would send,
receive messages, and read the timestamp. Then the Clock
Servo module calculates the offset from the salve clock to the Fig. 10. The effect of protocol stack.
master clock to implement time synchronization using the
timestamps. According to the timestamps, the Clock Servo In Figure 10, we can observe that the accuracy of the
module calculates and writes it to 1588 Clock module in FPGA software-based implementation is on the order of microsecond,
to adjust the clock frequency. but in the FPGA-based implementation, 97.76% of the errors
stand within ±40nS. When we adopt the software-based
VI. TEST RESULTS implementation, the time stamp is captured in the top of the
stack. In the CPU, one interrupt signal may take the CPU
IEEE 1588 implements clock synchronization by
several microseconds to process it and one task scheduler may
transmitting packets with network. Not only the clock itself,
deprive the process of the packet encapsulation or analysis.
but also any part related to the packets transmitting in the
Thus, the uncertainty of the time spent in the packet
network can be a factor that affects the synchronization
encapsulation and resolution process in the protocol stack is
accuracy. So there are many factors affecting the
very strong. In the FPGA-based implementation, the timestamp
synchronization accuracy, such as the delay produced by
is captured between the MAC and the physical layer. The
protocol stack, the stability of the crystal, the delay in the
propagation velocity of the electrical signal in the twisted pair
switch, and the state of the network, etc. In this paper, we
cable is about 2x108m/S, the signal propagation delay is about
mainly analyze the factor of the delay produced by protocol
5nS/m. In the case where the propagation distance is 5m, the
stack.
signal propagation delay is approximately 25nS. Assuming that
In order to analyze the factor how to affect the the uncertainty of the signal propagation velocity is 1%, the
synchronization result, we build the experiment environment, uncertainty of the signal propagation delay is 0.25nS. Thus, as
as shown in Figure 9. we can see from the figure, the precision of FPGA-based
implementation is higher than the software-based
implementation.

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 VII. CONCLUSION
In this paper, we design an IEEE 1588 standard
synchronization structure based on FPGA. The timestamps can
be captured between the physical layer and MAC layer. It can
eliminate the delay jitter which is caused by the network
protocol stack to improve the synchronization accuracy. The
deviation of the IEEE 1588 clock synchronization can be
limited into ±40nS with a rate of 97.76%, when the master
clock and slave clock are connected by a crossover cable
directly.
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