Proceedings of the International Conference on Intelligent Computing and Control Systems (ICICCS 2020)

IEEE Xplore Part Number:CFP20K74-ART; ISBN: 978-1-7281-4876-2

Test Logic Insertion for Optimization of Testing

Parameters on Lower Technology Node
Jhanvi Ravi Sheth Bhavesh Soni
MTech EC VLSI, Ganpat University Assistant Professor, Ganpat University
Ganpat University, Ganpat Vidhyanagar, Mehsana-Go zaria Ganpat Universiy, Ganpat Vidhyanagar, Mehsana-Gozaria
Highway,Kherva Highway,Kherva
Mehsana-384012, India Mehsana-384012, India
Jaahanviseth24@gmail.com bhavesh.soni@ganpatuniversity.ac.in

Rahul Mehta
Technical Associate-Physical Design, e-infochips Training & Research Academy
E-infochips,4, Aryan Park Complex, near Shilaj Railway Crossing, Thaltej
Ahmedabad, India rahul.mehta@eitra.org

Abstract: The complexi ty and g ate counts on chi ps is
growing rapi dl y on networking applicati on chi ps, because
of s maller lithographic nodes. Design for testability (DFT)
ensures no manufacturing defect on the VLS I fabricated
chips. Structured DFT approaches like scan methodol ogy,
BIST, MB IST ensure quality. Nowadays, DFT itself face
critical challenge due to node scaling and i t affects the
density of the fabricated chi p. In this paper, to opti mize
the parameters on the 28nm technol ogy node , like test
time, test cover age, power dissipation, the area shoul d be
analysed. This is the major concern of DFT for ASIC chi p
designing process.
Keywords : Scan insertion, ATPG, Design rule violations,
Design for testability for the lower lithographic node, 28nm
technology node
performance of the chip is getting better than earlier. The
number of transistors is increased the number of storage
elements in a particular design is getting increased. The test
time and the cost of test time will also be high.[3]. And this is
the biggest concern of DFT field for ASIC ch ip designing
process. There are such test parameters like test time, test
coverage, power dissipation, the area should be analyzed
must.
II. PROBLEM DEFINITION
At lower lithographic node the density of transistor is
very denser on the chi, and hence defect density will also be
higher. The following test parameters should be considered as
a higher priority. In this thesis, an industrial networking block
on 28nm technology to optimize the following parameters:

I. INTRODUCTION 1. Test time: In today’s era deformity thickness has quickly

In today’s era, the need for hand-held as well as wearable
devices for communicat ion, media entertain ment, storage
devices is increasing swift ly. These devices must have high
performance to be headed for lower technology nodes in ASIC
industries. As technology shrinks the number of transistors
and gates are increased as per Moore’s law [9] and to test the
device DFT do main of ASIC field is there. To provide a
quality device to customers DFT field came into the picture.
Earlier on higher technology nodes, the performance of the
fabricated chip was not good, in terms of area, power
dissipation and speed. To achieve better performance ASIC
industries are scaling the technology node and coming to
lower technology node. On 28n m lower lithographic node, the
main advantage is speed, area, power performance. Speed of
the manufactured chip is getting increased, and the
expanded on a lower node. To focus on the issues from
the plan in the slightest measure of time makes errand
basic for DFT people. Time is taken by the tester to test
the chip if it has defects or not.[4]
2. Test coverage: It is the only proportion of recognized
shortcomings to the nu mber of d iscernible b lames in the
chip. Industry people mostly focus on this test parameter
the most.[8]
3. Pattern Count: It additionally in fluences the test time
parameter.[4] It can be increased to focus the blames in
the structure of the design. It should be less constrained
on the external tester.
4. Area: DFT engineers involves extra rat ionale DFT logic
to test the chip. So the area will be more co mpared to the
original area of the chip but it should not be more than
5% of the real territory.[9]

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 Proceedings of the International Conference on Intelligent Computing and Control Systems (ICICCS 2020)
IEEE Xplore Part Number:CFP20K74-ART; ISBN: 978-1-7281-4876-2

form cells information

III. IMPLEMENTATION. 4 Design netlist .v form Verilog netlist
provided by
A. Block & EDA Tools : verification
engineer
TABLE I : EDA TOOLS BY VARIOUS FOUNDRIES 5 Sequential cells 7819 No. of sequential
Foundry Scan ATPG Pattern elements
Simulation
Synopsys DFT Tetramax VCS
B. Scan Insertion :
compiler
Cadence Modus Modus SimVis ion Scan insertion is all about to convert sequential cells of
Debug the original design into scan cells by adding extra mult iplexers
Mentor Tessent TestKompress ModelSim into the design to test the design. Multiplexer will distinguish
Graphics Scan between data or test input. This process can make each node
of the design more controllable and observable. All the scan
cells will be stitched together and forms a scan chain. Scan
Fig 1 used an industrial networking block on 28n m technology insertion can be done by following scan cells :
node and has basically no. of modules main module named
design_1 and it has 4 submodules instruction decoder, main
1. Muxed-D scan cell,
core and two for scan-compressor. Table I shows that which 2. Clocked cell,
are the EDA tools used for scan insertion, ATPG pattern 3. LSSD cell. [9]
generation and pattern validation respectively. Table II shows
the information of the block containing various parameters of
the design.

Fig. 1. Schematic of Industrial Design

TABLE II : BLOCK DATABASE
Sr. no Specification Data Information
value
1 Clock 1 GHz Operating
frequency frequency of the
design Fig. 2. (a) Scan insertion, (b) Output waveforms
2 Technology 28 nm Technology node
3 Library File .db Contains Standard

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 Proceedings of the International Conference on Intelligent Computing and Control Systems (ICICCS 2020)
IEEE Xplore Part Number:CFP20K74-ART; ISBN: 978-1-7281-4876-2
Here, in fig.2 (a) there are two scan cells and both
have data and test inputs DI & SI respectively. SE is the
control line it will select the particular input and will be
reflected at the output of that scan cell. The clock is there to
power on the cells and there are two primary inputs A and
B.[9] Scan input and scan outputs are the test input and test
output of the design. Fig.2 (b) shows the logical behavior of
the circuit.
Fig. 3. Block Diagram of Design
C. Scan Insertion Flow in DFTMAX Compiler :
Fig. 4. DFTMAX Flow for Scan Insertion
As per DFTMAX flo w in fig.4 [1] scan insertion is
done for our design and it first requires synthesized netlist of
the design then pre scan process like scan configurations like
which type of scan cell used. Mu xed- D for more convenience
and define various dft signals and port creation. Then created
test environment and checked design rule check for violations
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then dft logic can be add in our orig inal design and then it
goes for post scan processes and finally .spf file and scan
inserted netlist can be created for ATPG tool.
A various technique called test point insertion,
Single-pass scan synthesis and compression logic is used to
get a better result for scan insertion in the original design. For
test point insertion (fig.8) created numerous control points and
observe points into design and enabled test mode and for
compression used set_scan_compression_configuration -
chain_count 96 co mmand and enabled scan compression
mode and generated 96 internal scan chains and 8 main scan
chains as shown in (fig.5). Single pass scan synthesis is done
during logic synthesis of the design and this is widely used for
lowering down the test application time and for this used
compile –scan command.
Fig. 5. Scan Inserted Design for 8 Chains (compression)
Fig. 6. Scan path report
After creat ing test protocol DRC is checked and if it is
present or not, practically can ignore D8, D14 v iolations [1]
occurring during scan insertion but in our design and have
faced one important violation which can prevent insertion of
426
 Proceedings of the International Conference on Intelligent Computing and Control Systems (ICICCS 2020)
IEEE Xplore Part Number:CFP20K74-ART; ISBN: 978-1-7281-4876-2

scan logic named clock input is not controllable(D1) as fig.7

but picked each clocks used in our design and defined as scan
clock and it got removed by using set_dft_signal -view exist -
type ScanClock -t iming [list 45 55] -port (pin ) command.
Fig.8 shows informat ion of scan input, output & enable pin for
each scan chain created in design.

Fig. 9. Tetramax ATPG Flow [2]

First of all, set up lib raries like Verilog models of the design
then can go for reading scan inserted netlist(.v) then should go
And
for build model it will map our design with given cell libraries
then it will ask for checking DRC process at that time .spf file
is must. .spf file is STIL procedure file it has all information
of scan cells and chains.[2] Then finally can go for run atpg
process it will start generating test vectors and test bench can
be written out.
Fig. 7. Pre-DFT Violation (D1)
E. Pattern Simulation :

Pattern simulation is the process of validating the test patterns.

It can be done on any Verilog/ VHDL simu lator like Synopsys
VCS[10]. Here have performed zero delay simulat ion of
Fig. 8. Test Point Insertion patterns and if in case any mismatches occur it will throw an
error at specific failing test cycle and type of mis match as
D. Pattern Generation : well.

ATPG expands automatic test pattern generation for the IV. TECHNIQUES USED TO OPTIMIZE TEST
external tester. It helps to differentiate between correct and PARAMETERS
faulty behavior of chip for Automatic test equipment. It builds
patterns according to our design and generates faults model A. Single-Pass Synthesis :
for fau lts which can be occurred during the manufacturing
process.[7] ATPG tool generates a pattern which can able to After fixing all v iolations during the RTL test DRC process, it
detect more than one faults present in the chip. In our design, is ready to perform one-pass scan synthesis or single-pass scan
Synopsys tetramax tool is used for the generation of test synthesis, which perfo rms a test-ready comp ilat ion of the
patterns. Following in fig.9 is the flow wh ich followed for design. If DC co mp iler is used by specifying compile –scan
pattern generation. command one can perform this operation.

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 Proceedings of the International Conference on Intelligent Computing and Control Systems (ICICCS 2020)
IEEE Xplore Part Number:CFP20K74-ART; ISBN: 978-1-7281-4876-2

Test point insertion (TPI) is a co mmon ly used ad hoc DFT

technique for improving the controllability and observability
of internal nodes.[9] Testability analysis is typically used to
identify the internal nodes where test points should be
inserted, in the form of control or observation points.

Fig. 10. Test-ready Compilation Flow Fig. 12. Example for User defined test point insertion

With this compilation process, the Synopsys tools converge on
true one-pass scan synthesis. Fig. 10 shows to perform one-
pass scan synthesis flow in Synopsys DC co mpiler tool [1].
This process offers a better quality of results compared with
past methods and also this flow is simpler.
B. Compression Logic :
In the fig.12[1] can see that cloud it is combined of some
control signals and fed to the DI input of an analog block and
DO output is passes through an output drive buffer. But this
analog block is untestable and the DI and DO pin can not be
controlled and observed so to imp rove the testability of this
analog block and can define test points to it manually. Using
set_test_point_element –type observe (analog block), can
insert an observe test point at the DI input, using
set_test_element –type force_0 (pin), can hold the block at the
RSTN pin of analog block. Using set_test_element –type
force_1 (pin ) can provide controllability of downstream logic.
By using this logic, got increased test coverage for our
industrial design.

V. RESULT & DISCUSSION

A. Scan insertion Reports :

TABLE III : SCAN CHAIN INSERTION STATISTICS

Fig. 11. Scan Compression Mode
Block : Design_1
As fig.11[1] there are scan-ins and scan-outs and defined test Total cells 24777
Pre-Scan
mode. There are one 3:8 decomp ressor and 8:3 co mpressor,
Violation Reported D1,D14
mu ltip le no. of internal scan chains in the shadowed block. To
define test mode, can use set_dft_signal command[1]. To
Area 84343.632054
define no. of internal scan chains can use
set_scan_compression_configuration -chain_count command. Total cells 24979
Post-Scan
By using compression logic test data volume or pattern count Violation Reported C17,C26
can be decreased and can easily debug/diagnose.
Area 84925.920063
C. Test Point Insertion :

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 Proceedings of the International Conference on Intelligent Computing and Control Systems (ICICCS 2020)
IEEE Xplore Part Number:CFP20K74-ART; ISBN: 978-1-7281-4876-2

Block : Design_1 one is slow to rise and slow to fall wh ich can lead to
No. of Scan inputs & outputs 678 manufacturing defects like resistive vias, bridges, crosstalk,
M ax. chain length 1307
etc.

VI. CONCLUSION & FUTURE SCOPE

Here in Table III notable parameters are noticed of scan chain
insertion and it is visible that after adding scan logic number In this paper, a brief idea is demonstrated and practical work
of cells are getting increased so the area and power are also of how DFT (Design for testability) flo w can be implemented
increasing which is a critical issue for ASIC field. on 28n m technology node which includes how to scan
insertion and pattern generation can be done for a particular
B. ATPG Reports : design. Also, it includes various challenging parameters wh ich
ASIC industries are facing nowadays. The test point insertion
TABLE IV: STUCK-AT FAULT REPORT STATISTICS and ECO logic are used to get an optimized data value of test
parameters. In future, one can work on the same technique by
Itr. Test CPU Pattern Method used Fault changing the no. of the compressed chain so test time and
coverage time count type pattern count can be imp roved. Also, the same analysis can be
(s)
done for transition faults too.

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1 90.07% 0.22 377 ECO Stuck-
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(96 internal at
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[7] V. R. Devanathan, C. P. Ravikumar and V. Kamakoti, "Reducing SoC
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[8] N. Ranpura, “Implemntation Challenges for Large 28nm

Finally, in the third iteration, test point insertion logic is
used with co mp ression logic of 70 internal scan chains and
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[10] VCS® MX/VCS MXi™ User Guide, G-2012.09, September 2012
[11] DFT Compiler 1 Workshop Student Guide, 30-I-011-SSG-012,
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