EE213M

Digital Circuits

Arun Tej M.
EE213M Digital Circuits

L16: Common Functional Blocks - 3

Encoder

• Inverse operation of a decoder

• 2𝑛 (or fewer) input lines and 𝑛 output lines
• Only one of the input lines is assumed to be 1 at any given time.
• The outputs will contain the binary code of the input line that is at 1.

𝐼0 0
𝑓0 0 1
. 0
. 8-to-3 0 8-to-3
𝑓1 0
. Encoder 0 Encoder
𝑓2 1
0 1
𝐼7 0

Ex. 𝐼5 = 1 ⇒ Output will be 1 0 1

Encoder
Octal – to – Binary Encoder

𝐼7 𝐼6 𝐼5 𝐼4 𝐼3 𝐼2 𝐼1 𝐼0 𝑓2 𝑓1 𝑓0
𝐼0 0 0 0 0 0 0 0 1 0 0 0
𝑓0 0 0 0 0 0 0 1 0 0 0 1
.
8-to-3 0 0 0 0 0 1 0 0 0 1 0
. 𝑓1
Encoder 0 0 0 0 1 0 0 0 0 1 1
. 0 0 0 1 0 0 0 0 1 0 0
𝑓2 0 0 1 0 0 0 0 0 1 0 1
𝐼7 0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

𝑓0 = 𝐷1 + 𝐷3 + 𝐷5 + 𝐷7

Can be easily implemented with 3 4-i/p OR gates 𝑓1 = 𝐷2 + 𝐷3 + 𝐷6 + 𝐷7

𝑓2 = 𝐷4 + 𝐷5 + 𝐷6 + 𝐷7
What if, say, more than one of the inputs equal 1?
 Encoder
𝐼7 𝐼6 𝐼5 𝐼4 𝐼3 𝐼2 𝐼1 𝐼0 𝑓2 𝑓1 𝑓0
𝐼0 0 0 0 0 0 0 0 1 0 0 0
𝑓0 0 0 0 0 0 0 1 0 0 0 1
.
8-to-3 0 0 0 0 0 1 0 0 0 1 0
. 𝑓1
Encoder 0 0 0 0 1 0 0 0 0 1 1
. 0 0 0 1 0 0 0 0 1 0 0
𝑓2 0 0 1 0 0 0 0 0 1 0 1
𝐼7 0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

Other than these 8 input combinations, for all others there will be ambiguity.

To resolve this, priority encoders are used where each of the input lines are given certain priority.

For ex., suppose both 𝐼5 and 𝐼2 are 1, then this encoder might give higher priority to 𝐼5 and consider it.

Also, if all inputs are 0s, all outputs will also be 0s. This is conflicting with the output with only 𝐼0 = 1.
To resolve this, a separate output is provided which indicates whether or not at least one input is 1.
Priority Encoder
• A priority encoder is a combinational circuit that implements a priority function.
• Input lines are assumed to represent units that request some service.

• When two inputs 𝐼𝑖 and 𝐼𝑗 (𝑗 > 𝑖) request service simultaneously, line 𝐼𝑗 will be given higher priority.

• The outputs of the encoder give the binary code indicating which one of the input lines is given highest
priority.

𝐷0 𝐷3 𝐷2 𝐷1 𝐷0 𝐴1 𝐴0 𝑉
𝐴0 0 0
4 – to – 2 0 0 𝑋 𝑋 0
𝐷1 0 0 0 1
Priority 𝐴1 0 0 1 𝑉 = 1 if any input is 1.
𝐷2 0 0 1 𝑋 0 1 1
Encoder 0 1 𝑋 𝑉 = 0 if all inputs are 0s.
𝑋 1 0 1
𝐷3 𝑉 1 𝑋 𝑋 𝑋 1 1 1

Xs in input columns represent product terms that are not minterms.

Xs in output columns are don’t cares and not used here.
Priority Encoder

Xs in this condensed truth table are used to represent product terms that are not minterms
The number of rows of a full truth table represented by a row in the condensed table is 2𝑝 where 𝑝 is the
number of Xs in the row.
For example, 01XX represents 22 = 4 rows – 0100, 0101, 0110, and 0100, all having the same value for
outputs.

𝐷0 𝐷3 𝐷2 𝐷1 𝐷0 𝐴1 𝐴0 𝑉
𝐴0
𝐷1 4 – to – 2 0 0 0 0 𝑋 𝑋 0
Priority 𝐴1 0 0 0 1 0 0 1
𝐷2 Encoder 0 0 1 𝑋 0 1 1
0 1 𝑋 𝑋 1 0 1
𝐷3 𝑉 1 𝑋 𝑋 𝑋 1 1 1
Priority Encoder

𝐷3 𝐷2 𝐷1 𝐷0 𝐴1 𝐴0 𝑉
0 0 0 0 𝑋 𝑋 0
0 0 0 1 0 0 1
𝑉 = 𝐷0 + 𝐷1 + 𝐷2 + 𝐷3 0 0 1 𝑋 0 1 1
0 1 𝑋 𝑋 1 0 1
𝐷1 𝐷0
1 𝑋 𝑋 𝑋 1 1 1
𝐷3 𝐷2 00 01 11 10
00 𝑋 0 1 1

01 0 0 0 0

11 1 1 1 1

10 1 1 1 1

𝐴0 = 𝐷3 + 𝐷1 𝐷2′

𝐴1 = 𝐷2 + 𝐷3
Priority Encoder

𝑑 = 1 if any input is 1.
𝑑 = 0 if all inputs are 0s.
Comparator
• An 𝑛 bit comparator compares the magnitude of two numbers 𝐴 and 𝐵 and produces three outputs
𝐺𝑇, 𝐿𝑇, and 𝐸𝑄 as:
𝐺𝑇 = 1 iff 𝐴 > 𝐵
𝐿𝑇 = 1 iff 𝐴 < 𝐵
𝐸𝑄 = 1 iff 𝐴 = 𝐵
• Consider a 1-bit comparator.
𝐺𝑇 = 1 only for 𝐴 = 1, 𝐵 = 0 𝐺𝑇
𝐴
𝐿𝑇 = 1 only for 𝐴 = 0, 𝐵 = 1 Comparator 𝐿𝑇
𝐵
𝐸𝑄 = 1 for either 𝐴 = 0, 𝐵 = 0 or for 𝐴 = 1, 𝐵 = 1 𝐸𝑄

𝐺𝑇 = 𝐴. 𝐵′ 𝐿𝑇 = 𝐴. 𝐵′ 𝐸𝑄 = 𝐴′ . 𝐵′ + 𝐴. 𝐵 XNOR gate for 𝐸𝑄

Also called equivalence gate
2-bit Comparator

𝐴1 𝐴2
𝐵1 𝐵2 00 01 11 10 𝐴1 𝐴2 𝐵1 𝐵2
00 𝐸𝑄 𝐺𝑇 𝐺𝑇 𝐺𝑇

01 𝐿𝑇 𝐸𝑄 𝐺𝑇 𝐺𝑇
Comparator
11 𝐿𝑇 𝐿𝑇 𝐸𝑄 𝐿𝑇

10 𝐿𝑇 𝐿𝑇 𝐺𝑇 𝐸𝑄
𝐺𝑇 𝐿𝑇 𝐸𝑄

𝐺𝑇 = 𝐴1 𝐴2 𝐵2′ + 𝐴2 𝐵1′ 𝐵2′ + 𝐴1 𝐵1′

𝐿𝑇 = 𝐴′2 𝐵1 𝐵2 + 𝐴1′ 𝐴′2 𝐵2 + 𝐴1′ 𝐵1

𝐸𝑄 = ?
4-bit Comparator

𝐴 = 𝐴3 𝐴2 𝐴1 𝐴0 𝐵 = 𝐵3 𝐵2 𝐵1 𝐵0

Let 𝑥𝑖 = 𝐴′𝑖 . 𝐵𝑖′ + 𝐴𝑖 . 𝐵𝑖 ⇒ 𝑥𝑖 = 1 for 𝐴𝑖 = 𝐵𝑖 Else, 𝑥𝑖 = 0

𝐴 = 𝐵 when each 𝐴𝑖 = 𝐵𝑖 i.e., 𝑥𝑖 = 1

Thus, 𝐸𝑄 = 𝑥3 . 𝑥2 . 𝑥1 . 𝑥0

𝐺𝑇 = 𝐴3 . 𝐵3′ + 𝑥3 . 𝐴2 . 𝐵2′ + 𝑥3 . 𝑥2 . 𝐴1 . 𝐵1′ + 𝑥3 . 𝑥2 . 𝑥1 . 𝐴0 . 𝐵0′

𝐿𝑇 = 𝐴′3 . 𝐵3 + 𝑥3 . 𝐴′2 . 𝐵2 + 𝑥3 . 𝑥2 . 𝐴′0 . 𝐵0 + 𝑥3 . 𝑥2 . 𝑥1 . 𝐴′0 . 𝐵0

Array Multiplier

AND gate

AND gates and Half-adders

XOR for Sum

AND gate for Carry
Array Multiplier

B0A3 B0A2 B0A1 B0A0

AND gates

4-bit Binary Adders