Kahng Ansys Dacbreakfast Talk Distributed2

Machine Learning in EDA
Opportunities and Value Propositions
Andrew B. Kahng
CSE and ECE Department
UC San Diego
http://vlsicad.ucsd.edu/~abk/
abk@ucsd.edu
Andrew B. Kahng ANSYS Breakfast June 20, 2017

Machine Learning in EDA
Problem types in ML
• Classification
• Regression
• Dimensionality reduction
• Structured prediction
• Anomaly detection
ML applications in EDA literature
• Yield modeling (anomaly detection, classification)
• Lithography hotspot detection (classification)
• Identification of datapath-regularity (classification)
• Noise and process-variation modeling (regression)
• Performance modeling for analog circuits (regression)
• Design- and implementation-space exploration (regression)
Many unexplored opportunities in design- and
flow-level modeling, prediction and optimization!
Andrew B. Kahng ANSYS Breakfast June 20, 2017 2
Key Messages Today
• Many high-value opportunities for ML in EDA
• Correlation
• Design convergence
• Delivery of better design PPAC
• Reduced analysis margins, pessimism in SP&R
• Prediction
• “Lookahead”, one-pass design flows and methodologies
• Pathfinding in many forms: design-technology, SOC/SIP
architecture, die-package-board
• Optimization
• More effective use of tool, schedule resources
• Project prediction, monitoring, adaptive scheduling
• This talk: Some examples from past ~20 years
Ultimate PPAC @Node X: QOR and Time
(105, 130)
QOR (%) #1 #2
FUTURE (130, 120)
(30, 100)
#3
100 (50, 110) TODAY (130, 100)
90 (30, 90)
Design time
30 130 (weeks)
#3. Optimized back-end “Magic” synthesis, place, route, optimization; PG + Clock; Tech)
#2. Modeling, signoff criteria Reduced corners and guardbands; Targeting
#1. Bespoke, design-specific flow (+ Moore) Predictive, one-pass flow; Opt tool usage
ML (Data + Intelligence) is essential to this picture !!!

A. B. Kahng DARPA IDEA workshop 170413

Agenda
• Correlation
• SI for Free
• Learning Model-Guided Optimization of Routability
• Prediction
• Risk of Timing Failure at Floorplan Stage
• Bump Inductance in Die-Package PDN Design
• Optimization
• Design and Schedule Resources
• Conclusions

Agenda
• Correlation
• SI for Free
• Prediction
• Optimization
• Conclusions

TAU16 Keynote: “How Do We Lose Time?”
• It’s tough not to … [DATE14]
• The margining imperative …

• We give it away 0.1
• Intentionally
T2 Path Slack (ns)

0
• By miscorrelating -0.1
-0.2
-0.3
-0.4
123 ps
-0.5
-0.6
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1
T1 Path Slack (ns)

[DATE14]
Erase Miscorrelation with Machine Learning!
If
INCREMENTAL
Can also erase Outliers
(data points)
error >
threshol
miscorrelation of New
d
P&R STA vs. Designs

signoff STA !!! Train Validate
MODELS
(Path slack, setup
Test
time, stage, cell,
wire delays)
Artificial Real
Circuits Designs ONE-TIME
0.1 BEFORE AFTER

T2 Path Slack (ns)
T2 Path Slack (ns)

-0.1
-0.2
-0.3 ML 31 ps
Modeling
-0.4 123 ps ~4 reduction
-0.5
-0.6
-0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1
T1 Path Slack (ns) T1 Path Slack (ns)
[SLIP15]
Harder: Non-SI to SI Calibration
• Complex interplay of electrical,
Post P & R Database
logic structure, and layout
.db, .lib .spef .v .sdc parameters
• Black-box code in STA tools
• Slack diverges by 81ps (clock
period = 1.0ns)
• ~4 stages of logic at 28nm
Non-SI Timing FDSOI
Non-SIReport
Timing Report
($)
Non-SI Path Slack (ns)
Calibration: Recipe to Convert
Non-SI Timing Report to SI
Timing Report
81ps
SI Timing
SI Report
Timing
Report
SI Timing Report
SI Path Slack (ns) ($$$)

“SI for Free” with Machine Learning
Timing Reports in SI Timing Reports in
Mode Non-SI Mode • Machine learning of
Create Training, Validation and Testing Sets incremental transition
time, delay due to SI
ANN (2 Hidden Layers, SVM (RBF Kernel, 5-Fold
5-Fold Cross-Validation) Cross-Validation) • Accurate SI-aware
path delays, slacks
HSM (Weighted Predictions from ANN and SVM)
Save Model and Exit

Non-SI Path Slack (ns) ($)
Predicted Path Delay (ps)

BEFORE AFTER
81ps Worst absolute

error = 8.2ps
ML 8.2ps Average absolute
Modeling error = 1.7ps
SI Path Slack (ns) ($$$) Actual Path

Andrew B. Delay
Kahng ANSYS (ps)June 20,
Breakfast 2017 10
Agenda
• Correlation
• SI for Free
• Prediction
• Optimization
• Conclusions

[ISPD17]
Emerging Routability Challenges [ICCD16]
• More design rules to ensure manufacturability

• Increasing layout complexities with multi-height cells, SRAMs that
significantly complicate routability
• Slowing down of design closure flow and increasing design overheads
• E.g., lower achievable P&R utilization
[Source: SNPS Solvnet]

Misleading Congestion Maps
• Sub-14nm design: global route (GR) congestion map does
not correlate well with post-route (actual) DRC violations
• Many false positive overflows (red crosses) in GR
congestion map
• Many of them do not lead to actual DRC violations
GR Overflows Actual DRC
GR-based prediction can mislead routability optimizations!!!

Layout Study
• Initially predict with GR overflows and cell/pin density map
• Red DRC-hotspot likely be rejected due to low cell-pin density
• Larger windows and buried nets metrics to guide prediction
Standard cells
Route-DRC
False-negative
Extraction
windows
Non-buried net
Sparse pins/cells Dense pins/cells

Improved Learning-Based Predictor
• Captures all true-positive clusters
• Maintains low false-positive rate
Learning-based Prediction Actual DRC
(a) (b) (c)

Model-Guided Routability Optimization
Placed & optimized

netlist Parameter collection
(from placement and GR)
Predictor-guided
Global route
cell spreader Pre-stored DRC
predictor model
Track assignment Global route
Track assignment DRC Prediction

Detailed route
Detailed route
Base flow Test flow

Model-Guided Routability Optimization
• Testcases generated by in-tool placement perturbation
• Up to 76.8% DRC reduction
• Minor WL and timing impacts
#DRCs Wirelength TNS (ns) #FEPs
eg1 8478 1964 -76.83% 1742804 1747685 0.3% -153.43 -158.4 3.2% 7289 7352 0.86%
eg2 1502 927 -38.28% 1750698 1753047 0.1% -168.23 -163.5 -2.8% 7406 7374 -0.43%
eg3 2017 1819 -9.82% 1772889 1773701 0.0% -215.75 -213.6 -1.0% 7817 7751 -0.84%
eg4 2026 1780 -12.14% 1735185 1735227 0.0% -151.36 -149.6 -1.2% 7195 7143 -0.72%
eg5 4252 4255 0.07% 1831492 1836060 0.2% -264.34 -275.6 4.3% 7865 7975 1.40%
eg6 3440 3891 13.11% 1790059 1794184 0.2% -195.65 -203.5 4.0% 7587 7562 -0.33%
avg -20.6% avg 0.2% avg 1.1% avg -0.01%
max 13.1% max 0.3% max 4.3% max 1.40%
min -76.8% min 0.0% min -2.8% min -0.84%

Agenda
• Correlation
• SI for Free
• Prediction
• Optimization
• Conclusions

[ASPDAC16]
Closing Multiphysics Analysis Loops
Sim Results
Tech files, signoff (Dyn.) Activity Functional
Sim vectors
Sim
criteria, corners Factor (Static) Benchmark
RTL
IR Drop Power
Map Thermal
AVS Trace Analysis
Timing / Power Temp

Glitches Analysis Map
Slack
Task
Timing/ Mapping/
P&R + Noise Migration/
Reliability (DVFS)
Optimization
Report
MTTF &
Aging
[ASPDAC16]
Closing Multiphysics Analysis Loops
Sim Results
Tech files, signoff Workload-Thermal
(Dyn.) Activity Functional loopSim vectors
Sim
criteria, corners Factor (Static) Benchmark
STA-IR loop RTL
IR Drop Power
Map Thermal
AVS Trace Analysis
Timing / Power Temp

Glitches AnalysisSTA-Thermal Map
Slack
loop
Task
Timing/ Mapping/
P&R + Noise Migration/
Reliability (DVFS)
Optimization
Report
STA-Reliability loop MTTF &

Aging
Early Prediction of SRAM Timing Slack Failure
• Timing closure is time-consuming and complex at
advanced nodes significantly increases TAT
• Multiphysics effects (IR drop, thermal, etc.) affect timing
closure
• Floorplanning with SRAMs is complicated
• SRAMs create placement and routing blockages
• Makes timing unpredictable at the post-P&R stage
• Early prediction of post-P&R slack (“doomed
floorplans”) is incredibly valuable for design schedule
• Estimating post-P&R timing at the floorplan stage is
challenging due to many factors
• Wire delay estimate has no spatial embedding information
• Gate delay estimate has no buffering information
Multiphysics Analysis is Difficult to Predict
• IR drop, thermal, reliability, crosstalk, etc.
• Example: Can we predict “risk map” for embedded
memories at floorplan stage ?
SRAM Slack (ps)
29ps
25ps
SRAM #1 SRAM #5

Multiphysics Analysis is Difficult to Predict
• IR drop, thermal, reliability, crosstalk, etc.
• Example: Can we predict “risk map” for embedded
memories at floorplan stage ?
SRAM Slack (ps)
Implementation Index

Modeling Techniques and Flow
Parameters from netlist Parameters from floorplan Slack reports from

sequential graph context, constraints P&R, multiphysics STA
Ground Truth
ANN with 1 input, 2 Boosting with

LASSO with L1 SVM with RBF
hidden, 1 output SVM as weak
regularization kernel
layer learner
Combine using weights
Save model and exit

Floorplan Pathfinding Model
• False negatives = 3%
• Pessimistic predictions floorplan change that is
actually not required
• False positives = 4%
• Model incorrectly deems a floorplan to be good
Positive slack data points:

Precision: tp/(tp +fp) = 93.3% Actual
Recall: tp/(tp +fn) = 95.0%
Pass Pass Fail
Negative slack data points: Precision
Predicted
Precision: tn/(tn +fp) = 92.5% Precision

False
584 42
Recall: tn/(tn +fn) = 90.1% positives
Fail
31 384
False negatives
Recall Recall
Agenda
• Correlation
• SI for Free
• Prediction
• Optimization
• Conclusions

Die/PKG/PCB Co-Design
• Scope
• SOC floorplan, bump/ball assignment,
PKG/PCB routing, stackup optimizations, … !
• Challenges
• Cross-layer effects: die technology/stackup, Die Floorplan
standard cell and circuit design, floorplan and
physical design, system and industrial design
• Initial Target: PKG PDN Design
Automation
• PKG PDN performance largely depends on Bump Escape Routing
bump / ball assignment and PKG technology
• Quality of bump / ball assignment is assessed
by simulation after implementation
• Iterations of bump / ball re-assignment and
PKG PDN design
• Number of iterations can be reduced if PKG
PDN performance can be predicted before
implementation PKG/PCB PDN
27 A. B. Kahng DARPA IDEA workshop 170413 27
Andrew B. Kahng ANSYS Breakfast June 20, 2017
Learning-Based Bump Inductance Prediction
Problem: Given bump / ball assignment and PKG technology
parameters, predict the performance (in terms of inductance of
bumps) of PKG PDN without actual implementation
• Problem complexity
• Raw bump information data is comprehensive but very high-
dimensional
• Implies difficult (#neurons) ANN modeling task
• Key features can be selected using ML model selection techniques
• Identification of key features
• Routing congestion (e.g., based on number of rails in region)
• Length of return path (e.g., based on distance from VDD bump
VDD ball VSS ball VSS bump VDD bump)
• …
• Feature selection
• Backward elimination (standard for choosing subset of features while
considering possible interactions between features)
Initial Results
• Initial ANN modeling
• R-Squared = 0.93 for validation dataset in log scale
• [-40%, 40%] error bound for validation dataset

Agenda
• Correlation
• SI for Free
• CTS ECO Route Prediction and Optimization
• Prediction
• (3D Power Estimation from Golden 2D Implementation)
• Optimization
• Conclusions

[DAC15 WIP]
Pure Optimization is a Big Lever [ACM TODAES17]
• Project planning and management

• Unforeseen events (late RTL bugs, timing ECO)
• Resource co-constraints (e.g., 2 cores per EDA license, 3 concurrent
tapeouts)
A2 A5 A3
(3) (1) (3) Datacenter capacity
A2 A4 A5
Usage (Across Three
(1) (3) (1) Current servers

A4 A4 A4 A5
(1) (2) (1) (2)
A4 A3 A3 A3 A4 A5
(1) (1) (1) (2) (2) (2)
A3 A2 A3 A2 A3 A4 A4
Projects)
(1) (1) (2) (2) (3) (3) (3)

A1 A1 A2 A1 A4 A3 A4 A4
(2) (2) (2) (3) (2) (2) (2) (3)
A1 A1 A2 A2 A1 A4 A2 A2 A3 A5 A5
(1) (1) (1) (2) (3) (1) (3) (3) (3) (3) (3)
20 22 24 26 28 30 32 34 36 38
40 42 Work Weeks
• “How to pack 14 tapeouts into my design center during 2H15?”

• Schedule cost minimization (SCM)
• Minimize overall project makespan subject to delay penalties, resource
bounds, resource co-constraints, etc.
• Resource cost minimization (RCM)
• Minimize number of resources required across all projects
Example Solver Use Cases (from a design center of a world top-5 semi)
• Schedule modification after late-breaking bug
• Three projects, 11 activities/project (e.g., placement, routing, RCX, STA,
etc.)
• Five resource types (#cores, #memory, licenses for P&R, RCX, STA,
tools)
• Industry solution: Makespan of 41 days across all projects
• SCM solution: Makespan of 34 days across all projects (1.4 weeks
saved)
• Datacenter resource allocation
• 24 projects, five activities (synthesis, P&R, RCX, STA, PV) per project
• Forecast-based allocation for #servers in datacenter
• Industry solution: Purchase 600 additional servers
• SCM solution: Zero additional servers
• Human resource allocation
• Four large projects
• Four types of human resources (synthesis, P&R, verification, STA)
• RCM solution: ~$5.2M headcount cost savings for company
• MILP solver at http://vlsicad.ucsd.edu/MILP/
• ML/prediction needs: runtime, memory, QOR, failure, +++
Another Problem: Chaos in EDA Tools, Flows
• Advanced nodes: more complexity, competition
• Power, performance, cost and schedule
• Complex designs complex EDA tools
• Intractable design optimizations more heuristics with
unpredictable behavior
• “Chaos” in outcomes results when EDA tools are
pushed to “try hard”
• Recent work: Maximize ROI from advanced

nodes when EDA tools, flows are chaotic

Chaos is Real
• Synthesis, Placement, Routing and Optimization
performed at different synthesis frequencies, two designs
• Slight frequency perturbations 11 separate runs of the
tool flow per target frequency
Post Route Area vs Synthesis Frequency for AES in 28nm Post Route Area vs Synthesis Frequency for PULPino in
FDSOI 14nm finFET
• 6% area difference with 10MHz frequency difference!

• Thesis: Exploiting chaos can lead to better design PPA
Resource-Limited IC Design = “Multi-Armed Bandit”
• Multi Armed Bandit Problem: Given a slot machine
with N arms, maximize total reward obtained using T
pulls (iterations)
• Tradeoff of “Exploration” and “Exploitation”
(reinforcement learning)
• Draw samples to learn model parameters (e.g.,
distributions of outcomes)
• Simultaneously, maximize reward
• Resource-Limited IC Design Problem:
• Each “arm” = design target, flow configuration
• Each “pull” = a run of the tool flow
• Want best outcome with limited #pulls on arms

UCSD “No Human In Loop” Tool
• Fully automated tool using Python, Perl, Tcl
• Inputs:
• Constraints – Max Area, Max Power, WNS/TNS, #Licenses,
#Days
• Max #Arms Range of possible frequencies
• Output: Max frequency which satisfies constraints, obtainable
within N tool runs in M iterations
Design Constraint Max Freq
Tool Outcomes (Area,
Power, WNS/TNS)
ARM Area = XXX GHz
CortexM0 20500 um2
Arms to (28nm Power =
Sample Parallel FDSOI) 13.25mW
SAMPLER
Samples per Tool
Constraints Runs
Arm ARM Area = XXX GHz
CortexM0 9500um2
Max (14nm Power =
Frequency finFET) 3mW
Toward GOAT Designs (With No Humans!)
• Multi-Armed Bandit assumes Gaussian dist at each frequency
• Valid sample frequency becomes new fmax
• Sampling at frequencies > fmax in proportion to probability of
returning highest reward
reward = (f – fmax ) * Pr(obtaining valid sample)
Sampling Distribution
1.2
Frequency Sampled (GHz)
0.8
0.6
0.4
0.2
0
1 3 5 7 9 11 13
Sample Index
MAB sampling applied to synthesis runs on ARM CortexM0 using XXX cells
Agenda
• Correlation
• SI for Free
• CTS ECO Route Prediction and Optimization
• Prediction
• (3D Power Estimation from Golden 2D Implementation)
• Optimization
• Conclusions

[ISQED01]
METRICS (1999): Measure to Improve
• Goal #1: Predict outcome

• Goal #2: Find sweet spot (field of use) of tool, flow
• Goal #3: Dial in design-specific tool, flow knobs
http://vlsicad.ucsd.edu/GSRC/METRICS
Conclusions and Futures (1)
• This talk: What questions are being asked, where are
low-hanging fruits, … many high-value opportunities!
• ML in EDA will deliver better design QoR
• Accurate pre-route estimation of SI effects to prevent
optimization of paths
• Accurate pre-route modeling of advanced technology rules
to prevent unexpected QoR changes at post-route
• ML in EDA will deliver faster tool, flow TAT
• Accurate estimation of signoff QoR to reduce #iterations
between design and signoff tools
• ML in EDA (or, at customers) will help optimize
resource usage and meet product schedules
• Accurate modeling of tool runtimes and flow uncertainties to
guide project, schedule, resource management
Conclusions and Futures (2)
• ML in EDA: technology challenges
• “Small data” problem alongside “big data” problem
• Huge implementation space, difficult parameter identification
• Confounding factors: tool versions, design versions,
technology changes
• Good news: EDA folks know what’s in their tools!
• ML in EDA: industry challenges
• EDA {doesn’t like to, doesn’t know how to} model itself
• Dependence on customers and customer data to understand
what is needed
• Unclear whether customers or EDA vendors will drive ML
into leading-edge design enablements, production flows
• METRICS … revisited? (measure, record, model, predict, improve)
• Huge pool of ML / data science talent at UCSD !!!
Some References
Highlighted in the talk
• [RISKMAP] W.-T. J. Chan, K. Y. Chung, A. B. Kahng, N. D. MacDonald and S. Nath, "Learning-Based Prediction of
Embedded Memory Timing Failures During Initial Floorplan Design", (.pdf), Proc. ASPDAC, 2016.
• [GT1GT2] ] S. S. Han, A. B. Kahng, S. Nath and A. Vydyanathan, "A Deep Learning Methodology to Proliferate Golden
Signoff Timing", (.pdf), Proc. DATE, 2014.
• [GT1GT2] A. B. Kahng, M. Luo and S. Nath, "SI for Free: Machine Learning of Interconnect Coupling Delay and Transition
Effects", (.pdf), Proc. SLIP, 2015.
• [#ML/ROPT] W.-T. J. Chan, Y. Du, A. B. Kahng, S. Nath and K. Samadi, "BEOL Stack-Aware Routability Prediction from
Placement Using Data Mining Techniques", (.pdf), Proc. ICCD, 2016.
• [#ML/ROPT] W.-T. J. Chan, P.-H. Ho, A. B. Kahng and P. Saxena, "Routability Optimization for Industrial Designs at Sub-
14nm Process Nodes Using Machine Learning", (.pdf), Proc. ISPD, 2017.
Other machine learning / data mining papers from ABKGroup

• [CTS] K. Han, A. B. Kahng, J. Lee, J. Li and S. Nath, "A Global-Local Optimization Framework for Simultaneous Multi-Mode
Multi-Corner Skew Variation Reduction",(.pdf), Proc. DAC, 2015.
• [3DPE] W.-T. J. Chan, Y. Du, A. B. Kahng, S. Nath and K. Samadi, "3D-IC Benefit Estimation and Implementation Guidance
from 2D-IC Implementation", (.pdf), Proc. DAC, 2015.
• [INT] A. B. Kahng, S. Kang, H. Lee, S. Nath and J. Wadhwani, "Learning-Based Approximation of Interconnect Delay and
Slew in Signoff Timing Tools", (.pdf), Proc. SLIP, 2013.
• [METRICS] S. Fenstermaker, D. George, A. B. Kahng, S. Mantik and B. Thielges, "METRICS: A System Architecture for
Design Process Optimization", (.pdf), Proc. DAC, 2000.
• [METRICS] A. B. Kahng and S. Mantik, "A System for Automatic Recording and Prediction of Design Quality
Metrics", (.pdf), Proc. ISQED, 2001.
• [HSM] A. B. Kahng, B. Lin and S. Nath, "Enhanced Metamodeling Techniques for High-Dimensional IC Design Estimation
Problems", (.pdf), Proc. Design, Automation and Test in Europe, 2013, pp. 1861-1866.
• [HHSM] A. B. Kahng, B. Lin and S. Nath, "High-Dimensional Metamodeling for Prediction of Clock Tree Synthesis
Outcomes", (.pdf), Proc. ACM/IEEE International Workshop on System-Level Interconnect Prediction, 2013.
• [METRICS] GSRC/METRICS: http://vlsicad.ucsd.edu/GSRC/metrics/
More on “Ultimate PPAC @Node X”: Center for Design-Enabled Nanofabrication, http://cden.ucsd.edu

Thank You !
abk@ucsd.edu

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Machine Learning in EDA

Opportunities and Value Propositions

Andrew B. Kahng ANSYS Breakfast June 20, 2017

ML (Data + Intelligence) is essential to this picture !!!

Andrew B. Kahng ANSYS Breakfast June 20, 2017 4

Andrew B. Kahng ANSYS Breakfast June 20, 2017 5

Andrew B. Kahng ANSYS Breakfast June 20, 2017 6

• The margining imperative …

T2 Path Slack (ns)

T1 Path Slack (ns)

Andrew B. Kahng ANSYS Breakfast June 20, 2017 7

P&R STA vs. Designs

0.1 BEFORE AFTER

T2 Path Slack (ns)

SI Path Slack (ns) ($$$)

Save Model and Exit

Predicted Path Delay (ps)

81ps Worst absolute

SI Path Slack (ns) ($$$) Actual Path

Andrew B. Kahng ANSYS Breakfast June 20, 2017 11

• More design rules to ensure manufacturability

Andrew B. Kahng ANSYS Breakfast June 20, 2017 12

GR Overflows Actual DRC

GR-based prediction can mislead routability optimizations!!!

Andrew B. Kahng ANSYS Breakfast June 20, 2017 13

Sparse pins/cells Dense pins/cells

Learning-based Prediction Actual DRC

(a) (b) (c)

Placed & optimized

Track assignment DRC Prediction

Base flow Test flow

Andrew B. Kahng ANSYS Breakfast June 20, 2017 16

#DRCs Wirelength TNS (ns) #FEPs

avg -20.6% avg 0.2% avg 1.1% avg -0.01%

max 13.1% max 0.3% max 4.3% max 1.40%

min -76.8% min 0.0% min -2.8% min -0.84%

Andrew B. Kahng ANSYS Breakfast June 20, 2017 17

Andrew B. Kahng ANSYS Breakfast June 20, 2017 18

Timing / Power Temp

Timing / Power Temp

STA-Reliability loop MTTF &

Andrew B. Kahng ANSYS Breakfast June 20, 2017 22

Andrew B. Kahng ANSYS Breakfast June 20, 2017 23

Parameters from netlist Parameters from floorplan Slack reports from

ANN with 1 input, 2 Boosting with

Combine using weights

Save model and exit

Andrew B. Kahng ANSYS Breakfast June 20, 2017 24

Positive slack data points:

Precision: tn/(tn +fp) = 92.5% Precision

Andrew B. Kahng ANSYS Breakfast June 20, 2017 26

Andrew B. Kahng ANSYS Breakfast June 20, 2017 29

Andrew B. Kahng ANSYS Breakfast June 20, 2017 30

• Project planning and management

(1) (3) (1) Current servers

(1) (1) (2) (2) (3) (3) (3)

• “How to pack 14 tapeouts into my design center during 2H15?”

• Recent work: Maximize ROI from advanced

Andrew B. Kahng ANSYS Breakfast June 20, 2017 33

• 6% area difference with 10MHz frequency difference!

Andrew B. Kahng ANSYS Breakfast June 20, 2017 35

Andrew B. Kahng ANSYS Breakfast June 20, 2017 38

• Goal #1: Predict outcome

Other machine learning / data mining papers from ABKGroup