DAY-15

Programmable Logic Devices PLD

Programmable Logic Devices PLDs are the integrated circuits. They contain an array of AND gates &
another array of OR gates. There are three kinds of PLDs based on the type of arrays, which has
programmable feature.

 Programmable Read Only Memory

 Programmable Array Logic

 Programmable Logic Array

The process of entering the information into these devices is known as programming. Basically,
users can program these devices or ICs electrically in order to implement the Boolean functions
based on the requirement. Here, the term programming refers to hardware programming but not
software programming.
Programmable Read Only Memory PROM:
Read Only Memory ROM is a memory device, which stores the binary information permanently.
That means, we can’t change that stored information by any means later. If the ROM has
programmable feature, then it is called as Programmable ROM (PROM). The user has the flexibility
to program the binary information electrically once by using PROM programmer. PROM is a
programmable logic device that has fixed AND array & Programmable OR array. The block
diagram of PROM is shown in the following figure.

Figure 15.1 Block diagram of PROM

Here, the inputs of AND gates are not of programmable type. So, we have to generate 2 n product
terms by using 2n AND gates having n inputs each. We can implement these product terms by using
nx2n decoder. So, this decoder generates ‘n’ min terms. Here, the inputs of OR gates are
programmable. That means, we can program any number of required product terms, since all the
outputs of AND gates are applied as inputs to each OR gate. Therefore, the outputs of PROM will be in
the form of sum of min terms.
To program a ROM, consider a 4 x 4 ROM, which means that it has total of 4 addresses at which
information is stored, and each of those addresses has 4-bit information, which is permanent and
must be given as the output, when we access a particular address.
The following steps need to be performed to program the ROM:
1. Construct a truth table, which would decide the content of each address of the ROM and
based upon which a particular ROM will be programmed.
So, the truth table for the specification of the 4 x 4 ROM is described as below:

This truth table shows that at location 00, content to be stored is 0011, at location 01, the
content should be 1100, and so on, such that whenever a particular address is given as
input, the content at that particular address is fetched. Since, with 2 input bits, 4 input
combinations are possible and each of this combination holds 4-bit information, so this
ROM is a 4 X 4 ROM.

2. Now, based upon the total no. of addresses in the ROM and the length of their content,
decide the decoder as well as the no. of OR gates to be used. Generally, for a 2k x n ROM, a k
x 2k decoder is used, and the total no. of OR gates is equal to the total no. of bits stored at
each location in the ROM.
So, in this case, for a 4 x 4 ROM, the decoder to be used is a 2 x 4 decoder. The truth table for a 2x4
decoder is as follows

When both the inputs are 0, and then only D is 1 and rest are 0, when input is 01, then, only D is
high and so on. Now, since we want each address to store 4 – bits in the 4 x 4 ROM, so, there will be
4 OR gates, with each of the 4 outputs of the decoder being input to each one of the 4 OR gates,
whose output will be the output of the ROM, as follows :
A cross sign in this figure shows connection between the two lines is intact. Now, since there are 4
OR gates and 4 output lines from the decoder, so there are total of 16 intersections, called as cross
point.

3. Now, program the intersection between the two lines, as per the truth table, so that the
output of the ROM (OR gates) is in accordance with the truth table. For programming the
cross points, initially all the cross points are left intact, which means that it is logically
equivalent to a closed switch, but these intact connections can be blown by the application
of a high – voltage pulse into these fuse, which will disconnect the two interconnected lines,
and in this way the output of a ROM can be manipulated.
To program a ROM, look at the truth table specifying the ROM and blow away (if required) a connection.
The connections for the 4 x 4 ROM as per the truth table is as shown below
Remember, a cross sign is used to denote that the connection is left intact and if there is no cross
this means that there is no connection.
Example: Let us implement the following Boolean functions using PROM.
A(X,Y,Z)=∑m(5,6,7)
B(X,Y,Z)=∑m(3,5,6,7)
The given two functions are in sum of min terms form and each function is having three variables X,
Y & Z. So, we require a 3 to 8 decoder and two programmable OR gates for producing these two
functions. The corresponding PROM is shown in the following figure.

Here, 3 to 8 decoder generates eight min terms. The two programmable OR gates have the access of
all these min terms. But, only the required min terms are programmed in order to produce the
respective Boolean functions by each OR gate. The symbol ‘X’ is used for programmable
connections.

Different Types of RAM (Random Access Memory)

RAM (Random Access Memory) is a part of computer’s Main Memory which is directly accessible by
CPU. RAM is used to Read and Write data into it which is accessed by CPU randomly. RAM is volatile
in nature; it means if the power goes off, the stored information is lost. RAM is used to store the
data that is currently processed by the CPU. Most of the programs and data that are
modifiable are stored in RAM.
Integrated RAM chips are available in two forms:
1. SRAM(Static RAM)
2. DRAM(Dynamic RAM)
The block diagram of RAM chip is given below.
The SRAM memories consist of circuits capable of retaining the stored information as long as the
power is applied. That means this type of memory requires constant power. SRAM memories are
used to build Cache Memory.
SRAM Memory Cell: Static memories (SRAM) are memories that consist of circuits capable of
retaining their state as long as power is on. The memory circuit is said to be static if the stored data
can be retained indefinitely, as long as the power supply is on, without any need for periodic
refresh operation. Thus this type of memories is called volatile memories.
The below figure shows a cell diagram of SRAM . A latch is formed by two inverters connected as
shown in the figure. Two transistors T1 and T2 are used for connecting the latch with two bit lines.
The purpose of these transistors is to act as switches that can be opened or closed under the control
of the word line, which is controlled by the address decoder. When the word line is at 0-level, the
transistors are turned off and the latch remains its information. For example, the cell is at state 1 if
the logic value at point A is 1 and at point B is 0. This state is retained as long as the word line is not
activated.
For Read operation, the word line is activated by the address input to the address decoder. The
activated word line closes both the transistors (switches) T1 and T2. Then the bit values at points A
and B can transmit to their respective bit lines. The sense/write circuit at the end of the bit lines
sends the output to the processor.
For Write operation, the address provided to the decoder activates the word line to close both the
switches. Then the bit value that to be written into the cell is provided through the sense/write
circuit and the signals in bit lines are then stored in the cell.
6T SRAM:
The circuit structure of the full CMOS static RAM cell is shown in figure. The memory cell consists of
simple CMOS inverters connected back to back, and two access transistors. The access transistors
are turned on whenever a word line is activated for read or write operation, connecting the cell to
the complementary bit line columns.
READ Operation:
Consider a data read operation, shown in figure, assuming that logic '0' is stored in the cell. The
transistors M2 and M5 are turned off, while the transistors M1 and M6 operate in linear mode. Thus
internal node voltages are V1 = 0 and V2 = VDD before the cell access transistors are turned on. The
active transistors at the beginning of data read operation are shown in figure

After the pass transistors M3 and M4 are turned on by the row selection circuitry, the voltage CBb
of will not change any significant variation since no current flows through M4. On the other hand
M1 and M3 will conduct a nonzero current and the voltage level of CB will begin to drop slightly.
The node voltage V1 will increase from its initial value of '0'V. The node voltage V1 may exceed the
threshold voltage of M2 during this process, forcing an unintended change of the stored state.
Therefore voltage must not exceed the threshold voltage of M2, so the transistor M2 remains
turned off during read phase, i.e., The transistor M3 is in saturation whereas M1 is linear.
Write Operation:
Consider the write '0' operation assuming that logic '1' is stored in the SRAM cell initially. Figure
shows the voltage levels in the CMOS SRAM cell at the beginning of the data write operation. The
transistors M1 and M6 are turned off, while M2 and M5 are operating in the linear mode. Thus the
internal node voltage V1 = VDD and V2 = 0 before the access transistors are turned on. The column
voltage Vb is forced to '0' by the write circuitry. Once M3 and M4 are turned on, we expect the nodal
voltage V2 to remain below the threshold voltage of M1, since M2 and M4 are designed according to
that.
 SRAM start writes of 0”

WRITE Circuit:
The principle of write circuit is to assert voltage of one of the columns to a low level. This can be
achieved by connecting either or to ground through transistor M3 and either of M2 or M1. The
transistor M3 is driven by the column decoder selecting the specified column. The transistor M1 is
on only in the presence of the write enable signal and when the data bit to be written is '0'. The
transistor M2 is on only in the presence of the write signal and when the data bit to be written is
'1'.
DRAM:
DRAM stores the binary information in the form of electric charges that applied to capacitors. The
stored information on the capacitors tend to lose over a period of time and thus the capacitors must
be periodically recharged to retain their usage. The main memory is generally made up of DRAM
chips. DRAM, dynamic random access memory has provided bulk of high-speed random access
memory in mainstream computers since the late 1970s. The access time of DRAM makes it well-
suited to use as main store, although it is slower than processors which means that cache memory
is required to bridge the gap between processor and DRAM performance.
DRAM is read/write random access memory and requires a more complex processor interface than
static random access memory. Very simple systems (e.g., controllers and embedded systems)) may
use static memory to avoid the cost and complexity of DRAM controller. DRAM stores data as a
charge on a capacitor which leaks away in several milliseconds. Consequently, dynamic memory
must be continually refreshed to re-write data before it is lost. This operation is invisible to the
user.
DRAM Memory Cell: Though SRAM is very fast, but it is expensive because of its every cell requires
several transistors. Relatively less expensive RAM is DRAM, due to the use of one transistor and one
capacitor in each cell, as shown in the below figure., where C is the capacitor and T is the transistor.
Information is stored in a DRAM cell in the form of a charge on a capacitor and this charge needs to
be periodically recharged.
The DRAM Memory Cell
The classic crossed-gate static memory cell uses six transistors. One version of the DRAM cell uses
three transistors providing twice the bit density per chip. The figure shows a three transistor cell.
Two-bit lines are used to access the cell, Bit-line 1 and Bit-line 2 (one is used in writing and one in
reading the cell).
A write operation is performed by asserting the Write-line and Bit-line 1 simultaneously to charge
or discharge the capacitor. A charge is transferred to or from the capacitor via transistor T1. A read
operation is performed by sensing the voltage on the capacitor via transistors T2 and T3. The read
is carried out by asserting the Readline and then sensing the voltage on BitLine2.
This three-transistor circuit consists of a one transistor switch to charge/discharge the capacitor
and a two-transistor sense amplifier to detect its state. The read operation is non-destructive; that
is, the voltage ion the capacitor is not modified by a read. The output of the read circuit is inverted
so that the data must be inverted again to read its corrector value.
The three-transistor DRAM cell is very attractive and relatively easy to construct. Unfortunately, it
is only half the size of a six-transistor static memory cell and, therefore, does not achieve the
maximum efficiency in terms of the size of a cell. Three-transistor DRAM cells were used in first
generation DRAMs.
1T DRAM:
The figure shows the one-transistor memory cell. This is, six times more space-efficient than the
static memory cell.

Bitline and Writeline can be asserted to write data into the cell by charging or discharging the cell’s
capacitor Cs. Reading the cell is slightly more complicated.
When transistor T1 conducts, the storage capacitor Cs is connected to the bit line. You might think
that the voltage on the bit line is the same as that originally stored on the capacitor. However, the
bit line has its own capacitance to ground that is distributed along the bit line and its connections.
Consequently, the two capacitors CB and CS form a voltage divisor. The voltage that is sensed is
proportional to CS/(CS + CB).
Reading the data from a one-transistor cell destroys the data and the original data has to be
rewritten in a refreshing operation.