UNIT III

MOSFET Configuration

Small Signal Model – Low Frequency Response

In the analysis of a MOSFET amplifier circuit, the transistor can be replaced by the equivalent-circuit model shown in
Fig. The rest of the circuit remains unchanged except that ideal constant dc voltage sources are replaced by short
circuits. This is a result of the fact that the voltage across an ideal constant dc voltage source does not change, and
thus there will always be a zero-voltage signal across a constant dc voltage source. A dual statement applies for
constant dc current sources; namely, the signal current of an ideal constant dc current source will always be zero, and
thus an ideal constant dc current source can be replaced by an open circuit in the small-signal equivalent circuit
of the amplifier. The circuit resulting can then be used to perform any required signal analysis, such as calculating
voltage gain.
The drain current is changed by gmVGS and is modeled by a voltage-dependent current source tied between the
drain and source terminals. The gate current is very small, and its change is negligible.
Typically, ro or rds is in the range of 10 k to 1000 k. It follows that the accuracy of the small-signal model can be
improved by including ro or rds in parallel with the controlled source.

ro =rds

Low Frequency Small Signal Model with body effect

Due to body effect, bulk potential influences Vth and hence (VGS -Vth). With all other terminals held at constant
voltage the bulk terminal behaves as a second gate since the drain current is a function of the bulk voltage given by
gmbVBS. We can modeled this dependance by a current source connected between drain and source given by
gmbVBS.

High Frequency Small Signal Model

T model
We now note that we have a controlled current source gmvgs connected across its control voltage vgs. We can
replace this controlled source by a resistance if this resistance draws an equal current as the source. Thus, the value of
the resistance is vgs/gmvgs = 1/gm. Observe that ig is still zero.

The model of Fig. shows that the resistance between gate and source looking into the source is 1/gm.
Voltage Amplifier Requirements:
 Voltage Gain High
 I/P impedance Large
 O/P Impedance Small
 Linearity (o/p should be linear with I/P)
Different types of loads can be used in an amplifier:
1. Resistive Load
2. Diode-connected Load
3. Current Source Load
4. Current Mirror

Different Single Stage amplifiers with resistive load

G D

D
G
S
V1 = VGS S

CS Amplifier – Low Frequency Small Signal Model Without Channel Length Modulation

G D

D
G
S
S
V1 = VGS

CD Amplifier – Low Frequency Small Signal Model Without Channel Length Modulation
 G D

D
G S=
S =X

V1

CG Amplifier – Low Frequency Small Signal Model with Channel Length Modulation

• Common-source amplifier: good voltage amplifier, better transconductance amplifier

– Large voltage gain (Negative)
– High input resistance
– Medium / high output resistance
• Common-drain amplifier: good voltage buffer
– Voltage gain ≈ 1
– High input resistance
– Low output resistance
• Common-gate amplifier: good current buffer
– Current gain ≈ 1
– Low input resistance
– High output resistance
Current Mirror
A current mirror can be thought as a current controlled current source. Ideally, the output impedance of a current
source should be infinite and capable of generating or drawing a constant current over a wide range of voltages.
However, finite value of output resistance and a limited output voltage is required to keep the device in saturation will
ultimately limit the performance of the current mirror. Current mirror has been used for biasing, loading, current
amplification etc. Current mirrors are employed in many applications such as operational amplifiers, analog to digital
and digital to analog converters.
The performance requirements for current mirrors are similar as for current sources:
 The output resistance must be as large as possible to reduce the dependence of the output current on the output
voltage
 The input resistance must be as small as possible
 The minimum allowed output voltage must be as small as possible
 The minimum input voltage must be also as small as possible
 The current gain must be precisely defined, constant with the supply voltage and temperature independent.

Simple Current Mirror

Two identical MOS devices that have equal gate-source voltages and operate in saturation carry equal currents.
Figure 1 shows the circuit of a simple MOS current mirror. The heart of the circuit is transistor Q1, the drain of which
is shorted to its gate,1 thereby forcing it to operate in the saturation mode with

where we have neglected channel-length modulation. The drain current of Q1 is supplied by V DD through resistor R,
which in most cases would be outside the IC chip. Since the gate currents are zero,

where the current through R is the reference current of the current source and is denoted I REF.
Now consider transistor Q2: It has the same VGS as Q1; thus, if we assume that it is operating in saturation, its drain
current, which is the output current IO of the current source, will be
where we have neglected channel-length modulation. The relation between the output current IO to the reference
current IREF as follows:

The special connection of Q1 and Q2 provides an output current I O that is related to the reference current IREF by the
aspect ratios of the transistors. In the special case of identical transistors (Assumption: Q1 and Q2: Active Regions
(Saturation) Areas are equal, VGS1 = VGS2 and Finite Output Impedance ignored), IO = IREF, and the circuit
simply replicates or mirrors the reference current in the output terminal.

Small Signal Model of Q1

Before finding rout, consider the small signal model for Q1 alone, as shown in figure below. For a low frequency
analysis, all the capacitors are ignored in the model.

To calculate the output impedance of Q1 transistor,

apply Thevenin’s equivalent theorem.
Applying KCL at Node V1

The output impedance equals 1/gm1 || rds1. Because typically rds1>> 1/gm1. We approximate the output
impedance of Q1 to be simply 1/gm1.
Small Signal model for the Current Mirror
Vgs2 has been connected to ground via a resistance of 1/gm1. Since no current flows through the 1/gm1 resistor.
Thus, since gm2Vgs2=0, the circuit is simplified to the equivalent small signal model. The small-signal output
impedance rout is simply equal to rds2.

 The minimum allowed output voltage is defined similarly as for the simple,
one transistor current source and is equal to the drain-source voltage of the
transistor Q2 at which the device is still biased in the saturation region.
 Therefore, the minimum output voltage across the current mirror is given
by Vmin=VDS(SAT)=VGS-VTH.
 The output resistance of current mirror is equal to output resistance of Q2.

Source Generated Current Mirror:

To increase output impedance, Source generated current mirror can be used.

By Applying KCL at node Vs Thus, the output impedance has been increased by a factor approximately
equal to (1+Rsgm2).

With Body Effect:

Cascode Current Mirror

 The cascade current circuit model has been given in figure below. This circuit is obtained by cascading the
basic current mirror to get larger output resistance. The output current is as same as in basic current mirror.
 Observe that in addition to the diode-connected transistor M1, which forms the basic mirror M1–M2,
another diode-connected transistor, M3, is used to provide a suitable bias voltage for the gate of the
cascode transistor M4.
 To determine the output resistance of the cascode mirror at the drain of M4, we assume that the voltages
across M1 and M3 are constant, and thus the signal voltages at the gates of M2 and M4 will be zero.
 If Vx and Vy are the same, the channel length modulation term for both M1 and M2 will be the same. hence,
the effect is corrected. M4 now shields Iout from voltage variations at the output node as Vy is fixed by
transistor M4 and does not depend on Vout, eliminating the systematic error.
 Usually, (W/L)1= (W/L)3 and (W/L)2=(W/L)4
 M1 and M3 are always in saturation.
 M2 and M4 both must be in saturation for current mirror to work

o VDS2 > (VGS-Vth)

o VDS4 > (VGS -Vth)
Note all 4 transistors have the same threshold voltage if body effect
is ignored.
VGS1=VGS2=VGS3=VGS4=VGS

Hence VX =VY= Vth +VOD

VG3 As M1 and M3 carry the same current,

VG3 = VB = VG4

VGS1

Minimum Output Voltage:

To determine the minimum allowed output voltage, all the transistors will be considered identical and perfectly
matched. In this case VDS (sat) marks the minimum drain-source voltage of a transistor for which the device still
operates in the saturated region. At the limit, the saturation condition is V DS (sat) =VGS-VTh.

As VD4 falls below VGS4 – VTH, M4 enters the triode

region, requiring a greater gate-source overdrive to
carry the same current. Vy begins to drop, causing I D2
and hence Iout to decrease slightly.
Output Impedance of Cascode Current Mirror

Rs = rds2 is an output impedance of a simple current mirror circuit (basic mirror M1–M2). 1/gm3 is an output
impedance of M3 (a diode connected transistor). Thus, the output impedance can be derived by considering M 4 as
a current source with a source generated resistor of value rds2.

Advantage: The output impedance has been increased by a factor of gm4 rds2.
Disadvantage: It reduces the maximum output signal swing possible before transistor enter the triode region.
The high output voltage requirements are the result of a large voltage drop on the transistor in the fundamental
mirror M1-M2.
Wide Swing Cascode Current Mirror
The wide swing cascode current mirror is a variant on the cascode on a lower bias voltage. Its small-signal behaviour
is identical to the regular cascode, but its biasing is quite different. The extra MOSFET M5 is simply to ensure the rest
stay in saturation. It provides the same output resistance as of standard cascode, but it provides low input and output
compliance voltage in comparison to standard cascode structure.
The output resistance of the high swing cascode current mirror is the same that of cascode current mirror
circuit when both M4 and M2 operate in the active region. However, the input voltage and the systematic gain error
are worsened compared to the cascode current mirror without level shift.
• The minimum output voltage or compliance voltage is reduced to the sum of two overdrive voltages or
saturation voltages.
• The input voltage becomes a diode drop, comparable to that of a simple mirror.
Minimum Output Voltage:
We this case minimum output voltage = VD4(min) =?

Because the minimum output voltage (VD4 (min)) does not contain a threshold component, the range
of output voltages for which M4 andM2 both operate in the active region is significantly improved.
Therefore, the current mirror as shown in Fig. places much less restriction on the range of output
voltages.

Alternate Method for minimum output calculation

since Q5 has the drain current but is (n+1) ^2 times smaller, we have

Vov5 = (n+1) Vov

Vov=Vov2=Vov1=
Vov3= Vov4= nVov
VG5=VG3=VG4=(n+1) Vov+Vth
VDS2=VDS1=VG5 -VGS4=VG5 - nVov+Vth=Vov

This drain-source voltage puts Q1 and Q2 right at the edge of the triode region. Thus, the minimum allowable
output voltage is now

Vout > Vov+Vov = (n+1) Vov

For n=1, Vout > 2 Vov = 2 VDS (sat.)

Aspect Ratio of M5 Transistor:

Wilson Current Mirror

It is an example of using shunt-series feedback to

increase the output impedance. Basically, M2 senses the
output current and the mirrors it to ID1 which in turn is
subtracted from input current Iin. Note that ID1 must
precisely equal Iin, otherwise the voltage at the gate of
M3, M4 would either increase or decrease, and the
negative feedback loop forces this equality.

The feedback arrangement increases the output impedance

by an amount equal to (1+AB) Rout.

The systematic gain error is not zero without M3 because the drain-
source voltage of M1 differs from that of M2 by the gate-source
voltage of M4.
Transistor M3 is inserted in series with M3 to equalize the drain-
source voltages (VX=VY) of M1 and M2. Also, insertion of M3 does
not change either the minimum output voltage for which applies or
the input voltage.
Not good for low-voltage design.

Output Impedance Calculation

But,
Common Source Amplifier (At Low Frequency)

 The common source topology used when high input

impedance is desired.
 The Current mirror used to supply the bias current
for the drive transistor.
 A high impedance can be realized without using a
large resistor or a large power supply.
 The gain for this circuit is in the range of -10 to
-100.

Small Signal Model at Low Frequency

A small signal equivalent circuit for low frequency analysis of the CS amplifier is shown in Figure. Vin and Rin are
the Thevenin equivalent of the input source. The output resistance R2 is made up of the parallel combination of the
drain- source resistance of Q1 and output impedance of the current mirror circuit.

Voltage Gain: Internal Input Impedance:

Ri = ∞
Input impedance = Rin + Ri = ∞

Internal Output Impedance: R2 =rds1 || rds2

Note that the input impedance of the circuit is very high at low frequencies. The magnitude of Av can be increased
by increasing W/L or decreasing ID if other parameters are constant.
Common Source Amplifier – High Frequency Analysis (Frequency Response)

The common-source topology exhibits a relatively high input impedance while providing voltage gain. All the
capacitances in the circuit, noting that Cgs1 is “grounded” capacitance while Cgd1 appears between the input and
the output. C2 is a parallel combination of Cdb1, Cdb2 and CL.

Cdb1 || Cdb2 ||CL

KCL at V1 node

KCL at output Node

At high frequencies where the gain has started to decrease but is much greater than unity, the first order term in
the numerator and the second order term in the denominator can be ignored.

Dominant pole approximation - Finding the roots – approximately

Now, suppose w1 << w2,

Common Drain Amplifier/ Source Follower

The source follower (also called the “common-drain”

stage) can operate as a voltage buffer.
The source follower features a very high input
resistance (ideally, infinite), a relatively low output
resistance, and an open-circuit voltage gain that is
near unity. Thus, the source follower is ideally suited
for implementing the unity-gain voltage buffer.
The source follower is also used as the output (i.e.,
last) stage in a multistage amplifier, where its
function is to equip the overall amplifier with a low
output resistance, thus enabling it to supply relatively
large load currents without loss of gain

Source Follower circuit with current mirror as a load & its small signal model

The transistor output admittances are gds1 and gds2.

The nonlinearity and Voltage gain is less than unity due to body effect. The drawbacks of source followers,
namely, nonlinearity due to body effect and voltage headroom consumption due to level shift, limit the use of this
topology. As a rule, we avoid the use of source followers unless they become necessary. One application of source
followers is in performing voltage-level shift.
Source Follower -Frequency Analysis (High Frequency)
Source Follower amplifiers can have
complex poles. So, the circuit exhibit
overshoot and ringing.
With the help of a compensation circuit,
complex poles can be converted into
real axis poles.

Ig1
KCL at node Vout
 Comparing above equation with standard equation for calculation of pole frequency and quality factor

Pole Frequency & Quality Factor Frequency corresponds to zero

Common Gate
A common-gate (CG) stage senses the input at the source and produces the output at the drain. The gate is connected
to a dc voltage to establish proper operating conditions.

Common Gate Amplifier with current mirror as a load and its low frequency small signal model

Is

KCL at Node Vout

KCL at Node Vin

The attenuation from the input to the transistor source can be considerable for a common gate amplifier when
Rs is large. This attenuation is given by,

Voltage Gain
Common Gate – High Frequency Response

An important property of this circuit is that it exhibits no

Miller multiplication of capacitances, potentially achieving
a wide band. Note, however, that the low input impedance
may load the preceding stage. Furthermore, since the voltage
drop across RD is typically maximized to obtain a reasonable
gain, the dc level of the input signal must be quite low.
For these reasons, the CG stage finds two principal
applications: as an amplifier in cases where a low input
impedance is required and in Cascode stages.

Frequency:

KCL at node A
KCL at Node Vout
Cascode Stage:

 Configuration: CG-stage in cascade with CS-stage - CS-stage is called the main device whereas CG is
called the cascode device.
 Basic Idea: It combines high input impedance and large transconductance of CS with the current
buffering property and the superior high frequency response of CG stage.
 Cascode Provides: wider bandwidth, increased small-signal gain, high input impedance, customized
output impedance.
 Applications: Current Source, Small-Signal Amplifier
 Main device (CS Stage) in saturation region converts and amplifies an input voltage signal into output
current.
 Cascode device (CG Stage) in saturation region routes the current generated by main device to R D

Telescopic Cascode Amplifier Folded Cascode Amplifier

Telescopic Cascode Amplifier:

It has both an n-channel CS transistor Q1 and an n-channel CG transistor Q2.
It can have quite large gain for a single stage due to large impedance at output. To enable this high gain, the
current source connected to the output nodes are realized using high quality cascode current mirrors.

Folded Cascode Amplifier:

Folded cascode Amplifier is an NMOS CS feeding into PMOS CG Stage or p-channel transistor as input and
n-channel transistor is used for cascode (CG stage) transistor.
It allows the dc level of the output signal to be same as the dc level of the input signal.
Folded Cascode amplifier is slower than the telescopic-cascode amplifier due to parasitic capacitances. The
impedance levels of the folded-cascode stage transistor are roughly three times larger due to the smaller
transconductance of p-channel transistors as compared to n-channel transistors.
Small Signal Model of Telescopic-Cascode Amplifier
If RL is present
rin2? (Without Capacitors)

KCL at node Vout

KCL at node Vs1

Substituting Value of Vout in above equation

If RL is present, KCL at node Vo:
Cascode Stage – High frequency Analysis

The resistance seen by Cs2 is the parallel combination of rin2 and rds1.

The total resistance seen at the drain of Q1 is rin2 || rds2.

Where, Gain of CS stage :

&

Miller Capacitance:
since Rs is the same order as rds
High Frequency Gain

Where, CL is a load capacitance

Additional Concepts
There are two ways to find the upper 3-dB frequency ωH
– Use open-circuit time constant method
– Use Miller’s theorem
– Brute force calculations to find Vout/vin
Open-Circuit Time Constant Method – Frequency Calculation
The approach:
• For each capacitor:
– set input signal to zero
– replace all other capacitors with open circuits
– find the effective resistance (Rio) seen by the capacitor Ci
• Sum the individual time constants (RCs or also called the open-circuit time
constants)

High Frequency Analysis: Common Source Amplifier

Miller's theorem

The Miller’s theorem establishes that in a linear circuit, if there exists a branch with impedance Z,
connecting two nodes with nodal voltages V1and V2, we can replace this branch by two branches
connecting the corresponding nodes to ground by impedances respectively Z / (1-K) and KZ / (K-1),
where K = V2 / V1.
 MCQ

1. The output impedance of given small signal model is

 1/gm
Vout  Zero
 Infinite
 None of the above

2. The small Signal Model of given circuit is

Vout
Vout
3. The output compliance voltage (minimum output voltage) of Wide Swing Cascode Current Mirror is
Vov
2Vov+2VT
2Vov
Vov+2VT

4. Folded cascode Amplifier is a/an

NMOS CS feeding into PMOS CG
NMOS CG feeding into PMOS CG
NMOS CG feeding into NMOS CG
Both A and B

5. Cascode Current mirror is not suitable for

High-Voltage Operation
High Output Requirement
Low-Voltage Operation
None of the above

6. Wilson Current Mirror employs

Series-Series Feedback
Shunt-Shunt Feedback
Series-Shunt Feedback
Shunt-Series Feedback

7. In Cascode amplifier, _____ is known as cascode device.

Common Source Stage
Common Gate Stage
Common Drain Stage
Current Mirror

8. Which of the following current mirror employs the negative feedback arrangement?
Wilson Current Mirror
Cascode Current Mirror
Simple current Mirror
Wide Swing Current Mirror
9. Output Impedance of Simple Current mirror can be increased by
Source Resistor
Cascoding
Both A and B
None of the above

10. The output compliance voltage (minimum output voltage) of simple Current Mirror is
Vov
2Vov+2VT
2Vov
Vov+2VT

11. A MOSFET operates in the ________________ Region when VGS > VGS (th) and VDS > (VGS- VGS (th))
Triode
Linear
Saturation
Cut-off
The output impedance of given circuit is
  Zero
 Infinite
 1/gm
 1/(gm+gmb)

12. The voltage Gain of Source Follower is less than unity

Due to Miller Capacitance
Due to Parasitic Capacitance
Due to Body Effect
Due to Short Channel Effect

13. Cascode Current Mirror Circuit has

High Output Impedance
High Output Swing
Low Output Impedance
Both A and B

14. The ratio of Iref to Iout is

0.5

50u

The MOSFET in the following circuit is in which configuration?

15. The MOSFET in the following circuit is in which configuration?

16. An NMOS technology has μnCox = 50 μA/V2 and Vt = 0.7 V. For a transistor with L = 1μm, find the value of
W that results in gm 1mA/V at ID = 0.5 mA.
10um
20um
30um
40um

17. Which of the following is true for the voltage gain (AV) for the common source configuration (represented by
A1) and the common gate configuration (represented by A2)?
A1 = A2
|A1| = |A2| and A1 ≠ A2
|A1| > |A2|
|A1| < |A2|
Ans: |A1| = |A2| (Approximately) and A1 ≠ A2

18. Which of the following has AVO independent of the circuit elements?
Common source configuration
Common gate configuration
Source follower configuration
None of the mentioned
19. Determine the conditions in which the MOSFET is operating in the saturation region
VGD > Vt (Threshold voltage)
VDS > VOV
ID ∝ (VOV)^2
i, ii, and iii are correct
i and iii are correct
i and ii are correct
ii and iii are correct

20. Vout?

Vin
V1
0
None of the above

21. The output impedance of given small signal model is

Zero
Infinite
1/gm
None of the above