Verilog construct/structure

Verilog design describes a single system

has suffix *.v
module inc interface(i/o), description of behaviour
case sensitive
each verilog declaration is terminated with a ;
comment is preceeded by //, /*
names must start with alphabetic letter

Data type used in verilog

value set
0=logic zero, false condition
1=logic one, true condition
x or X=unknown or uninitialized
z or Z=high impedance, tri-stated or floating
net data type
every signal must be associated with a data type
WIRE
variable data type
hold value assigned
REG - Can take values 0,1,x, and z
Vectors
one-dimensional array
used to designate multiple binary bits
<type>[<MSB_index>:<LSB_index>];
group of bits can be accessed using an index range
Arrays
multi-demensional array
vectors within the array all have same dimension
<element_type>[<MSB_index>:<LSB_index>] array name
[<array_start_index>:<array_end_index>];
System treats integer as a 32 bit vector so need to set data type
*When accessing an array, the name of array is given first followed by index
**Access an individual bit within an array by adding appending the index
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