Rele de Estado Sólido Con TRIAC - Foros de Electrónica

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JANUARY 2010
T H E I N T E R N AT I O N A L M A G A Z I N E F O R S E M I C O N D U C T O R M A N U FA C T U R I N G
Reducing process steps with

all-wet photoresist removal p. 10
Executive forecast for 2010 p. 12
Marketplace optimism abounds p. 14
More Moore vs. More than Moore p. 24
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𰀳𰁅𰁍𰁉𰁃𰁏𰁎𰁄𰁕𰁃𰁔𰁏𰁒𰀀
𰀡𰁕𰁔𰁏𰁍𰁁𰁔𰁅𰁄
𰀯𰁐𰁔𰁉𰁃𰁁𰁌𰀀𰀩𰁎𰁓𰁐𰁅𰁃𰁔𰁉𰁏𰁎
𰀷𰀨𰀹𰀀𰁗𰁁𰁓𰁔𰁅𰀀𰁍𰁏𰁎𰁅𰁙𰀌𰀀𰁔𰁉𰁍𰁅𰀀𰁁𰁎𰁄𰀀𰁒𰁅𰁓𰁏𰁕𰁒𰁃𰁅𰀀
𰁁𰁓𰁓𰁅𰁍𰁂𰁌𰁉𰁎𰁇𰀀𰁄𰁅𰁆𰁅𰁃𰁔𰁉𰁖𰁅𰀀𰁐𰁒𰁏𰁄𰁕𰁃𰁔𰁓𰀟
𰀩𰁍𰁁𰁇𰁅𰁓𰀀𰁆𰁒𰁏𰁍𰀀𰀶𰁉𰀀𰀴𰀥𰀣𰀨𰀮𰀯𰀬𰀯𰀧𰀹𰀀
𰀲𰀥𰀶𰀥𰀡𰀬𰀀𰁏𰁐𰁔𰁉𰁃𰁁𰁌𰀀𰁈𰁅𰁁𰁄
■𰀀𰀀𰀀𰀓𰂔𰁍𰀀𰁆𰁏𰁒𰁅𰁉𰁇𰁎𰀀𰁍𰁁𰁔𰁅𰁒𰁉𰁁𰁌𰀀𰁄𰁅𰁔𰁅𰁃𰁔𰁉𰁏𰁎𰀌𰀀𰁄𰁉𰁅𰀀𰁒𰁏𰁔𰁁𰁔𰁉𰁏𰁎𰀀𰁁𰁎𰁄𰀀𰁔𰁉𰁌𰁔𰀀𰁍𰁅𰁁𰁓𰁕𰁒𰁅𰁍𰁅𰁎𰁔𰀀𰁗𰁉𰁔𰁈𰀀𰁁𰀀𰁈𰁉𰁇𰁈𰀀𰁔𰁈𰁒𰁏𰁕𰁇𰁈𰁐𰁕𰁔𰀀
𰀀
■𰀀𰀀𰀀𰀥𰁌𰁉𰁍𰁉𰁎𰁁𰁔𰁅𰀀𰁄𰁅𰁆𰁅𰁃𰁔𰁉𰁖𰁅𰀀𰁐𰁒𰁏𰁄𰁕𰁃𰁔𰁓𰀀𰁁𰁎𰁄𰀀𰁍𰁁𰁋𰁅𰀀𰁍𰁏𰁎𰁅𰁙𰀀𰁔𰁈𰁒𰁏𰁕𰁇𰁈𰀀𰁉𰁎𰁃𰁒𰁅𰁁𰁓𰁉𰁎𰁇𰀀𰁙𰁏𰁕𰁒𰀀𰁑𰁕𰁁𰁌𰁉𰁔𰁙𰀀𰁌𰁅𰁖𰁅𰁌𰀁
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JA NUA RY 2 010 Vol. 53 • No. 1
CO N T E N T S
For wafer cleaning, a new all-wet stripping process eliminates the need
F E AT U R E S
for dry plasma ashing processes. (Photo courtesy of FSI International)
WAFER CLEANING
10 All-wet stripping process for highly
C OV E R A R T I C L E
implanted photoresist
An all-wet photoresist removal process has been
developed that reduces the number of process steps and
eliminates the potential for plasma-induced substrate
damage, while minimizing substrate material loss. Ron
Nan, Freda Lee, Jey Hung, SMIC, Shanghai, P.R.C.; James.
M.M. Chu, Jack Yuan, David Yang, FSI International,
Hsinchu, Taiwan R.O.C., Jeffery W. Butterbaugh, FSI
International, Chaska, MN USA
D E PA R T M E N T S
12 Executive viewpoints:
TECHNICAL FORECAST World News 6
The recovery has arrived! Tech News 8

The conventional wisdom is that scaling will ■ IMAPS 2009: Fusion bonding for 3D/TSV, wafer-level
multichip packaging for MEMS
continue at the traditional pace defi ned by Moore’s
Law well into the future. To gain insight into what ■ Getting greener: New fab EHS benchmark tool debuts
technologies will be required , and what impact the ■ Improved tungsten deposition for 3Xnm logic, memory
recent downturn had on technology development, Web Exclusives 4
leading executives provide their perspectives on
what 2010 will bring . Product News 22
Ad Index 23
14 For 2010, marketplace

ANALYST OUTLOOK
optimism abounds
Booming. Recovery. Upturn. Choose your favorite COLUMNS
optimistic word, and that is what many analysts
surveyed by Solid State Technology are projecting for
the semiconductor market in 2010. Editorial 5
Life after the “Reset” button
Pete Singer, Editor-in-Chief
Industry forum 24
Innovation on the interface between disciplines
The semiconductor industry is positioning itself on the plane of
two complementary axes—the traditional scaling or More Moore
axis, and the More than Moore axis. Luc Van den hove, IMEC,
Leuven, Belgium
2 Solid State Technology ■ January 2010 ■ www.solid-state.com
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Solid State Technology ONLINE

Diane Lieberman, Group Publisher,
Ph: 603/891-9441, dianel@pennwell.com
Peter Singer, Editor-in-Chief,
Web Exclusives Ph: 603/891-9217, psinger@pennwell.com
Robert C. Haavind, Editorial Director,
Ph: 603/891-9453, bobh@pennwell.com
Steve Smith, Managing Editor,
ONLINE AT WWW.SOLID-STATE.COM
____________________ Ph: 603/891-9139, stevesm@pennwell.com
IEDM 2009 Debra Vogler, Senior Technical Editor,
Ph: 408/774-9283, debrav@pennwell.com
The annual International Electron
James Montgomery, News Editor,
Devices Meeting (IEDM) is arguably Ph: 603/891-9109, jamesm@pennwell.com
the semiconductor industry’s top Katherine Derbyshire, Contributing Technical Editor
tech showcase. SST reports on key Selma Uslaner, Director of Industry Relations
discussions about high-k/metal Gate (TiN/Pt/Au) Rachael Caron, Marketing Manager
gate (HKMG) gate-first vs. gate-last Melody Lindner, Presentation Editor
LG = 75nm Valerie Richards, Production Manager
options; why silicon-based scaling InGaAs n+ cap
Dan Rodd, Illustrator
will continue to at least the 11nm InGaAs QW Michelle McKeon, Audience Development Manager
40Å TaSiOx/20Å InP Marcella Hanson, Ad Traffic Manager
node (with a caveat), and individual composite gate stack
company announcements ranging InAIAs/GaAs
on Si EDITORIAL ADVISORY BOARD
from Cu interconnects to III-V chips, John O. Borland, J.O.B. Technologies
spintronics, and CNT transistors. Jeffrey C. Demmin, Tessera Technologies Inc.
Michael A. Fury, InterCrossIP Management LLC
Rajarao Jammy, SEMATECH
Making e-beam direct write faster William Kroll, Matheson Tri-Gas
Ernest Levine, Albany NanoTech
E-beam direct write lithography Lars Liebmann, IBM Corp.
using character projection VDD Dipu Pramanik, Cadence Design Systems Inc.
Griff Resor, Resor Associates
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enable maskless production for A.C. Tobey, ACT International
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Hybrid CMOS-memristors, the future of analog

Industry luminaries packed the Silicon Valley Engineering Council’s recent
open house, where HP senior Fellow Stan Williams discussed research by his
group and others on memristors, and hinted on upcoming developments in
this area.
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EDITORIAL
Life after the “Reset” button
I
n 2005, SEMI commissioned a report that looked at the one or two and they’ve got to get
funding gap between what it would cost to achieve the goals it right. It’s really interesting to
defined by the industry in the International Technology listen to how people are trying to
Roadmap for Semiconductors (ITRS) and what equipment work their way through this. We
and materials suppliers were realistically capable of spending know how it worked, we know how we all got successful, but
on R&D. The conclusion, at the time, was that by 2010 there is that going to work for the next ten years? I don’t think it
would be a shortage of somewhere between $6-9 billion (the will,” Armburst said.
higher figure including the costs of transitioning to 450mm). One solution is, of course, consortia such as
The recession is, by all measures, over for the semicon- SEMATECH and IMEC. Although they have very different
ductor industry. This issue features rosy outlooks from models, both play a role in helping suppliers develop new
forecasters and industry executives (and if they had written technologies and determine their production worthiness.
them even closer to press time, they’d be rosier still). After “When we get our hands on a piece of equipment, we
many devastating quarters, the capex faucet has can provide a dataset back, which is very useful to
been turned on, and equipment and the supplier, and give them a pretty
material suppliers are enjoying objective perspective on how
“a very strong growth spurt,” Back to business as usual? the tool is proving out for
as Dean Freeman, research Hardly. Suppliers have had to hit the manufacturability,” said
VP at Gartner, noted in revenue “Reset” button, while R&D Armburst. “There’s an ongoing
mid-December. Foundries and demands continue to grow. set of interest in the supplier
a few memory companies started community, and I think we can
spending again in 2H09, and 1H10 will do more.”
see an influx of technology upgrades. After a possible lull It’s unlikely that this will be enough, however, to offset
in 3Q10, look for capacity upgrades to ramp up into 2011, the the R&D funding gap. If it was projected to be $6-9B five
he says. years ago, it can only have gotten bigger due to the deepest
Back to business as usual? Hardly. Suppliers have had recession and most dramatic reduction in capex spending
to hit the revenue “Reset” button, while R&D demands the industry has ever seen. Executives at equipment suppliers
continue to grow. At the recent International Electron look down the road and see that new technologies, such as
Devices Meeting, I had a chance to sit down with Dan FinFETs and high mobility transistors with III-V channels,
Armbrust, the new president and CEO of SEMATECH. are probably feasible, but openly question whether it’s
Dan, who was most recently the vice president of 300mm possible given R&D spending constraints.
semiconductor operations at IBM in East Fishkill prior The conventional wisdom is that scaling will continue
to SEMATECH, described the R&D funding situation as at the traditional pace defi ned by Moore’s Law well into
“under a lot of stress.” He said equipment supplier share- the future. Companies are just now ramping 32nm
holders “are going to be pressing to reset R&D (i.e., spend devices into volume production, and the industry is on
less) at the very same time that customers, the chipmakers, track to move to the 22nm node in 2011. Th at will be
are saying you can’t reset R&D. We need you to invest more. followed by 15nm in the 2014-15 timeframe and the
And, oh by the way, we’d like you to consider 450mm.” 11nm node in 2017-18. Further scaling to 8 and 5nm
Armbrust believes the equipment industry may have to nodes will occur beyond 2020, perhaps enabled by
cooperate in a way similar to what that the chipmakers did silicon nanowires.
20 years ago. Saying EUV is a perfect example, where only Such continued scaling is called More Moore (not to
one supplier is fielding a solution, Armbrust said “it’s getting be confused with More than Moore, which constitutes
to the point where we’re only going to have one supplier, and the integrated of devices with diverse functionality, such
they can’t even afford the development or won’t take the risk as sensors, batteries, passive components, microprocessors
of developing the tool that’s needed without an expression and energy harvesting devices). The massive R&D spending
financially of commitment of the ultimate beneficiaries, gap, however, is making another scenario increasingly likely:
which would be the mask makers or the chip makers,” he No More Moore. ■
said. “You’re just getting into a very different world where Pete Singer
you don’t have two or three or four suppliers, you’ve got Editor-in-Chief
www.solid-state.com ■ January 2010 ■ Solid State Technology 5
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WORLD NEWS
■ BUSINESS TRENDS
Gartner: Chip capex recovery marches on
A final year-end boost to Gartner’s 2009 $B equipment spending will be availability

semiconductor capital spending forecast 60 of 193nm immersion lithography tools,
paves the way for a big recovery in 2010 and necessary for foundry and memory
beyond for almost all sectors. 50 technology upgrades. Demand will vary
Foundries and a few memory companies 40
in the packaging/assembly sector, with
started spending again in 2H09, and 1H10 more investments required for advanced
will see an influx of technology upgrades, 30 processes, such as wafer-level packaging,
noted Dean Freeman, research VP at Gartner. 20 3D processes, and through-silicon vias
After a possible lull in 3Q10, look for capacity (TSV).
upgrades to ramp up into 2011, he says. 10 Gartner has lowered its outlook for the
After a -43% plunge in 2009, capex ATE sector through the entire forecast
0
is expected to surge 45% surge in 2009 2010 2011 2012 2013 2014 period as “memory test has completely
Year
2010, with very solid growth in nearly collapsed” and DDR3 ramps in 2009
equipment sector—though broken into Wafer fab equipment Automated test “failed to materialize,” Freeman explained;
Packaging/assembly Other spending
quarters, growth “is actually relatively consolidation and technology improve-
flat coming off of 4Q09,” Freeman told Worldwide semiconductor capital equipment spending ments in this sector “will keep this growing
SST. The big question for wafer-fab forecast. (Source: Gartner) at a lower pace than before.”
WORLDWIDE HIGHLIGHTS Hemlock Semiconductor has broken Elpida plans to ramp production of 32-bit
The World Semiconductor Trade Statistics ground on a $1.2B plant in Clarksville, TN, 2Gb DDR2 in 2Q10, and has opened a high-
(WSTS) and Gartner have updated their chip scheduled to be completed in 2012. speed DRAM test lab in Germany.
sales projections: about an -11% decline in
2009, and 12%-13% growth in 2010. An unidentified “Tier-1 fab in East Asia”
ASIAFOCUS has ordered multiple Jordan Valley X-ray
SEMATECH has named Daniel Armbrust, Toshiba says it has developed a high- metrology tools for Cu and seed barrier
most recently IBM’s VP of 300mm opera- resolution photoresist specifically for EUV processes.
tions at East Fishkill, as president/CEO. lithography viable to 20nm.
STMicroelectronics is extending its use of STATS ChipPAC has ramped volume EUROFOCUS
Brion Technologies’ Tachyon source-mask production of embedded wafer-level BGA. ASM has licensed processes and material
optimization to 28nm-node deployment and IP to Air Liquide related to deposition of
22nm development. Fujitsu says it is exploring “drastic reforms,” advanced ultrahigh-k insulator films.
including realigning chip production
Nemotek Technologie has added in-house lines—but for now, no tie-ups with rivals. Scottish foundry Semefab is investing £6.6M
testing capabilities for wafer-level cameras. (US $11M) in a new wafer fab for frontend
Hynix reportedly will spend roughly $2B processing of MEMS structures.
in 2010 on its semiconductor business, but
USA mostly not on new facilities. Plus Semi is taking over X-Fabs’ 5000
Applied Materials has acquired Semitool for WSPM (200mm-equivalent) wafer fab in
~$364M to solidify footholds in 3D packaging/ TSMC plans to launch a process qualification Plymouth, UK, reuniting two former Plessey
TSVs and Cu-based interconnects. and service package for automotive-grade operations.
semiconductors, which its 200mm Fab 10
ClassOne Equipment has purchased the in Shanghai is prepared to manufacture. Soitec and CEA-LETI are expanding their
equipment inventory of Colibrys’ MEMS collaboration on wafer-level 3D integration,
facility in Stafford, TX. Tokyo Electron Ltd. reportedly will resume starting with process customization for
plans to build a new factory near Sendai. 200mm-300mm prototyping. ■
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TECHNOLOGY NEWS
IMAPS 2009: Fusion bonding for 3D/TSV,

wafer-level/multichip packaging for MEMS
resentations at the International Misalignment dy (nm) atmospheric pressure. These were
Symposium on Microelectronics the motivating factors to develop a
500
(IMAPS, Nov. 1-5) included WLP encapsulation structure with
400 Left alignment
discussion of through-silicon Right alignment hybrid thin-film (four thin-film
300
via (TSV) /3D integration challenges layers) using standard backend-
200
and temporary bonding steps qualified of-line LSI technologies. The first
100
for different process flows, and a wafer- layer (SiO) is the cap layer; the
level packaging (WLP) encapsulation -500 -400 -300 -200 -100 0 100 200 300 400 500 second layer (polymer) is the plug
-100
process and stacked multi-chip package dx (nm) dx (nm) layer; the third layer is the moisture
-200
(MCP) for a MEMS variable capacitor barrier (SiN); and the fourth layer,
-300
and control IC chip. formed in the polymer, protects the
-400
EV Group’s Th orsten Matthias entire encapsulation from subse-
-500
presented his company’s solutions quent MCP processes.
Alignment results with the EVG SmartView NT Aligner (400 alignments). (Source:
for TSV/3D integration, with data The motivation for devel-
EV Group)
showing that temporary bonding opment of a stacked MCP for the
to a carrier wafer, thinning, backside met with advanced CMP technology. control IC chip (that provides the actuation
processing, and subsequent debonding The surface pre-processing step used voltage to the MEMS capacitor) was to find
were qualified for several different process by the group, called “LowTemp” plasma a fabrication process compatible with the
flows (session #WA5, paper #1). activation, modifies the wafer surface in such MEMS capacitor structure, because the
Though Cu-Cu thermo-compression a way that the annealing temperature can be control chip was to be integrated into the
wafer bonding has shown promise for very reduced to a range of 200-400°C. According WLP package. Endo noted that although
high TSV density face-to-face integration to EV Group, such plasma activation enables the fabrication process of the stacked MCP
applications, the researchers found that the usage of fusion wafer bonding for 3D is based on a conventional packaging
fusion bonding, with its cost-of-ownership integration. Alignment accuracy for the process, some of the processes had to
advantages, is very attractive compared to group’s research was verified using the EVG be optimized to handle the fragile WLP
metal-metal bonding. Among the other SmartView NT Aligner (see figure). encapsulation. The researchers, therefore,
advantages of fusion bonding noted by Also at IMAPS, Toshiba’s Mitsuyoshi optimized a stacked MCP process, having
Matthias: high alignment accuracy (because Endo reported on a wafer-level packaging also decided that chip-scale or system-on-
misalignment due to thermal expansion of encapsulation process and a stacked multichip (SoC) packages would be difficult to
the wafers is eliminated), high-throughput, chip package for an electrostatically actuated integrate with the MEMS chip.
and the ability to be inspected after MEMS variable capacitor, and the control IC Based on the reliability testing data
pre-bonding prior to final annealing. chip, respectively (session #TA5, paper #1). (temperature cycling, accelerated moisture
The main challenges of using fusion Because a MEMS variable capacitor needs resistance, and moisture/reflow sensitivity),
bonding, according to the researchers, are to be operated in a dry atmosphere (to avoid the researchers concluded that neither
sensitivity to particles and surface roughness. voltage shifts), and it is known that movable voids nor cracks were present in the MCP.
An integrated cleaning module addresses the electrodes (in a MEMS capacitor) vibrate in a Normal operation of the MEMS variable
problem of particles, and the surface micro- vacuum, the researchers needed a process that capacitor was confirmed up to 85% relative
roughness requirement of 0.5-2nm can be enabled the capacitor to be operated under humidity. — D.V.
Getting greener: New fab EHS benchmark tool debuts

Researchers at the Department of improvement—all toward the pursuit of Semiconductor Industry Association
Energy’s Lawrence Berkeley National a “greener” industry. (SIA) and validated with help from
Labs have devised a tool to gauge a The Fabs21 beta tool draws on research ISMI’s Green Fab working group. Users
semiconductor facility’s energy and examining other high-tech facilities can compare up to 46 different building-
water consumption, and compare against (labs, data centers, cleanrooms), as well and system-level metrics for semicon-
similar facilities, to identify areas of as survey methods/data collected by the ductor manufacturing facilities, distilled
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into characteristics of energy and Improved tungsten deposition for 3Xnm logic, memory
water consumption—a facility’s overall
energy and water efficiency, for example, critical dimensions (CD),
can be benchmarked as kWh/cm 2 , but their higher resistivity
BTU/cm 2 wafer out, and gallons/ft 2 of 55nm N-diff contacts will keep scaling with each
manufacturing space. Such metrics help node progression. The new
facility operators applying for LEED LRWxT tungsten deposition
Conventional nucleation
certification of existing buildings. process involves three steps:
PNLxT
The tool also can calculate system- LRWxT
a <20Å thick nucleation layer
level metrics for “action-oriented bench- is deposited; a low-resistivity
marking” to identify potential systems 25 75 125 175 225 275 tungsten (LRWxT) treatment
Contact resistance (Ω/unit)
areas for improvement—e.g., ventilation step is applied to promote
airf low efficiency (W/ft 3/m) or chiller Kelvin contact resistance measurements obtained from 55nm N-type doped diffused growth of the low resistivity
plant efficiency (kW/ton). contacts, showing reduced Rc with PNLxT, and additional Rc decrease with LRWxT. bulk film; and an optimized
(Source: Novellus Systems; data courtesy of NEC Electronics)
Metrics span environmental condi- CVD-W film is deposited
tions, ventilation, cooling and heating, Novellus Systems has developed a new for the bulk fill of nanometer-sized struc-
process equipment, and lighting/ tungsten deposition process that can reduce tures. Filled features contain larger tungsten
electrical systems. Facilities can be contact and line resistance at the 3Xnm node grains than either conventional silane-based
benchmarked across a set of years or versus conventional tungsten CVD. Dubbed nucleation or PNLxT process; the larger grain
compared to similar facilities, and “LRWxT,” the new approach, when used with structure lowers the contact resistance of NiSi
filtered by criteria such as climate zone, the company’s Altus Max system, results in contacts by 20%-30%, the company claims.
facility type, and cleanliness level. highly conformal large grain size films with The process has been tested on device
After further beta-testing by ISMI lower tungsten bulk resistivity. features provided by NEC Electronics; results
members, Fabs21 was planned for full At 32nm and beyond, thinner tungsten were presented at the Advanced Metalli-
release in November 2009. — J.M. (W) films are required to fill smaller zation Conference in October. — J.M.
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WA F E R C L E A N I N G C OV E R A R T I C L E
All-wet stripping process for

highly implanted photoresist
E XECUTIVE OVERVIEW patterning cycle time, which can be especially
A new all-wet stripping process elimi-
important for foundry CMOS fabrication.
nates the need for dry plasma ashing processes in the removal of highly
In a high-volume production environment,
implanted photoresist, while maintaining low defectivity levels and high
yield performance at least equivalent to the process of record. The elim- adoption of such an all-wet photoresist stripping
ination of the ashing step reduces undesirable substrate damage and process can only be justified if it matches the
material losses, improves cycle time, frees up fab floor space, and reduces final yield performance of the existing process
capital investment and operating costs. of record (POR). In the methodology discussed
in this article, therefore, all-wet post-ion implan-
tation photoresist resist stripping
Material loss etch rate
I
n CMOS fabrication, ion qualification is started from the well
Etch amount (Å)
implantation is used to loop for both nMOS and pMOS, with
25.0 Poly Si-APM
modify the silicon substrate for of PR All Wet multiple implantation steps.
various band gap engineering The qualification results show
20.0
needs. Typically, patterned photo- equivalent physical defect control
resist (PR) is used to define the ion and >99.9% yield performance
15.0 Poly Si-APM
implant location. After ion implan- of POR
similarity compared to the ash plus
tation, the patterned photoresist wet clean POR. Estimated benefits
10.0 Oxide-APM
must be completely removed and of PR All Wet
resulting from the adoption of this
the surface must be prepared for process include a >60% reduction
Oxide-APM
the next round of patterning and 5.0 of POR in process cycle time and a >300%
ion implantation. Ion implantation improvement in productive
forms a tough layer at the surface of 0.0 0 5 10 15 20
cleanroom space utilization.
the photo resist, making it difficult Process time (mins) The ViPR all-wet photoresist
to remove. removal solution developed by FSI is
Figure 1. Material loss behavior of APM conditions in PR all-wet and post-ash clean.
Implanted photoresist is typically a batch spray process with point of use
removed using dry plasma ashing, followed by wet chemical cleaning. (POU) mixing of pre-heated (150° C) sulfuric acid and room temper-
Three loops of ion implant process—isolation (well) loop, transistor ature hydrogen peroxide (SPM), capable of achieving a temperature
channel loop, and transistor structure loop—are used to build a of up to 200° C on the wafer surface due to exothermic mixing. The
CMOS device. The well loop alone accounts for nearly one-third of all-wet process sequence is used for complete removal of implanted
the total process layers, and can involve more than 21 steps of ion photoresist, with low defectivity.
implantation and photoresist stripping in the case of 90nm logic A three-stage methodology was used to systematically develop
CMOS fabrication. Thus, any reduction in cycle time multiplies and qualify the PR all-wet process in the existing production flow:
quickly to provide a significant benefit in total processing time. • In stage one, the process condition for damage-free all-wet
implanted PR stripping was determined by tuning the high
All-wet photoresist advantages temperature SPM step conditions.
An all-wet photoresist removal process has been proposed to • In stage two, the ammonium hydroxide-hydrogen peroxide
eliminate the potential for plasma-induced substrate damage (APM) step was tuned for the lowest defectivity and material
and reduce substrate material loss [1, 2]. In addition, eliminating loss matching. Stage two included tuning the intermittent
the plasma ash step dramatically reduces the ion implantation de-ionized water rinse steps, APM ratio, final de-ionized water
rinse steps, and final nitrogen spin dry.
Ron Nan, Freda Lee, Jey Hung, SMIC, Shanghai, P.R.C.; James. M.M. Chu, Jack • In stage three, production split-lots were used with in-line metrology
Yuan, David Yang, FSI International, Hsinchu, Taiwan R.O.C., Jeffery W. Butter- to characterize any remaining physical defects and with final yield
baugh, FSI International, Chaska, MN USA electrical measurements at the wafer acceptance test (WAT).
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Process results: Stages Process defect control performance. This technique uses step-by-step
1 and 2. First, the post-ion- identical characterization during the fabrication
implant photoresist all-wet PW #1 PW #3 NW #1 NW #3 process and final yield performance analysis
stripping process condition through various wafer acceptance tests (WAT),
was determined through and then employs a proprietary algorithm to
short loop wafer test. The test evaluate the harmonization confidence and
results indicate the well loop determine the similarity of process results.
post-ion-implant photoresist Physical defect scanning of the yield lot wafers
can be effectively stripped is done on an in-line defect scan tool after the
within five minutes of SPM post-ion implant photoresist stripping process
exposure. Then, the chemical on each layer. The physical scan determined any
process-induced material loss possible pattern damage, photoresist residue,
behavior that takes place on and fall-on particle on the wafer. The developed
polysilicon and silicon oxide damage-free post-ion implant photoresist
Ash + Wet PR All Wet
are explored by blanket wafers stripping processes for both baseline and all-wet
with extended chemical Figure 2. The well loop fall-on defect control result. process gave the same defect performance on
exposure time. yield lot wafers. The fall-on particles results (Fig. 2) shows the all-wet
The etch rate behavior from both the manufacturing baseline process has achieved equivalent defect performance on both nMOS
(post-ash clean) process and and pMOS well loops.
WAT yield performance comparison
the all-wet stripping process Yield performance
Harmonization confidence (%)
are shown in Fig. 1. The etch index matching to
101
rate data were used to set the POR. In final WAT,
all-wet stripping process param- 100 the electrical perfor-
eters to minimize the fall-on mance for the device
99
defect control performance saturation current (Idsat),
and to match process-induced 98 off-state current (Ioff ),
material loss to the manufac- and threshold voltage at
97
turing baseline on current device constant current (Vth)
geometries. A process using 96 were measured on two
five minutes of SPM exposure test keys on both nMOS
95
followed by two minutes of APM Test #1 #2 #1 #2 #1 #2 #1 #2 #1 #2 #1 #2 and pMOS. The overall
exposure was used for all four key NMOS NMOS PMOS PMOS NMOS NMOS PMOS PMOS NMOS NMOS PMOS PMOS device yield performance
well loops in this work. Idsat Idsat Idsat Idsat Ioff Ioff Ioff Ioff Vth Vth Vth Vth comparison was made
Yield lot results: Stage 3. Figure 3. Wafer acceptance test result comparison by harmonization of the confidence level. using the harmonization
The yield lot wafers were prepared with a 300mm standard process confidence technique, described earlier, to check the similarity of
flow, and split at the well loop photoresist stripping steps between process results and to qualify device functionality. Figure 3 shows the
the existing POR (plasma ash followed by wet harmonization confidence level for the all-wet
Ratio of WPH to space
cleaning) and the all-wet process. After well stripping split compared to the POR split is
Productivity (WPH/μ2)
loop ion implantation, the split wafers were >99.9% for all parameters, which is well above
merged and followed the rest of the baseline 30.0 the targeted goal of 99%.
process steps to complete the CMOS fabrication. 25.0
Inline defect scanning was used to measure the Operational benefit review
20.0
physical defect performance during processing, Process cycle time. Compared to the POR
and automatic electrical probing was used in 15.0 (ash + wet), this all-wet process can reduce
the wafer acceptance test (WAT) for final yield 10.0 the photoresist stripping cycle time from 70
performance comparison over selected perfor- minutes to about 25 minutes for each mask—
5.0
mance items. about one-third of the POR baseline cycle
0.0 time. Considering the seven mask layers of
Ash + PAC PR All Wet
Yield performance benchmark the well loop, total cycle time through all-wet
To achieve a volume production comparison Figure 4. Cleanroom space productivity (wafer per hour photoresist stripping is reduced from eight
between the post-ion implant photoresist vs. space occupation). hours to about five hours, which is a >60%
all-wet stripping process and current baseline (ash + post-ash clean) reduction in cycle time.
process, a proprietary statistical control technique, called the harmo- Cleanroom space occupation. Compared to the baseline
nization confidence [3], was used to benchmark the wafer final yield continued on page 17
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TECHNIC AL FOREC AST
Executive viewpoints:
The recovery has arrived!
he conventional wisdom is that scaling will continue at the EDA industry has developed new approaches, including electronic
traditional pace defined by Moore’s Law well into the future. system level (ESL), coverage-based verification, emulation, intelligent
Companies are just now ramping 32nm devices into volume testbench, hardware acceleration of test benches and assertion-based
production, and the industry is on track to move to the 22nm verification, which are all showing great results. The challenge here
node in 2011. That will be followed by 15nm in the 2014-15 timeframe is to help designers adopt these new methods to improve their verifi-
and the 11nm node in 2017-18. Further scaling to 8 and 5nm nodes cation approaches.
will occur beyond 2020, perhaps enabled by silicon nanowires. Dealing with manufacturing variability. As we move toward
To gain insight into what technologies will be required to make smaller geometries, we need better techniques to manage the growing
all this happen, and what impact the recent downturn has had on problem of variability in nanometer integrated circuit manufacturing.
technology development, we invited leading industry executives to We are really starting to see that design for manufacturing (DFM)—
provide their perspectives on what 2010 will bring by asking them something the industry has been talking about for years—is now
two questions: 1) How will the current economic climate affect our becoming critical to design. DFM requires a detailed understanding
market in 2010?, and 2) What will be the most significant techno- of optical proximity correction (OPC). Specialists in optics have joined
logical advancements in 2010? These are their responses: traditional electronic design specialists at EDA companies to create
these key technologies. And EDA companies are working closely with
Delivering 10X design improvements semiconductor manufacturers on process technology, as evidenced
Time and time again, escalating complexity by the IBM/Mentor joint development program at 22nm.
has threatened to derail the IC industry from By creating innovative solutions to tackle challenges such as
the extraordinary 35% annual reduction in these, the EDA industry enables designers to successfully exploit the
transistor pricing it has enjoyed the past 40+ exponential rise in complexity to continue the remarkable 35% annual
years. Fortunately, in every instance, creative cost reduction we have grown to expect from the high tech industry.
engineers and companies have seen this as a
challenge and opportunity to innovate. As Shrink is the key
a result, the electronic design automation Walden C. Rhines, Shrink is a key business differentiator for chipmakers as it continues
Mentor Graphics, Wilson-
(EDA) industry has repeatedly delivered order to provide the most cost-effective manufacturing solution. And
ville, OR USA
of magnitude improvements in every aspect of lithography continues adding value, with ArF
the IC design cycle for over three decades. immersion lithography providing shrink to 4x
Today, the exponential rise in complexity has quickened its pace as and 3x nodes.
the industry moves toward adoption of 28nm and below. In the next Three significant things will happen to
few years, 10X improvements in design methodologies are needed lithography in 2010. First, double-patterning
in the following areas: techniques will be commonly implemented
Low power design (from system level through physical layout). to realize low-3x and 2x nm manufacturing.
This issue of power can no longer wait to be addressed in the backend. Second, the lithography process will become Martin van den Brink,
Architectural choices made in the front end of design have very large more holistic. Third, the first production EUV EVP, Marketing and Tech-
impact on the power, which is why advanced design tools now provide systems will ship. nology, ASML, Eindhoven,
accurate power modeling early in the design flow when architectural For the 2x node, many chipmakers will The Netherlands
tradeoffs can be made more easily. Look to see many exciting innova- employ double-patterning techniques with ArF immersion; however,
tions in low power design capabilities. with double-patterning, overlay requirements become extremely
Keeping up with the growing functional verification challenge. stringent and productivity becomes more important. Chipmakers
As designs explode in size and complexity, old-school simulation will look to lithography systems that provide low single-digit overlay
runs aren’t sufficient to reach effective coverage. Fortunately, the performance while at the same time driving system throughput to
200 wafers per hour and more.
Pete Singer, Editor-in-Chief Holistic lithography is the intelligent integration of computational
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lithography, wafer lithography and process control. Today’s ultra- approach to subsystem design and manufacture enables suppliers
small feature sizes and complex pattern geometries mean that it is to develop process and performance-specific solutions using off-the-
no longer enough to optimize individual IC manufacturing steps in shelf components. This model allows for flexibility of customi-
isolation. Manufacturers need to use the degrees of freedom available zation, while reducing costs to OEMs and IDMs, by implementing
in one step to compensate for limitations in others. By integrating a standardized set of tools. Inherent in the ability to standardize
“pre-manufacturing” and “manufacturing” products and processes, platforms is significant cost savings, while customization can
lithography becomes “application aware” and low-k1 processing can enhance critical aspects of the process tool performance.
be done at acceptable yield. For example, new technologies such as It is change along these lines that will be required to sustain the
flexible illumination—already an inherently powerful tool—become incredible creative force of the semiconductor industry, which is
even more valuable when working in concert with Source Mask needed to ensure the constant flow of innovation in order to meet
Optimization (SMO) products. the projected growth in the future.
Two EUV alpha demo tools shipped in 2006, and since that
time have provided a platform to build industry infrastructure A decade gone, new challenges ahead
and develop EUV processing knowledge. The first production EUV It’s hard to believe as I reflect on our industry
system integration is being completed and will ship in 2010. As a today, that the first decade of the 21st century
single exposure solution, EUV imposes fewer design restrictions and is already gone. The 2000s have brought both
provides better cost of ownership than immersion double-patterning triumph and tragedy to the macroeconomic
techniques. EUV is a multi-generation platform that will enable climate and semiconductor industry as a
shrink down to 5nm. whole—with the harsh economic trials of late
Immersion, double patterning and EUV are all required to meet 2008 and 2009 still emblazoned on our minds.
diverse customer requirements. Implementing these technologies As I reflect today on the 12 months ahead, I Brian Trafas, Chief
using a holistic lithographic approach will continue to provide shrink can say that while there is still a lot of uncertainty Marketing Officer, KLA-
for many years to come. about the pace of economic recovery, the overall Tencor, Milpitas, CA USA
semiconductor industry is seeing signs of stabilization. It feels like the
New approaches needed to enhance worst is behind us. We are currently in the early stages of a semicon-
collaborative efforts ductor cycle characterized by rising technical complexity, and particu-
Looking ahead to 2010 from where the industry larly for KLA-Tencor, a cycle riddled with increasingly challenging yield
is today, the semiconductor market has clearly issues for chipmakers—which will ultimately drive higher adoption of
entered a growth phase; what remains to be process control solutions. To benefit from this growth, KLA-Tencor
seen is its rate and duration, although current intends to continue its heavy investment in R&D.
capex forecasts suggest rapid acceleration. Today, we’re seeing primarily technology buy orders that are
Given the depth and duration of the down cycle focused on design rule conversions and advanced development,
and its impact to the financial health of our driven by new consumer products. We are also seeing some mild
industry, it would seem some changes in the Larry Dulmage, VP, capacity investment. Among our customer base, foundry has once
industry’s business model could help mitigate Corporate Marketing, again been very strong, supplying the majority of new orders over
the costs of all that lies before us. Crossing Automation, the past few quarters. As foundries accelerate their technology
In the next two years, the industry is Mountain View, CA USA investments, they’re investing in process control to speed their yield
looking at ramping capacity by 40% or more while developing the learning in production—ensuring qualification of next-generation
new technologies for 22nm manufacturing that will be required to technologies.
sustain Moore’s Law, and at the same time, pursuing the 450mm We’re also seeing technology buys in the memory market—
transition while driving cost reduction. Unless equipment suppliers primarily DRAM—and over the coming months, we’re seeing overall
and manufacturers find ways to share development costs, accom- memory order levels on the upswing as general memory industry
plishing all of this will further stress the financial stability of the health continues to improve, and competitive forces push market
industry. And yet, this issue remains one of the more contentious players to accelerate investment in the leading edge to drive down
and difficult concepts to resolve. costs. While NAND investment continues to remain light, we expect
On the bright side, the IDM community is embracing JVs, JDAs higher levels overall of investment from memory in the first half
and consortia while retaining its competitive edge. We see this as an of 2010 as memory capex budgets were suppressed in 2009 below
opportunity for IDMs to work much more closely with the process sustainable levels.
equipment industry. But such joint development efforts alone will not For industry leaders to remain financially and competitively
achieve critical improvements ,such as shorter development times, strong over the next four quarters, investment in innovation must
reduced inventories, and tool configuration flexibility. remain a top priority. I look forward with excited curiosity to what
The full impact of new approaches to subsystems, modules, and lies ahead in 2010, and to the new triumphs—and challenges—the
common control platforms for wafer-level automation can deliver semiconductor industry may face.
value-add to OEMs and device manufacturers alike. One novel continued on page 18
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A N A LYS T O U T L O O K
For 2010, marketplace

optimism abounds
ooming. Recovery. Upturn. Choose your favorite Bob Johnson and Klaus Rinnen add, “we are also hearing
optimistic word, and that is what many analysts surveyed rumblings about possible shortages and short term allocations
by Solid State Technology are using to describe the of some parts as the industry recovers from one of the most
semiconductor market outlook for 2010. “The forecast violent down cycles in its history. As for the longer term, the
tea leaves have rarely looked better,” says Malcolm Penn of key question for the coming decade still is how to prosper in a
UK-based Future Horizons. slowing growth environment.”
A world economy seemingly on the rebound, low inventories, For the next 12 months, however, Jim Feldhan, president of
and maximized fab capacities are among the reasons analysts Semico Research, points to continued consumer enthusiasm for
are upbeat. In addition, new products and leading edge technol- cutting edge handheld and wireless devices (and the memory
ogies are likely to help fuel the rebound, analysts say, including and logic required to run them) as a significant indicator of a
production at 32nm for logic devices and NAND Flash memory market rebound from 2009.
getting up to speed, and increasing 4Xnm process DRAM “The recovery is real,” sums Feldhan. “Although consumers
production. may not spend as much during the holiday season, electronic
But tempering the enthusiasm are uncertainties concerning devices are defi nitely on the gift list. In 2010, we’ll be entering
unemployment, consumer spending, and some economic the year with high capacity utilization rates and an economy
prognosticators’ belief that a second dip in the market will that is starting to expand.”
occur before a long-term recovery takes hold. Gartner analysts Here’s more of what analysts are saying for the year ahead:
Back to normal abnormality

his time last year the market was in freefall, the closures and a two-year capex famine. 2009’s capex
victim of a collapsing world economy. As a result, (2010’s capacity) ran barely US$1 billion per month,
Q4-2008 sales sequentially fell an unprecedented or only 5% of sales. While the number stabilized
24% followed by a further 16% fall in Q1-2009. in the second half of the year, capacity is already
With Q1-2009 now 30% down on the previous year, little getting tight and will only get tighter; already, the
wonder our forecast called for a 28% overall decline. foundries are starting to talk allocation.
Then came Q2 and an equally dramatic bounce back, The foundries’ profitability is also at an all-time
up 17% on Q1-2009 versus the zero to small single digit Malcolm Penn, chair- low, at a time when they are being asked to carry
growth norm. Clearly, the market was responding to a man & CEO, Future Hori- an ever-increasing share of the wafer-processing
cut back too far, and this data point alone was enough zons, Kent, UK burden. This is economically unsustainable,
to drive the forecast up 14% points to only –14%—still bad but especially with allocations; 2010 foundry wafer prices will rise,
euphorically better than the –28% abyss. putting an even greater pressure on IC ASPs.
Turning to 2010, the forecast tea leaves have rarely looked We, therefore, have the inverse of the 2001 perfect storm: a
better. First, the world economy is recovering, with all econo- strengthening world economy, robust unit growth, little excess
mists forecasting low positive 2010 GDP growth. And with inventory, tight wafer fab capacity, continuing low levels of
inventories still low, new units must be built, which means we capex spending, and increasing ASPs. Even benign quarterly
should see a reasonably strong SC unit demand. ASPs are also growth patterns of ±2 (for two quarters), followed by +12 and
on the upturn, despite the recession, mostly due to structural +3, yields a year-on-year growth of +19%. If allocation kicks
and mix effects but also to memory price increases. in, this could go a lot, lot higher. Watch out for 2010-11 to be a
Finally, fab capacity is starting to look tight, squeezed by fab re-run of 1993-95.
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New growth and opportunity After the global recession,

for the semiconductor industry a booming market on the horizon
2 I
010 will be a good year for the semicon- n 2009, a global GDP decline of -0.8% marked the worst global
ductor industry. Semiconductor recession since 1946. In 2010, global GDP growth is expected
revenue will see double-digit growth to rebound to 3.4%, just 0.2 percentage
levels for the first time in years, as the points under the long-term average GDP
recovery in the end user markets gains steam, growth rate of 3.6%. In 2009, worldwide
driven by a return to growth in global markets. electronic system sales decreased 10%, only
All levels of the supply chain will benefit, from the third annual decline in history. Directly
increased materials purchases to a revival Bob Johnson, VP Re- impacted by the economic recovery, total
of capital investment for capacity and new search, Gartner, San Jose, 2010 worldwide electronic system sales are
technology. CA USA forecast to register an 8% increase.
Yet, despite the good news, there are concerns about the While global recessions are certainly Bill McClean, President,
strength of the recovery. Unemployment still stands at histori- traumatic for many people and businesses IC Insights, Scottsdale,
cally high levels, and will likely continue that way for some time. throughout the world, they typically have set AZ USA
Consumer spending is once again driving market growth, but the stage for a booming semiconductor market. Over the past 30
consumer confidence is shaky at best, and industrial buying has years, the world has endured four global recessions, and after every
not yet recovered to a large degree. Only time will tell whether one of these recessions, a booming semiconductor market immedi-
we will see a second downward leg in industry growth before a ately followed! Moreover, the strong semiconductor market that
long-term sustainable recovery sets in. followed the global recession has always lasted at least two years.
As in past recoveries, this one will also D r i ve n by
be driven by new products and leading edge relatively low oil
technology. Production at 32nm will begin in In the aftermath of the 2008- prices, record low
earnest in 2010 for logic devices and NAND 2009 global recession, the worldwide interest
Flash memory; and in DRAM, companies are 2010 IC market will grow rates, and economic
racing to reach production in the 4Xnm process stimulus packages
realm. Most current capital investments are for 15%, followed by even from the U.S., China,
technology upgrades, with little new capacity stronger growth in 2011. Europe, Japan, and
Klaus Rinnen, coming on line for the near future; however, other countries that
Managing VP, Gartner, lead times for critical equipment types are total more than $2.0
Washougal, WA USA pushing out availability and may put a short- trillion (with 60% of the stimulus expected to be spent in 2010), the
term damper on technology improvement projects. We are also worldwide economy and semiconductor markets in 2010 are forecast
hearing rumblings about possible shortages and short-term alloca- to show a strong rebound from the poor performance exhibited in
tions of some parts as late 2008 and the first half of 2009.
the industry recovers In the aftermath of the 2008-2009 global recession, IC Insights
from one of the most As in past recoveries, this forecasts that the 2010 IC market will grow 15%, followed by even
violent down cycles stronger growth in 2011. Worldwide IC unit volume shipments
in its history. one will also be driven by are forecast to increase 15% in 2010, up significantly from an 8%
So, 2010 will see new products and leading decline in 2009.
excitement return edge technology. After falling 37% in 2009, worldwide semiconductor industry
to the industry as capital spending is forecast to increase 18% in 2010; however, as a
it grapples with direct result of the steep capital spending declines in 2008 and 2009,
the problems of the capital spending as a percent of sales ratio reached an all-time
handling a return to double-digit growth and the introduction of low of only 12% in 2009. Even with a moderate rebound in spending
new technology into the marketplace. in 2010, IC Insights believes that there are likely to be major conse-
But even two years of double-digit growth will only get us back quences (e.g., surging IC average selling prices, capacity shortages,
to where we were before the recession hit hard. As for the longer etc.) from the 2008-2009 capital spending collapse.
term, the key question for the coming decade still is how to prosper Given the world’s almost insatiable demand for ICs, it is only
in a slowing growth environment. Gartner believes the industry will a matter of time before the impact is felt in the way of longer lead
respond to this long-term challenge with significant changes in its times, spot shortages, and higher average selling prices for many
underlying dynamics, competitive landscape, and business models IC devices.
and practices.
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Analyst Outlook continued from page 15
It’s upturn time again
A
bout the best thing that can be said about 2009 is that expected to rise 4%. Overall memory bit growth
it’s nearly over. The meltdown that reached a head with is still very positive.
the stock market collapse of October 2008 dragged Memory prices, a leading indicator for the rest of
semiconductors down just when the 2008 overcapacity the semiconductor market, have been flat for most
should have been burned off. Although a typical semicon- of this year after plunging nearly 40% from the third
ductor cycle would have driven growth in 2009, softening to fourth quarters of last year. As a general rule, flat
demand extended the market’s malaise. Objective Analysis memory prices set the stage for important revenue
sees the year ending about 19% below 2008, with revenues of growth in the following year. If demand continues
about $205 billion. Jim Handy, Analyst, Ob- (depending on the world economic picture), then
jective Analysis, Los Gatos,
What does 2010 hold in store? From a global economic bit growth will maintain its current level, if not
CA USA
standpoint, things are still very fuzzy—many economists and strengthen. Flat prices cause revenue growth to
armchair pundits are calling for a second dip in the recession. We match bit growth. With modest bit growth projections for 2010 of
don’t know about that, and soft demand makes it tough to forecast 75% for NAND and 40% for DRAM, we should expect combined
with confidence, but if the market plays out the way that semicon- memory revenue growth of about 55%.
ductors have for the past four decades (and the past nine cycles), then In past cycles, semiconductor growth is about two-thirds
2010 should be a very good year indeed. that of memories. Assuming 2010 follows this trend, we should
So far, demand has not been as significantly impacted as many anticipate overall semiconductor growth of 35% or better. I am
anticipated. True, cell phone unit shipments are down by 10% sure that the many hurting vendors and unemployed semicon-
and PC units are expected to decline by 2%, but there is strength ductor professionals will join Objective Analysis in saying: “It’s
in other sectors. Feature phone sales are up. Set-top box sales are about time!”
Yes, Virginia, the recovery is real
T
he economy hit an upswing in March 2009, which is the exact positive for the last five months aft er being negative for the
month Semico Research predicted sales prior 12 months.
would begin to increase. Much of the On the memory front, NAND prices have been on an
global news across different industries upswing since November 2008. Th is recovery has been driven
is still negative, with foreclosures and poor by reduced capacity expansion, restocking the supply chain, and
consumer credit continuing to dominate the consumer spending on electronics. Average prices for NAND
headlines. Unemployment remains high but bottomed in 2008 at $2.75, and by August 2009 had reached
employment is always a lagging indicator. $3.80. The rebound in NAND has been so strong that revenues
Semico believes the recession ended in third in 2009 will be flat or slightly positive compared to 2008. In
quarter 2009. Even with the weak economy, Jim Feldhan, President, 2010, NAND revenues will grow 21% to $14.5 billion.
Semico Research, Phoenix,
there is some good growth in markets directly 2009 is the year when DDR3 DRAMs came into their own.
AZ USA
related to semiconductors. DRAM prices have been on the rise since December 2008,
On the consumer side, e-readers are growing from $1.20 to $1.57 by August
gaining more and more popularity, as 2009. DRAM revenues will be down 27% in
well as smaller HDTVs and netbooks. Devices that find sockets in 2009, followed by a recovery of 15% in 2010.
With Apple and Microsoft both releasing Some of the MOS logic categories actually
updated versions of their MP3 players, the
wireless, handheld, and other saw double-digit growth in 2009 and will
small dollar consumer market is headed consumer products, such as continue that trend in 2010. Devices that
into a strong fourth quarter, and 2010 is HDTVs, are showing strong fi nd sockets in wireless, handheld, and
looking up. other consumer products, such as HDTVs,
Semico forecasts total worldwide
growth trends...In 2010, we’ll are showing strong growth trends.
semiconductor revenue to decline 12.5% be entering the year with high In conclusion, the recovery is real.
to $217.5 billion in 2009. But the recovery capacity utilization rates. Although consumers may not spend
will be in full swing in 2010 when the as much during the holiday season,
industry will experience a revenue growth electronic devices are definitely on the
of 18% to $262.7 billion. gift list. In 2010, we’ll be entering the
The PCB book-to-bill ratio points to improved markets in year with high capacity utilization rates and an economy that
the coming months. The combined book-to-bill ratio has been is starting to expand.
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Analyst Outlook continued from page 16 All-wet stripping process continued from page 11
HDDs will boom in 2010 process cell configuration (two ashers + one wet bench), this all-wet
process cell also reduces the required cleanroom space for a given
ate in 2008, as banks were faltering throughput requirement. A ratio of throughput rate per unit space
and the stock market was melting is used to demonstrate the difference in Fig. 4. The all-wet process
down, the economic storm clouds cell has a ratio of 26.98 compared to the baseline process cell ratio
were seemingly so dark that any of 7.26. By this criterion, the all-wet process cell shows >300%
silver lining seemed impossible. However, increase in cleanroom space utilization.
consumers proved resilient in 2009. PC
prices fell to unprecedented levels, thanks Conclusion
in no small part to the emergence of the An all-wet photoresist removal process has been developed that reduces
low-cost “netbook.” And the cost-effec- Mark Geenen, Trend- the number of process steps and eliminates the potential for plasma-
tiveness of HDDs snuffed out SSD’s initial FOCUS, Los Altos, CA USA induced substrate damage, while also minimizing substrate material
foray into mobile computing. While SSDs are evolving and are loss. As demonstrated in the process qualification experiment detailed
finding a place at the table, HDDs are still the storage medium of in this article, this stripping methodology delivers equivalent defect
choice for servers, PCs, and a host of consumer electronics devices. control and comparable yield control (>99.9%) when compared with
The netbook has proven to be a catalyst for a restructuring and the current manufacturing baseline process (plasma ashing followed by
repricing of the mobile PC market. For $300 or less, a full-function wet clean). In addition, the all-wet process demonstrates the capability
PC can be secured that will fit the needs of most consumers or to reduce the ion implantation cycle time by >60%, while delivering a
businesses. Now, the average price of notebook PCs is in the >300% improvement in cleanroom space utilization. ■
$600-$700 area—roughly half of where it was just two years ago.
More and more buyers are opting for mobility, so the notebook PC References
market is rapidly expanding. Interestingly, HDDs will continue to 1. K. K. Christenson, J. W. Butterbaugh, T. J. Wagener, N. Pyo Lee, B. Schwab,
M. Fussy, J. Diedrick, Solid State Phenomena, 134, p. 109 (2008).
dominate, despite all of the articles and blogs that have declared 2. B. K. Kirkpatrick, J. J. Chambers, S. L. Prins, D. J. Riley, W. Xiong, X. Wang,
SSDs as “HDD killers.” Well under 5% of all notebook PCs will Solid State Phenomena, 145, p. 245 (2009).
employ SSDs in 2010, and until prices and capacities improve, 3. U.S. Patent 007003430, “Method and System for Processing Stability of Semi-
conductor Devices,” SMIC, (2006).
HDDs will reign supreme.
External HDDs continue to offer unprecedented value. Biographies
Whether it’s for data backup or just more storage, users are taking Ron Nan received his BS in automation from Shanghai U., and
advantage of attractive pricing to purchase hundreds of gigabytes MS in microelectronics from Fudan U., and is process section
of capacity, often for less than $100. Capacities are now at 2 TB for manager at SMIC F-8 18, Zhangjiang Rd. Pudong New Area,
3.5” externals, and 1 TB for 2.5” mobile externals. Shanghai 201210, P.R.C; ph.: +86-2138610000 ext 18213; Danny_
Digital video recorders (DVRs), IPTVs, and the like continue Rong@smics.com.
to enjoy broadening appeal around the world. With tens of
Freda Li received her MS in materials science and BS in materi-
millions installed and demand on the rise, HDDs have another
als science from Sichuan U., and is a process engineer wet clean
avenue of growth. High-definition recording is boosting HDD
and CMP at SMIC.
capacities in DVRs, proving once again that users cannot have
enough storage. As digitization of content pervades, HDDs will Jey Jey Hung received his ME in chemical engineering from Tai-
be the cost-effective king of mass storage. wan U., and is an assistant director at SMIC.
Technology developments will pave the way for James M.M. Chu received his MS in system engineering from
multiple-terabyte mobile HDDs within two years. New National Cheng Kung U., Taiwan, and is currently a PhD can-
technologies, such as discrete track recording or bit didate at the university; he is a field application manager at FSI
patterning, promise to push HDD capacities higher. International, Hsinchu, Taiwan R.O.C.
Of course, SSDs are finding homes in enterprise applications that
need higher throughputs, and in specific portable computing appli- Jack Yuan received his BS degree in chemistry science from
cations. Performance and durability concerns are being addressed, Lanzhou U. and Masters in material science from Shanghai
although cost and capacity are far from allowing SSDs to compete U., and is an application engineer at FSI International, Hsinchu,
with HDDs across the storage spectrum. Taiwan R.O.C.
With a stabilizing global economy, Windows 7, and a long- David Yang received his MS in atomospheric physics from
overdue PC upgrade cycle on the horizon, data storage require- National U., Taiwan, and is a senior application engineer at FSI
ments will continue to grow in 2010. PC shipment growth will International, Hsinchu, Taiwan R.O.C.
approach double digits this year, and most of that expansion will
be served by HDDs. Maybe we’ll see a long-promised combi- Jeffery W. Butterbaugh received his PhD in chemical engi-
nation of HDD and SSD technology that offers the best of both neering from MIT, and is chief technologist at FSI International,
worlds—perhaps as early as 2010. Chaska, MN USA.
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Technical Forecast continued from page 13
Mobile communications technology and the manufacturing processes that are even more pure and defect-free,
environment to drive growth in 2010 which involves controlling increasingly subtle and costly contami-
At Edwards, we are seeing positive signs of economic rebound. We nation sources. The use of new materials and chemistries, combined
are forecasting orders to increase by 30-40% in our sector of the with implementation costs, makes controlling contamination a
semiconductor market in 2010. We expect the primary drivers to challenge, but well worth the investment. Minimizing airborne
be technology upgrades and new capacity orders. One of the key molecular contamination (AMC) and controlling volatile organic
applications fueling this growth will be mobile compounds in critical areas of the fab, and in microenvironments
communications and netbooks, where demand that house wafers and reticles, can reduce on-wafer defects and lower
for improved display technology will require expensive production tool maintenance costs.
expanded capacity in LED and FPD manufac- This illustrates an interesting paradox that is emerging. As our
turing. A growing demand for Ethernet industry redefines its roadmap and recalibrates its spending on
connectivity in the home will be another key next-generation process technology development, we need more
technology driver. We also expect to see an innovation, not less. We need to find new solutions that improve
Nigel Hunton, CEO, upturn in our service business as fab utili- productivity and yield, while lowering the total cost of ownership.
Edwards, Crawley, West zation increases in the coming year. Once this mindset is fully incorporated into the semiconductor
Sussex, UK Environmental concerns will spur demand industry, those questions that we are asking may become much
for our products, due to the growing need to control greenhouse gas easier to address.
emissions. Fuel burners can be optimized for complete abatement
of offensive gasses with minimum fuel consumption, providing the Secondary equipment market
dual benefit of efficient abatement and reduced carbon footprint. As a enables financial viability
result, we expect to see significant demand for our abatement systems, Economic recovery? The stock market appears
with growth in that sector outstripping that of our vacuum products. to have bounced back, but we won’t have a true
We see much of this growth coming from our customers in Asia. sustainable recovery until we have a sustained
Concerns about global warming and sustainable manufacturing recovery in the job market. After all, consumers
have led us to take a careful look at the environmental impact of our are funded by jobs and a lack of jobs means a
products. In fact, Edwards has developed and published specific goals lack of consumer funds and thus diminished
for the coming year to minimize the effects our tools and manufac- consumer spending. Regardless of political
turing processes have on the environment. Since vacuum subsystems affiliation, this should be the main focus of any Tim Tobin, CEO, En-
account for as much as 50% of the power used by many process tools, purported economic stimulus efforts. trepix, Tempe, AZ USA
reducing their water usage and power consumption not only helps the Circa 2005, the consumer became our industry’s main end user,
environment, but also lowers the cost of ownership of our products, accounting for over 50% of all semiconductor sales. The economics
providing a direct economic benefit to our customers. of such a mature semiconductor industry were redefined by the
Our position as an independent company has helped us to weather 2007 ITRS roadmap. Naturally, the secondary equipment market
the recent downturn by enabling us to be more responsive to the plays a key and central focal point enabling financial viability. This
demands of the market. We believe this approach will enable us secondary market imperative is verified by looking at the operations
to anticipate and react proactively to the challenges of a changing of several larger OEMs who now have groups or divisions dedicated
market in the coming year and into the future. to supporting their pre-owned equipment. It was further emphasized
by SEMI’s July 2009 launch of the Secondary Equipment Services
Innovation in 2010: full speed ahead and Technology Group (SESTG), a special interest group targeted at
The signs of recovery in the semiconductor formally developing, enhancing and promoting the unique require-
industry are encouraging, but there are ments of this market space.
several questions behind these signs. What A large but highly fragmented supply chain of smaller third parties
will this industry look like when the global has developed to support device manufacturers’ needs beyond the
economy recovers? Can the industry return capability of the OEMs due to both OEM resource limitations and
to its historical levels of spending? And if so, a large base of very small companies with special needs. Much the
what will drive that spending? same as the IDMs and the OEMs themselves, a key point to the
These certainly aren’t new questions, and Gideon Argov, Presi- evolution and maturation of this secondary market space will be
even though significant capacity expansion dent & CEO, Entegris, Bil- consolidation of third-party providers to achieve critical mass and
in the industry has slowed, the drive for next- lerica, MA USA provide a stronger value proposition for the customer.
generation technologies has not. With 32nm production upon us A successful consolidation effort will result in several larger
and 22nm on the doorstep, realizing the full technical and market third parties who provide OEM-like support, particularly for the
potential of these technology generations requires breakthrough higher value-add manufacturing processes. These large third-party
solutions in a number of areas. providers must have a global presence and be able to support all facets
One area that continues to receive critical evaluation is creating continued on page 20
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of IDMs requirements, including refurbished equipment, spare parts, we increased our investments in Asia, where
field service, training, process development, as well as hardware and the majority of our system sales are occurring.
software upgrades. By doing this, these providers will be able to offer I believe we are now well positioned to improve
manufacturers improved technical performance and long-term our financial performance and gain share, as
platform viability while significantly increasing their ROI. the cycle swings into positive territory again.
There are credible indications that
New technology will lead emergence a strong recovery has now begun. For
from the downturn in 2010 instance, major manufacturers are reporting Don Mitchell, Chair-
While 2009 was clearly a down year for the very positive results and offering encour- man and CEO, FSI Inter-
semiconductor industry, we saw continuing aging guidance for the future. We remain national, Inc., Chaska,
activity in research and development as cautiously optimistic that the recovery will MN USA
major manufacturers strove to prepare for the accelerate into 2010.
anticipated recovery. Collaborative research Our sales through this difficult period have been driven primarily
at organizations such as SEMATECH, Leti, by “technology buys” of our advanced new products as our customers
Albany NanoTech, and others, has continued have sought to take advantage of the slowdown to develop new
to push the technological envelope, and Rudy Kellner, VP and processes and implement new technologies. We have seen significant
advanced analytical instrumentation will GM, Electronics Division, interest in FSI’s ViPR technology—a high temperature wet chemical
FEI, Hillsboro,
certainly play a critical role in bringing these method, capable of removing difficult films, such as highly implanted
OR USA
innovations into production. photo resist in 300mm FEOL processes, which, by eliminating the
The semiconductor industry and its equipment suppliers have need for plasma ashing, reduce unwanted material loss, cycle time,
recently seen increased order activity, and it remains to be seen how and capital expenditures. In BEOL applications, these same technol-
sustainable the recovery will be. We do know that the industry will ogies can strip unreacted metal in nickel platinum salicide processes
continue to innovate and drive to new generations of devices and the that use low annealing temperatures. The process is already well
tools that are used to develop and produce them. Growing demand established on batch spray platforms and we expect to see similar
for the advanced analytical instrumentation that we supply will be acceptance on single wafer platforms as that they continue to gain
driven by the move to 32 and 22nm technology nodes, the imple- ground in advanced processes.
mentation of new device designs and 3D chip architectures, such as Also on single wafer platforms, we are seeing significant
FinFETs and TSVs, and the increasing complexity of the materials interest in the unique benefits of closed chamber, low oxygen
being used. environments for critical BEOL interconnect cleaning. We expect
The increased resolution required by the shrinking size and to see substantial growth in the single wafer cleaning segment.
growing complexity of semiconductor devices will accelerate the
transition from scanning electron microscopy (SEM) to scanning/ Reduced cost per die will drive end user choices
transmission electron microscope (S/TEM) systems; however, the The last 18 months have been the toughest on record for the semicon-
move from SEM to S/TEM is not just a resolution game. Most impor- ductor industry, and extremely frustrating for equipment providers. It
tantly, it is about enabling manufacturers to get the data they need was tough because the familiar industry downturn cycle was coupled
faster, easier, and at a more affordable cost per sample. FEI is investing with the worst global economic crisis in living memory, giving rise
heavily in products that help to support this transition. to, quite simply, mayhem. Almost everywhere, things were bad and
Ultimately, we expect the semiconductor industry to emerge from seemed to be getting worse—including major companies closing and
this downturn, although it will probably have a narrower base of supply chains in disarray. It has also been an
participants with the wherewithal to make the required investments incredibly challenging time because it seemed
in research and fabrication facilities. We look forward to continuing that sales forecasts kept moving further out.
to meet the imaging and analytical needs of this vital and innovative Customers wanted to place orders, but would
industry, as it moves ahead into a promising and exciting future. simply not release their budgets. In most
instances, business wasn’t lost, but timing was
Looking for gains as the recovery solidifies delayed and unpredictable.
Our industry has recently suffered one of the most serious downturns How could anybody survive such turmoil?
in its history, the result of the industry’s own cyclical nature Adrian Kiermasz, With fewer orders than we would have
compounded by a deep general economic recession. Worldwide President & CEO, Metryx, liked, a dedicated staff and some difficult
average monthly spending for the equipment we produce dropped Bristol, UK management decisions —common trends seen
by 91% from the 2007 peak to the early 2009 trough. For FSI, our across the industry—we are now seeing signs of the next upturn
bookings dropped 75% during the same period—less than the and anticipating an extremely strong 2010. Customers who delayed
industry because of new products and some increasing market share purchases have started buying, and interest is very high for products
in Asia. Still, we have aggressively cut costs and realigned our infra- that enable chip manufacturers to realize reduced cost-per-die.
structure. We consolidated our European and US operations, and We expect that sales across the industry in 2010 will be for high
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ROI solutions, and those with the ability Innovations such as new compression the recession. Substantive revenue gains
to offer risk management of process molding compounds that we have developed for handsets will be largely dependent on
performance, particularly on product over the past few years, are now finding appli- replacement cycles, population expansion,
wafers, reducing the significant cost of cation in 8-inch and 12-inch wafer-level redis- and affordability among people in emerging
test wafers. tribution technology. A new portfolio of film economies. Photovoltaics enjoyed substantial
Downturns are a fact of life in the die attach products has also been introduced progress in 2008, but 2009 has been a
semiconductor industry. When you’re in a to support improved package reliability, ease different story. This is expected to change
downturn, it’s always difficult to see when it of use, and better throughput. in 2010 as production will increase, albeit at
will end and when you’re not in a downturn, Anticipating the need for thinner lower per-module prices.
predictions are that the good times will bondlines of 5μm and less, lower total Throughout the downturn, DEK
continue forever. Predictions are often wrong, package cost, and throughput increases, carefully balanced cost structure reduc-
of course. Therefore, we are still vigilant next-generation die attach technology— tions with the safeguarding of value-
and mindful that although signs look very such as wafer backside coating (WBC)—is driven customer activities, ensuring that
encouraging, we are still in the very early also in development to meet the require- our long-term strategic technology initia-
stages of recovery. ments of advanced die stacking applica- tives were not adversely impacted. While
tions not conducive to traditional die DEK has adjusted accordingly for the
Disruptive packaging technology attach fi lm processes. Products for robust challenging year behind us, we have not
will drive the recovery in 2010 photovoltaic production have also been done so at the expense of innovation and
Recent statistics regarding inventory levels central to our innovation efforts and R&D investment. Because we continued
and corporate earnings suggest that the long-term strategy. to invest in R&D, we will launch several
semiconductor packaging market appears We believe the recovery is underway and new products and are, therefore, prepared
to be recovering from the Q4 2008–Q1 2009 we’re looking forward to a year filled with for moderate gains in the semiconductor
low point much faster than many industry exciting technology progress! continued on page 23
experts had anticipated. Though the improve-
ments seem to be occurring in a wide range of Established markets to be most
markets and applications, recovery in some robust through recovery
segments is following The consensus among industry analysts
a faster curve which, and DEK’s Dover Electronics group
in part, may be attrib- colleagues is that, while all market sectors
utable to innovation and all geographies declined sharply in
initiatives. 2009, there is no doubt that recovery has
Last year, in- begun and will continue into 2010 and
novation focus in the beyond. In fact, we believe that the global
Michael Todd, VP of packaging industry electronics industry should rebound and
Product Development & was driven by cost. develop according to
Engineering, Henkel Cor- Th is year, however, its long-term average
poration, Irvine, CA USA disruptive packaging growth trend lines.
advances are likely to lead the headlines. While there will
New package innovation is arguably back no doubt be new
on track and we, as a materials developer, technology intro-
are now being pushed harder for enabling ductions, the markets
products that we have been developing that were strongest
over the last 12–24 months. Wafer-level prior to the downturn Michael Brianda, Presi-
packaging innovations, such as through will remain the most dent, DEK International,
Zürich, Switzerland
silicon vias (TSVs)—especially in the area of robust throughout
IC/memory integration—and an explosion the recovery.
of new developments in the area of multi-die Notebook growth has historically
and die integration technologies are moving been strong, but trends indicate a shift
the industry further and faster than we can toward low-cost netbooks and inexpensive
recall in recent years. laptops—a condition that will likely improve
During the downturn, we invested unit shipments but leaves revenue levels in
significant resource to deliver market-ready doubt. Likewise, the maturity of the handset
materials aligned with this renewed emphasis market is difficult to dispute, and this
on packaging technology development. segment was one of the hardest hit during
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PRODUC T NEWS
Trio of tools for CMP, anneal, energy monitoring
The Reflexion GT CMP platform targets copper inter-
connect planarization as well as tungsten applications for
Wafer inspector for LED, MEMS
4Xnm logic and memory. A dual-wafer architecture enables
The ICOS WI-2250 wafer
inspector offers defect
inspection of whole
and diced wafers up to
200mm, with macroin-
spection sensitivity in
the pre- and post-dice
inspection (front- and
backend) of high-
brightness LEDs and
two wafers to be processed simultaneously on each platen, MEMS manufacturing.
with the polishing heads independently controlled. A shield The system incorporates
around each platen works in concert with an exhaust system advanced rule-based binning for real-time defect classification, advanced
to handle misting/aerosols, etc. The company says pad life metrology capabilities, and faster throughput for inspection. KLA-Tencor
is doubled with up to 30% less slurry usage. Throughput Corp., Milpitas, CA; ph 408/875-3000, www.kla-tencor.com
is 80wph for a 30k logic or 120k memory WSPM scenario
(with 6kÅ incoming copper), the company claims.
The Vantage Astra system targets millisecond annealing facilitates patterning of dense, high-AR features. Using the new AHM films
required for creating nickel silicide (NiSi) transistor contact with the company’s Vector PECVD platform enables AHM removal within a
layers in 45nm and beyond logic. The dynamic surface 1mm transition zone, ensuring CD uniformity within 2mm from the wafer’s
annealing (DSA) system uses a compact diode-stack laser edge, and helps block moisture uptake. Novellus Systems Inc., San Jose, CA;
to scan across the wafer in a series of passes, heating the ph: 408/943-9700, e-mail: www.novellus.com
surface directly below the beam to a depth of 100μm; the
result is sub-millisecond exposure that allows for a very High-current implanter
high maximum peak temperature, enabling effective phase The Optima HDx high-dose implanter features enhancements to maximize beam
transformation or dopant activation. Possible combina- current, minimized beam setup time, and eliminate energy contamination. Spot
tions include two millisecond chambers, or a hybrid that beam technology and short beamline deliver drift beam currents up to 36mA.
combines a spike chamber and a millisecond chamber. A patented AutoTune beam tuning system accelerates both tune times and success
Throughput is claimed to be >40wph per two-chamber rates; a proprietary RadiusScan ensures across-wafer dose and angle process
system. The company says silicidation enables up to 5% uniformity as well as repeatability. Axcelis Technologies Inc., Beverly, MA;
greater device speeds and up to 15× lower leakage; the ph: 978/787-4000, www.axcelis.com
system is extendible to high-k/metal gate applications.
The iSYS platform aims to help semiconductor fabs 300mm full-wafer DRAM test
improve energy conservation and lower utility cost for The SmartMatrix 100 probe card for ≤5Xnm-node DDR2 and DDR3 DRAM
abatement and vacuum pumping on process tools by >20%. devices incorporates a new architecture leveraging the company’s MicroSpring
Installed in less than a day on a wafer processing tool, it MEMS contact technology, enabling pad pitches as small as 50μm and pad
senses real-time changes in the process chamber and directs sizes as small as 40×50μm. It quickly reaches test temperatures and enables
subsystems into predefined standby states. Built-in sensors dual-temperature operation, with scrub consistency even on smaller pads and
and software enable remote monitoring of cumulative pad pitches. The new design also “virtually eliminates” thermal bow effects
energy savings and tracking energy-sustainability progress. of traditional full-wafer-contact probe cards, the company says. A RapidSoak
Applied Materials Inc., Santa Clara, CA; ph: 408/727-5555, technology option enables reduced soak time. FormFactor Inc., Livermore, CA;
www.appliedmaterials.com ph: 925/290-4095, www.formfactor.com
MEMS product design platform

Ashable hardmask films for sub-32nm The MEMS+ environment offers a fully parameterized 3D design entry canvas
New ashable hard mask (AHM) plasma-enhanced chemical to assemble complete MEMS devices using elements such as beams, plates,
vapor deposition (PECVD) films for 32nm lithography electrostatic combs, etc. Schematic symbols are placed in an IC schematic, and
patterning have up to 25% greater etch selectivity and up to simulations are run in an analog mixed-signal simulator; the same model can
7% die yield improvements versus conventional amorphous be used for coupled MEMS and IC simulations. Results can be visualized back
carbon films, the company claims. Better within-wafer CDU in the 3D environment to verify mechanical behavior. Coventor Inc., Cary, NC;
ph: 919/854-7500, www.coventor.com
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market over the next five years, followed on developing market opportunities. As
by what we anticipate will be growth levels numerous companies are still investi-
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primarily driven by China. Solar cell a tremendous savings potential. These
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e-mail: kristinec@pennwell.com will slowly recover, mainly through an mance of DI-water. For example, almost
Regional Sales Manager increased demand for high end products all notable industry leaders (especially
West Coast US, Midwest, Western Canada
Lisa Zimmerer, 190 Cecil Place, Costa Mesa, CA 92627 by the military and the semiconductor chip manufacturers)
Tel: 949/515-0552; Fax: 949/515-0553;
e-mail: lisaz@pennwell.com medical segments. have switched to, or are current by transi-
Direct Mail Director Due to numerous
Bob Dromgoole, 98 Spit Brook Rd, Nashua, NH 03062-5737;
tioning to a chemistry “assisted“ cleaning
Tel: 603/891-9128; Fax: 603/891-9341;
e-mail: bobd@pennwell.com
consumer electronic process. Previously, they had been strict
Austria, Germany, Liechtenstein, Russia, innovations, we advocates of using DI-water only. Th is
N. Switzerland, Eastern Europe
Holger Gerisch, Hauptstrasse 16, predict to see the move comes as decreasing geometries
D-82402 Seeshaupt, Germany;
Tel: 49/8801-302430; Fax: 49/8801-913220; largest recover y and physical characteristics of DI-water
e-mail: holgerg@pennwell.com
France, Netherlands, Belgium, W. Switzerland,
within the Asian are not allowing for sufficient cleaning
Spain, Greece, Portugal manufacturing Dr. Harald Wack, Pres- under components. This trend coincides
Luis Matutano, Adecome+, 1, rue Jean Carasso, ident ZESTRON Worldwide
F-95870 Bezons, France market next year. with the emergence of pH-neutral
Tel: 33/1-30 76 55 43; Fax: 33/1-30 76 55 47;
e-mail: luism@pennwell.com The latter is complemented by a continued defluxing technologies intended to provide
Italy
Vittorio Rossi Prudente, Uniworld Marketing transfer of aerospace manufacturing to ultimate material compatibility while
Via Sorio, 47, 35141 Padova, Italy
Tel: 39/049-72-3548; Fax: 39/049-856-0792; Southeast Asia. meeting the most stringent environmental
e-mail: vrossiprudente@hotmail.com
In anticipation of significant growth requirements.
United Kingdom & Scandinavia
Tony Hill, PennWell Publishing UK Ltd., Warlies Park House, next year, ZESTRON has chosen to heavily We foresee that 2010 will hold a number
Horseshoe Hill, Hill, Upshire, Essex, U.K. EN9 3SR
Tel / Fax: 44-1442-239547 invest in personnel and its organization of tremendous innovations mainly
e-mail: tonyh@pennwell.com
Israel
within the Asian-Pacific region in 2009 designed to help manufacturers meet the
Dan Aronovic, Allstar Media Inc.,
3/1 Hatavas St., Kadima, 60920, Israel
and 2010. Two new technical centers are ever increasing demands of the electronics
Tel / Fax: 972/9-899-5813
e-mail: aronovic@actcom.co.il
in the planning phase to further focus assembly industry. ■
Japan
Manami Konishi, Masaki Mori, ICS Convention Design, Inc.,
Chiyoda Bldg., Sarugaku-cho 1-5-18,
Chiyoda-ku, Tokyo 101-8449, Japan
Tel: 3-3219-3641; Fax: 3-3219-3628;
e-mail: konishi-manami@ics-inc.co.jp
AD INDEX
mori-masaki@ics-inc.co.jp
Advertiser Pg Advertiser Pg
Korea
Mihye Kang, Electronic Sources Inc., 137-894 Jaeyeon Bldg. 3F, 261-1 Alcan Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 REC Silicon. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
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Tel: 82/2-2243-4658; Fax: 82/2-2249-4279;
e-mail: seminews@semiconnews.co.kr Levitronix. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Solid State Equipment Corp . . . . . . . . . . . . . . . . . . . . . . . . . . . . C2
Taiwan NUSIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Stanford Research Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . C4
Vicky Kung, Alice Chen, Arco InfoComm, 4F-1, #5, Sec. 1,
Pa-Te Rd., Taipei, Taiwan R.O.C. 100
Tel: 886/2-2396-5128; Fax: 886/2-2395-9571;
Plasmatic Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 VITECHNOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
e-mail: alicea@arco.com.tw
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Adonis Mak, ACT International, Room 1011, 10/F, New Kowloon Plaza, The Advertiser’s Index is published as a service. The publisher does not assume any liability for errors or omissions.
38 Tai Kok Tsui Road, Kowloon, Hong Kong
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I N D U S T RY F O R U M
Innovation on the interface

between disciplines
day, the world is waking up from on the interface between disciplines; i.e., between
one of the largest economic crises it nanoelectronics and biology, nanoelectronics and
has ever experienced. A large fraction mechanics, imaging, sensing and actuating, etc.
of the semiconductor industry is still Indeed, traditional players in the semiconductor
struggling to get out of the severe industry, who used to focus on their scaling activities,
downturn—one that is deeper than all are now widening their spectrum. They look for new
others that it has been through. Though opportunities in the beyond-CMOS domain.
the ongoing crisis has not had a significant delaying The semiconductor industry is positioning itself on
effect on the semiconductor roadmap, it has changed the plane of two complementary axes—the traditional
the landscape of the semiconductor industry. It has scaling or More Moore axis, where new materials are
Luc Van den hove,
also stimulated consolidation. Unfortunately, it has explored to further push the roadmap, and the More
IMEC, Leuven, also resulted in some players that have than Moore axis, where semiconductor
Belgium entered into Chapter 11 bankruptcy, or Companies that technologies are combined with other
even failed. technologies to develop innovative appli-
And not only small companies have continue to cations. As a leading innovator, IMEC
been impacted; all companies face this pioneers in research and development on
challenging environment. Economical invest in R&D the interface between More Moore and
management through cost reduction More than Moore. Combining expertise
and critical questioning of expenses is
during a period and technologies is rapidly becoming the
vital for everyone; companies, therefore, way to go to differentiate with creative
of economic
have delayed investments, defi ning prior- products. That’s why IMEC leverages its
ities and increasing efficiency. The most downturn will knowledge built up in 25 years of nanoelec-
obvious effect of the crisis is the steep tronics R&D into dedicated new strategic
decline of tool orders in the fi rst half thrive. research domains, such as bioelectronics,
of 2009, which resulted in empty order photovoltaics, imaging, sensing, actuating,
books of some equipment companies and a crash of energy harvesting, power electronics, etc.
the equipment industry. Financial indicators are currently rising, and
Companies that continue to invest in R&D during companies are returning to profit. But the question
a period of economic downturn will thrive—they is, how will 2010 look? Are the current positive figures
will be prepared for the future when the economy sustainable, or are they only a temporary revival?
revives. It is often observed that during recessions, There are hopeful signs for recovery, but the industry
companies distinguish themselves from the others fi nds itself in a fragile situation. Moreover, experts
through innovation. But this crisis is so deep that predict that the crisis will probably not immediately
many companies have also started saving on their come to a complete end in 2010.
R&D expenses, and are looking for alternatives to Due to this uncertainty, many companies will
their expensive, proprietary R&D via collaboration be very cautious in spending and companies will
in pre-competitive research. Outsourcing R&D in a invest carefully in new projects. Although 2010 will
cost-sharing way is an attractive solution for these be a challenging year, I am convinced that it may be
innovative companies who want to prepare for the thriving for innovative companies that look for new
future. By sharing costs and the risks of pre-compet- markets and continue investing in R&D to prepare
itive research, they are guaranteed a competitive for the future. ■
advantage in further product development.
The semiconductor roadmap is moving forward, Luc Van den hove is president and CEO of IMEC, Kapel-
and we are getting closer to the physical limits of dreef 75, 3001 Leuven, Belgium; ph.:+32 16 28 18 80; e-mail:
scaling. In the future, innovation will be created katrien.marent@imec.be
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Contents Zoom In Zoom Out For navigation instructions please click here Search Issue Next Page

Don’t miss an issue of Solid State Technology magazine and renew

Take a Closer Look...

Stanford Research Systems

Reducing process steps with

Executive forecast for 2010 p. 12

Marketplace optimism abounds p. 14

More Moore vs. More than Moore p. 24

ssec single wafer

High Velocity Spray Tri-Megasonic Scrub Double-sided PVA Brush

Strip & Lift-Off Immersion and Single Wafer Processing

Wet Etch Uniform, Selective Etching on Multiple Process Levels

Wafer Thinning Stream Etch for Films & Metals

Coat/Develop Photolithography Clusters

Spin Coating Hot Plate Bake Processing Low Impact Developing

solid state equipment corporation www.ssecusa.com

JA NUA RY 2 010 Vol. 53 • No. 1

The recovery has arrived! Tech News 8

14 For 2010, marketplace

2 Solid State Technology ■ January 2010 ■ www.solid-state.com

THE CELEBRITY OF SILANE (SiH4)

SILANE GASES | ELECTRONIC & SOLAR GRADE POLYSILICON

Solid State Technology ONLINE

the number of characters available PennWell Corporation, Solid State Technology

Hybrid CMOS-memristors, the future of analog

4 Solid State Technology ■ January 2010 ■ www.solid-state.com

Life after the “Reset” button

www.solid-state.com ■ January 2010 ■ Solid State Technology 5

Gartner: Chip capex recovery marches on

A final year-end boost to Gartner’s 2009 $B equipment spending will be availability

6 Solid State Technology ■ January 2010 ■ www.solid-state.com

The lifesaving microchip never failed thanks to a powerful

It’s part of our extensive line of low-outgassing materials

At NuSil, our scientists are dedicated to helping innovators

We want every product story to have a happy ending.

What? When? Where? If it’s NuSil, it’s no problem.

IMAPS 2009: Fusion bonding for 3D/TSV,

Getting greener: New fab EHS benchmark tool debuts

8 Solid State Technology ■ January 2010 ■ www.solid-state.com

All-wet stripping process for

10 Solid State Technology ■ January 2010 ■ www.solid-state.com

www.solid-state.com ■ January 2010 ■ Solid State Technology 11

TECHNIC AL FOREC AST

12 Solid State Technology ■ January 2010 ■ www.solid-state.com

• Navigating the Design IP Minefield

Register Online at _______________

www.solid-state.com ■ January 2010 ■ Solid State Technology 13

For 2010, marketplace

Back to normal abnormality

14 Solid State Technology ■ January 2010 ■ www.solid-state.com

New growth and opportunity After the global recession,

www.solid-state.com ■ January 2010 ■ Solid State Technology 15

Analyst Outlook continued from page 15

It’s upturn time again

Yes, Virginia, the recovery is real

16 Solid State Technology ■ January 2010 ■ www.solid-state.com

www.solid-state.com ■ January 2010 ■ Solid State Technology 17

Technical Forecast continued from page 13

18 Solid State Technology ■ January 2010 ■ www.solid-state.com

Alcan’s foil packaging with built-in desiccating agent

Reduce complexity. Eliminate waste. Add value.

Contact Bret Melton to Learn More:

Technical Forecast continued from page 18