COMSATS UNIVERSITY

ISLAMABAD

ELECTRICAL CIRCUIT ANALYSIS II

Lab Report

Name: Muhammad Mamoon Akber

Registration No.FA17-BEE-084

Section: BEE-3B

Report #4

Dated: Oct 08, 2018

Submitted to: Sir Ibtisam Aslam

Lab # 4: Verification of Network Theorems (KCL, KVL and Thevenin
theorem) in Phasor Domain.
Objective: Verification of Network Theorems (KCL, KVL and Thevenin theorem) in Phasor Domain.

Introduction:

Kirchhoff's Voltage Law: "The algebraic sum of all voltages in a loop must equal zero"

Kirchhoff's Current Law: “At any node (junction) in an electrical circuit, the sum of currents flowing
into that node is equal to the sum of currents flowing out of that node” or “The algebraic sum of current
in a network of conductors meeting at a point is zero.”

Thevenin theorem: Any combination of sinusoidal AC sources and impedances with two terminals can
be replaced by a single voltage source and a single series impedance z. 

Pre-Lab Task -1: Verify the Network Theorems (KCL, KVL and Thevenin theorem) of the following
circuit in Phasor Domain and find the Node voltages and voltages across the capacitors.
In Lab:

EQUIPMENT AND MATERIALS

1. Digital Oscilloscopes with Probes

2. Digital Multi-meter.
3. Digital Function Generator with Probes.
4. 2.2 uF Capacitor, 1uF capacitors, 100 ohmResistors

Task 1: (Verification of KCL and KVL)

1. Create the circuit as shown in Fig No.1.

Fig No.1 Circuit diagram for the lab experiment

2. Determine the magnitude and phase (i.e. Phasor Value) of all the node voltages from V1 to V6.
3. Fill in the table and blanks in the measurement section. Verify KCL and KVL using your results for
each node and each loop.

Figure 1 waveform of all the nodes

 Figure 2 show KCL and KVL circuit

Figure 3 voltage waveform at node 1

Figure 4 voltage waveform at node 2

Figure 5 voltage waveform at node 3

Figure 6 voltage waveform at node 4

Figure 7 voltage waveform at node 5

 Figure 8 voltage waveform at node 6

Task 2: (Verification of Thevenin Theorem)

1. For the circuit in Fig No.1 assume C3 to be the load capacitor.

2. Disconnect the capacitor C3 form the circuit and determine the magnitude and phase (i.e.
Phasor Value) of the open circuit voltage (i.e. V4).
3. Now replace C3 with a short circuit and determine the Phasor value of the short circuit current
i.e. the current through resistor R5. To determine this current determine the Voltage Phasor for
R% and divide it by the value of R5 to get the current through R5.
4. Calculate the Thevenin equivalent impedance using the formula
~
V
ZTH = ~ open circuit
I s h ort circuit

5. Determine the output voltage across the output capacitor C3 using the Thevenin equivalent

Fig No.2 Thevenin Equivalent Circuit

6. Compare it with the actual voltage across C3 measured in the previous task (i.e. V6).
7. If the results are the same Thevenin theorem is verified.

Post Lab: Verify the Network Theorems (KCL, KVL and Thevenin theorem) of the following circuit in
Phasor Domain using LTspice and find the Node voltages and voltages across the capacitors.
Task -1

(Fill the table with Phasor values (magnitude and phase) of the node voltages)

~ ~ ~ ~ ~ ~
V1 V2 V3 V4 V5 V6

~I ~ ~
R 1= (V ¿¿ 1¿−V 2 )/ R 1 ¿ ¿
= ___________________________

~I ~ ~
R 2 =(V ¿¿ 2¿− V 3 )/R 2 ¿ ¿
= ___________________________

~I ~ ~
R 3 =(V ¿¿ 2¿− V 4)/ R 3 ¿ ¿
= ___________________________

~I ~ ~
R 4 =(V ¿¿ 4 ¿− V 5 )/ R 4 ¿ ¿
= ___________________________

~I ~ ~
R 5 =(V ¿¿ 4¿− V 6 )/ R 5¿ ¿
= ___________________________

~ ~
I C 1= I R 2 = ___________________________

~ ~
I C 2= I R 4 = ___________________________

~ ~
I C 3= I R 5 = ___________________________

~ ~
V R 1 =(V ¿¿ 1¿−~
V 2 )¿ ¿ = ___________________________

~ ~
V R 2=(V ¿¿ 2¿−~
V 3 )¿¿ = ___________________________

~ ~
V R 3 =(V ¿¿ 2¿−~
V 4) ¿ ¿ = ___________________________

~ ~
V R 4=(V ¿¿ 4 ¿−~
V 5)¿ ¿ = ___________________________
~ ~
V R 5 =(V ¿¿ 4¿−~
V 6 ) ¿ ¿ = ___________________________

~ ~
V C 1=(V ¿ ¿3 ¿) ¿ ¿ = ___________________________

~ ~ = ___________________________
V C 2=(V ¿ ¿5 ¿) ¿ ¿

~ ~
V C 3=( V ¿¿ 6¿)¿ ¿ = ___________________________

Verification of KCL

Node V2:

The currents entering the node are: _______________________________________________

The currents leaving the node are: _________________________________________________

Sum of all currents entering: _________________________________________________

Sum of all currents leaving: ________________________________________________

Node V4:

The currents entering the node are: _______________________________________________

The currents leaving the node are: _________________________________________________

Sum of all currents entering: _________________________________________________

Sum of all currents leaving: ________________________________________________

Node V6:

The currents entering the node are: _______________________________________________

The currents leaving the node are: _________________________________________________

Sum of all currents entering: _________________________________________________

Sum of all currents leaving: ________________________________________________

Verification of KVL

Loop 1: V1->V2->V3->V1
The voltage rise in the loop: _______________________________________________

The voltage drops in the loop: _________________________________________________

Sum of all voltage rise: _________________________________________________

Sum of all voltage drops: ________________________________________________

Loop 2: V2->V4->V5->V3->V2

The voltage rise in the loop: _______________________________________________

The voltage drops in the loop: _________________________________________________

Sum of all voltage rise: _________________________________________________

Sum of all voltage drops: ________________________________________________

Loop 3: V4->V6->V5->V4

The voltage rise in the loop: _______________________________________________

The voltage drops in the loop: _________________________________________________

Sum of all voltage rise: _________________________________________________

Sum of all voltage drops: ________________________________________________

Loop 4: V1->V2->V4->V5->V1

The voltage rise in the loop: _______________________________________________

The voltage drops in the loop: _________________________________________________

Sum of all voltage rise: _________________________________________________

Sum of all voltage drops: ________________________________________________

Loop 5: V2->V4->V6->V3->V2

The voltage rise in the loop: _______________________________________________

The voltage drops in the loop: _________________________________________________

Sum of all voltage rise: _________________________________________________

Sum of all voltage drops: ________________________________________________

Loop 6: V1->V2->V4->V6->V1

The voltage rise in the loop: _______________________________________________

The voltage drops in the loop: _________________________________________________

Sum of all voltage rise: _________________________________________________

Sum of all voltage drops: _______________________________________________

Task 2

~
V oc =¿ ¿

~
I sc =¿ ¿

ZTH =¿ ¿

~
V out (using T h evenin equivalent )=¿ ¿

~
V out (as measured ∈Task 1)=¿ ¿

Critical Analysis: