Advanced Power MOSFET SFR/U2955

FEATURES
BVDSS = -60 V
Avalanche Rugged Technology
Rugged Gate Oxide Technology
RDS(on) = 0.3 Ω
Lower Input Capacitance ID = -7.6 A
Improved Gate Charge
Extended Safe Operating Area
D-PAK I-PAK
Lower Leakage Current : 10 µA (Max.) @ VDS = -60V
Lower RDS(ON) : 0.22 Ω (Typ.) 2

1
1
2
3 3

1. Gate 2. Drain 3. Source

Absolute Maximum Ratings
Symbol Characteristic Value Units
VDSS Drain-to-Source Voltage -60 V
o
Continuous Drain Current (TC=25 C) -7.6
ID o A
Continuous Drain Current (TC=100 C) -5.4
IDM Drain Current-Pulsed 30 A
VGS Gate-to-Source Voltage O1 +
_ 20 V
EAS Single Pulsed Avalanche Energy O2 99 mJ
IAR Avalanche Current O1 -7.6 A
EAR Repetitive Avalanche Energy O1 3.2 mJ
dv/dt Peak Diode Recovery dv/dt O3 -5.5 V/ns
o
Total Power Dissipation (TA=25 C) * 2.5 W
o
PD Total Power Dissipation (TC=25 C) 32 W
o
Linear Derating Factor 0.26 W/ C
Operating Junction and
TJ , TSTG - 55 to +150
Storage Temperature Range
o
C
Maximum Lead Temp. for Soldering
TL 300
Purposes, 1/8” from case for 5-seconds

Thermal Resistance
Symbol Characteristic Typ. Max. Units
RθJC Junction-to-Case -- 3.91
o
RθJA Junction-to-Ambient * -- 50 C/W
RθJA Junction-to-Ambient -- 110
* When mounted on the minimum pad size recommended (PCB Mount).
Rev. B

©1999 Fairchild Semiconductor Corporation

 P-CHANNEL
SFR/U2955 POWER MOSFET

Electrical Characteristics (TC=25oC unless otherwise specified)

Symbol Characteristic Min. Typ. Max. Units Test Condition
BVDSS Drain-Source Breakdown Voltage -60 -- -- V VGS=0V,ID=-250µA
∆BV/∆TJ Breakdown Voltage Temp. Coeff. -- -0.04 --
o
V/ C ID=-250µA See Fig 7
VGS(th) Gate Threshold Voltage -2.0 -- -4.0 V VDS=-5V,ID=-250µA
Gate-Source Leakage , Forward -- -- -100 VGS=-20V
IGSS nA
Gate-Source Leakage , Reverse -- -- 100 VGS=20V
-- -- -10 VDS=-60V
IDSS Drain-to-Source Leakage Current µA o
-- -- -100 VDS=-48V,TC=125 C O
4

Static Drain-Source
RDS(on) -- -- 0.3 Ω VGS=-10V,ID=-3.8A
On-State Resistance
gfs Forward Transconductance -- 3.6 -- Ω VDS=-30V,ID=-3.8A O
4

Ciss Input Capacitance -- 465 600

VGS=0V,VDS=-25V,f =1MHz
Coss Output Capacitance -- 140 215 pF
See Fig 5
Crss Reverse Transfer Capacitance -- 40 60
td(on) Turn-On Delay Time -- 11 30
VDD=-30V,ID=-9.4A,
tr Rise Time -- 21 50
ns RG=18 Ω
td(off) Turn-Off Delay Time -- 29 65
See Fig 13 O
4 O
5
tf Fall Time -- 20 50
Qg Total Gate Charge -- 15 19 VDS=-48V,VGS=-10V,
Qgs Gate-Source Charge -- 2.9 -- nC ID=-9.4A
Qgd Gate-Drain(“Miller”) Charge -- 6.0 -- See Fig 6 & Fig 12 O
4 O
5

Source-Drain Diode Ratings and Characteristics

Symbol Characteristic Min. Typ. Max. Units Test Condition
IS Continuous Source Current -- -- -7.6 Integral reverse pn-diode
A
ISM Pulsed-Source Current O
1 -- -- -30 in the MOSFET
o
VSD Diode Forward Voltage O
4 -- -- -3.8 V TJ=25 C,IS=-7.6A,VGS=0V
o
trr Reverse Recovery Time -- 80 -- ns TJ=25 C,IF=-9.4A
Qrr Reverse Recovery Charge -- 0.22 -- µC diF/dt=100A/µs O
4

Notes ;
O Repetitive Rating : Pulse Width Limited by Maximum Junction
1
o
Temperature
O2 L=2.0mH, I AS =-7.6A, V DD =-25V, R G =27Ω * , Starting T J =25 C
O3 ISD <_ -9.4A, di/dt <_ 250A/ µs, VDD <_ BVDSS , Starting T J =25 C
o

O4 Pulse Test : Pulse Width = 250 µs, Duty Cycle _

< 2%
O5 Essentially Independent of Operating Temperature
 P-CHANNEL
POWER MOSFET SFR/U2955
Fig 1. Output Characteristics Fig 2. Transfer Characteristics
VGS
[A]

Top : - 15 V

[A]
- 10 V
- 8.0 V
101 - 7.0 V 101
-ID , Drain Current

-ID , Drain Current

- 6.0 V
- 5.5 V
- 5.0 V
Bottom : - 4.5 V
150 oC

100 100
@ Notes :
25 oC
@ Notes : 1. VGS = 0 V
1. 250 µs Pulse Test 2. VDS = -30 V
2. TC = 25 oC 3. 250 µs Pulse Test
- 55 oC

10-1 10-1
10-1 100 101 2 4 6 8 10
-VDS , Drain-Source Voltage [V] -VGS , Gate-Source Voltage [V]
[A]

Fig 3. On-Resistance vs. Drain Current Fig 4. Source-Drain Diode Forward Voltage
Drain-Source On-Resistance

0.4
-IDR , Reverse Drain Current
RDS(on) , [Ω ]

0.3 101

VGS = -10 V
0.2

100
150 oC
0.1 @ Notes :
1. VGS = 0 V
o
25 C 2. 250 µs Pulse Test
VGS = -20 V @ Note : TJ = 25 oC

0.0 10-1
0 10 20 30 40 50 60 70 0.5 1.0 1.5 2.0 2.5 3.0 3.5
-ID , Drain Current [A] -VSD , Source-Drain Voltage [V]

Fig 5. Capacitance vs. Drain-Source Voltage Fig 6. Gate Charge vs. Gate-Source Voltage
800
[V]

Ciss= Cgs+ Cgd ( Cds= shorted )

Coss= Cds+ Cgd VDS = -12 V
10
[pF]

VDS = -30 V
-VGS , Gate-Source Voltage

C iss Crss= Cgd

600 VDS = -48 V
Capacitance

C oss

400
@ Notes : 5
1. VGS = 0 V
2. f = 1 MHz
200 C rss

@ Notes : ID =-9.4 A

0 0
100 101 0 2 4 6 8 10 12 14 16
-VDS , Drain-Source Voltage [V] QG , Total Gate Charge [nC]
 P-CHANNEL
SFR/U2955 POWER MOSFET

Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature

Drain-Source Breakdown Voltage

1.2 2.5

Drain-Source On-Resistance
-BVDSS , (Normalized)

RDS(on) , (Normalized)
2.0
1.1

1.5

1.0

1.0

0.9 @ Notes : @ Notes :

1. VGS = 0 V 0.5 1. VGS = -10 V
2. ID = -250 µA 2. ID = -4.7 A

0.8 0.0
-75 -50 -25 0 25 50 75 100 125 150 175 -75 -50 -25 0 25 50 75 100 125 150 175
o
TJ , Junction Temperature [ C] TJ , Junction Temperature [oC]
[A]

Fig 9. Max. Safe Operating Area Fig 10. Max. Drain Current vs. Case Temperature
[A]
-ID , Drain Current

Operation in This Area

8
102 is Limited by R DS(on)
-ID , Drain Current

6
0.1 ms
101 1 ms
10 ms
4
DC
@ Notes :
100 1. TC = 25 oC
2. TJ = 150 oC 2
3. Single Pulse

10-1 0
100 101 102 25 50 75 100 125 150
-VDS , Drain-Source Voltage [V] Tc , Case Temperature [oC]

Fig 11. Thermal Response

10 1
Thermal Response

D=0.5
@ Notes :
10 0 1. Zθ J C (t)=3.91 o C/W Max.
0.2
2. Duty Factor, D=t1 /t 2
3. TJ M -T C =P D M *Z θ J C (t)
0.1
P.DM
0.05
(t) ,

0.02 t1.
10- 1 0.01 t2.
θJC

single pulse
Z

10- 5 10- 4 10 - 3 10 - 2 10 - 1 100 10 1

t 1 , Square Wave Pulse Duration [sec]
 P-CHANNEL
POWER MOSFET SFR/U2955
Fig 12. Gate Charge Test Circuit & Waveform

“ Current Regulator ”
VGS
Same Type
50KΩ as DUT Qg
12V 200nF
300nF -10V

VDS
VGS Qgs Qgd

DUT

-3mA
R1 R2

Current Sampling (IG) Current Sampling (ID)

Charge
Resistor Resistor

Fig 13. Resistive Switching Test Circuit & Waveforms

RL
t on t off
Vout tf
td(on) tr td(off)
Vin VDD
( 0.5 rated VDS ) Vin
10%
RG
DUT

-10V
90%
Vout

Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms

BVDSS
LL 1
EAS = ---- LL IAS2 --------------------
VDS 2 BVDSS -- VDD
Vary tp to obtain ID tp Time
required peak ID
VDD VDS (t)
RG C VDD ID (t)
DUT
-10V IAS
tp BVDSS
 P-CHANNEL
SFR/U2955 POWER MOSFET

Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms

VDS
DUT
--

IS
L

Driver
VGS
Compliment of DUT
RG
(N-Channel) VDD

VGS • dv/dt controlled by “RG”

• IS controlled by Duty Factor “D”

Gate Pulse Width

VGS D = --------------------------
Gate Pulse Period 10V
( Driver )

Body Diode Reverse Current

IRM
IS
( DUT )
di/dt

IFM , Body Diode Forward Current

Vf
VDS
( DUT )
Body Diode VDD
Forward Voltage Drop

Body Diode Recovery dv/dt

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PRODUCT STATUS DEFINITIONS

Definition of Terms

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Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.

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supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

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any time without notice in order to improve design.

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that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.