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KA431 / KA431A / KA431L Programmable Shunt Regulator: Features Description
KA431 / KA431A / KA431L Programmable Shunt Regulator: Features Description
July 2013
Features Description
• Programmable Output Voltage to 36 V The KA431 / KA431A / KA431L are three-terminal
• Low Dynamic Output Impedance: 0.2 Ω (Typical) adjustable regulators with a guaranteed thermal stability
over the operating temperature range. The output volt-
• Sink Current Capability: 1.0 to 100 mA
age can be set to any value between VREF (approxi-
• Equivalent Full-Range Temperature Coefficient
mately 2.5 V) and 36 V with two external resistors.
of 50 ppm/°C (Typical) These devices have a typical dynamic output impedance
• Temperature Compensated for Operation of 0.2 Ω. Active output circuitry provides a sharp turn-on
Over Full Rated Operating Temperature Range characteristic, making these devices excellent replace-
• Low Output Noise Voltage ments for Zener diodes in many applications.
• Fast Turn-on Response TO-92
1
1. Ref 2. Anode 3. Cathode
8-SOIC
1.Cathode 2.3.6.7.Anode
4.5.NC 8.Ref
Ordering Information
Operating
Output Voltage
Part Number Temperature Top Mark Package Packing Method
Tolerance
Range
KA431DTF 2% 431 8-SOIC Tape and Reel
KA431ADTF 431A 8-SOIC Tape and Reel
KA431AZBU -25 ~ +85°C 1% KA431AZ TO-92 Bulk
KA431AZTA KA431AZ TO-92 Ammo
KA431LZTA 0.5% KA431LZ TO-92 Ammo
+ CATHODE
REFERENCE
-
2.5 Ref
ANODE
CATHODE (K)
REFERENCE (R)
ANODE(A)
Figure 2. Test Circuit for VKA= VREF Figure 3. Test Circuit for VKA ≥ VREF
Figure 5. Cathode Current vs. Cathode Voltage Figure 6. Cathode Current vs. Cathode Voltage
Figure 7. Change in Reference Input Voltage vs. Figure 8. Dynamic Impedance Frequency
Cathode Voltage
Figure 9. Small Signal Voltage Amplification vs. Figure 10. Pulse Response
Frequency
140
A
120 A VKA = Vref B
B VKA = 5.0 V @ IK = 10mA
C VKA = 10 V @ IK = 10mA C
IK, CATHODE CURRENT(mA)
60
40
D
20
0
100p 1n 10n 100n 1? 10?
R 1 R
1 R 1
V O = 1 + ------- V V O = V ref 1 + ------- V O = 1 + ------- V
R 2 ref R
2 R 2 ref
Figure 12. Shunt Regulator Figure 13. Output Control for Three- Figure 14. High-Current Shunt
Terminal Fixed Regulator Regulator
Figure 15. Current Limit or Current Source Figure 16. Constant-Current Sink
D
D) DRAWING FILENAME: MKT-ZA03DREV3.
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/ZA/ZA03D.pdf.
For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area:
http://www.fairchildsemi.com/packing_dwg/PKG-ZA03D_BK.pdf.
D
D) DRAWING FILENAME: MKT-ZA03FREV2.
Figure 18. 3-Lead, TO-92, Molded, 0.200 in Line Spacing Lead Form
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/ZA/ZA03F.pdf.
For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area:
http://www.fairchildsemi.com/packing_dwg/PKG-ZA03F_BK.pdf.
8-SOIC
5.00 A
4.80 0.65
3.81
8 5
B
6.20 1.75
5.80 4.00 5.60
3.80
PIN ONE 1 4
INDICATOR
1.27
(0.33) 1.27
0.25 C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.25
0.10
0.25
1.75 MAX C 0.19
0.51 0.10
0.33 OPTION A - BEVEL EDGE
0.50 x 45°
0.25
R0.10 GAGE PLANE
Figure 19. 8-Lead, SOIC, JEDEC MS 0-12, 0.150 inch Narrow Body
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/M0/M08A.pdf.
For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area:
http://www.fairchildsemi.com/packing_dwg/PKG-M08A_PSTS.pdf.
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