Design and Performance of a High Efficiency Ka-band Power Amplifier
MMIC
Charles F. Campbell , Deep C. Dumka, Ming-Yih Kao and David M. Fanning
TriQuint Semiconductor, Richardson, TX 75080, ccampbell@tqs.com
Abstract — The design and performance of a 0.15-μm
PHEMT high efficiency Ka-band power amplifier MMIC is
presented. The 3-stage amplifier utilizes a commercially
available production released process with demonstrated
reliability and 3-metal interconnect (3MI) technology.
Experimental continuous wave (CW) in-fixture results for the
power amplifier MMIC demonstrate up to 3.8W of saturated
output power and 36% associated power added efficiency at
34GHz.
Index Terms — Power Amplifier, MMIC, Ka-band, PHEMT.
I. INTRODUCTION
Significant effort has been spent over the last few years to
develop Ka-band power amplifier MMICs for both
commercial and military systems. Typical applications for
these amplifiers include point to point radio networks, VSAT
satellite ground terminals, EW systems and the test equipment
market. Recently published benchmarks demonstrate steady
progress in improving both output power and efficiency
performance of Ka-band power amplifier MMICs [1]-[5]. In
this paper the design and performance of Ka-band power
amplifier MMIC utilizing a commercially available production
released TriQuint Semiconductor 0.15-μm GaAs PHEMT
(DR15) process is described.
II. PROCESS TECHNOLOGY
The MMIC described in this paper was fabricated on GaAs-
based epitaxial wafers with an InGaAs channel grown by
Molecular Beam Epitaxy (MBE) and a dual-recessed (DR)
0.15μm PHEMT process. The MBE layer growth sequence
starts with a semi-insulating GaAs buffer followed by
the AlAs/GaAs superlattice layers, pulse silicon doping and an
un-doped AlGaAs spacer. This is followed by the InGaAs
channel layer, an un-doped AlGaAs spacer, a second pulse
+
silicon doping, n-AlGaAs Schottky layer and finally an n
GaAs cap layer. Openings for both the wide (first) and gate
(second) recesses are defined by the e-beam lithography. The
first recess stops at the top of the AlGaAs Schottky layer. An
AlAs etch-stop layer was inserted in the n-AlGaAs Schottky
layer to achieve a nominal pinch-off voltage of -1.05V
consistently across a wafer and wafer to wafer. A source-
drain spacing of 2μm was utilized to minimize the access
resistances. Epitaxial layer structures and process parameters
for the dual-recess 0.15μm PHEMT process were optimized to
978-1-4244-7438-7/10/$26.00 ©2010 IEEE
achieve a maximum drain current density greater than
675mA/mm, peak transconductance of 470mS/mm, Idss of
375mA/mm, and typical two-terminal gate to drain breakdown
voltage of 12 to 15 volts. An FT of 57GHz and FMAX of
160GHz are routinely achieved for 4x75μm PCM transistor
cells. The substrate is thinned to 50μm and 7.5x40μm slot
vias are formed by reactive ion etching (RIE). This process
uses a 3-metal interconnect technology which features three
interconnect layers, 50Ω/sq. thin film resistors, three available
2
capacitance densities (240, 300 and 1200 pF/mm ), and
capacitors built directly over substrate vias. The small slot
vias and capacitor over via feature are particularly useful for
mm-wave designs where parasitic effects should be minimized
and circuit matching elements are located in close proximity to
one another.
III. CIRCUIT DESIGN
The design goals for this 3-stage power amplifier MMIC
were to achieve greater than 30% power added efficiency and
3W associated output power under continuous wave (CW)
operating conditions covering as much of the 33-37GHz band
as possible. The first step in the design process was to select
appropriate transistor cells that optimize Ka-band performance
and demonstrate acceptable thermal properties under CW
operation. For the output stage a 300μm unit FET cell
constructed of 12x25μm long gate fingers with 15μm gate to
gate pitch was selected. The air bridge connected source
contacts are grounded with two substrate vias located on
opposite sides of the transistor. This transistor cell design
deviates somewhat from the individual source (ISV) via
topology that has been typical of TriQuint Semiconductor
Ka-band power amplifier MMICs [3]. The minimum practical
gate finger length for a FET cell with a ISV topology is about
50μm, set by the length of the via contact. Using a shorter
gate finger length improves RF and thermal performance. The
reduced channel temperature afforded by a shorter gate finger
allows one to reduce the gate to gate pitch providing yet an
additional improvement in electrical performance. Continuous
wave load pull results at 30GHz are summarized in Table 1 for
6x25μm, 8x25μm and 12x25μm FET cells under efficiency
tuned conditions.
These transistor cells are capable of very good Ka-band
performance demonstrating 800-900mW/mm of output power
and associated power added efficiency well over 50%.
Thermal simulation of the 12x25µm FET cell predicts that for
a +85ºC MMIC backside temperature and 630mW/mm power IV. MEASURED RESULTS
dissipation (see Table 1) that the channel temperature will be
about 130ºC. This is well under the maximum recommended Completed devices were 100% DC and RF tested on-wafer
channel temperature of 150ºC for the DR15 process and will at TriQuint’s production test facility. On-wafer RF probe
result in reliable operation. power data is shown in Fig. 2 for the 4-wafer process lot (246
total devices). The production on-wafer test system does not
provide a suitable thermal environment for CW operation,
Table 1. Efficiency tuned 30GHz Load pull data at 6.0 V and therefore the 6.0V drain bias supply was pulsed at 10% duty
150mA/mm quiescent bias.
cycle with a 1μs pulse width. The unscreened results shown
FET Cell Pout-dBm PAE % GAIN-dB Pdiss Pout in Fig. 2 are at 3dB of gain compression. Measured output
Size @Max PAE @Max PAE @Max PAE mW/mm mW/mm power is typically greater than 3W with PAE ranging from
6x25um 21.4 53.9 9.1 695 926 about 24% to 35% for the 32-36GHz frequency band. Good
8x25um 22.6 54.1 9.3 682 909
uniformity was also observed with most of the devices falling
12x25um 24.0 53.1 8.4 627 829
within a +/- 0.4dB distribution about the mean. Since the
circuit was designed to accommodate bond wires connected to
the RF ports, the amplifier will not be optimally loaded for an
To achieve the output power and efficiency goals the
on-wafer testing environment.
following three stage line up was selected. The output stage is
constructed with 16-way combined 12x25μm FET cells which
is driven by second stage built with 8-way combined 8x25μm
36 50
devices. The first stage is comprised of 4-way combined
6x25μm cells producing an overall staging ratio of 3:1 and 35 45

Power Added Efficiency (%)

2.67:1 for output and second stages respectively. This staging
P3dB
ratio will provide about 2.5dB of room temperature drive Output Power (dBm) 34 40
margin for the second stage assuming 1dB of loss in the 2-3 33 35
interstage. The various networks were designed using a
TM
modified version of the Cripps’s method within the AWR 32 30
Microwave Office simulation environment tuned to the load
pull conditions listed in Table 1. Capacitors built directly over 31 25

the substrate vias are used extensively in the matching 30 20

networks. This approach significantly reduces the impact of
substrate thickness variation on overall circuit performance
compared to using very wide transmission lines to realize
shunt capacitance [1,2,5]. The design was finalized with
TM
extensive EM simulation using Sonnet . A photograph of the
fabricated MMIC mounted to the test carrier is shown in Fig.
2
1, the die dimensions are 2.75x3.6mm .
Fig. 1. Photograph of 3W power amplifier MMIC
PAE
29 15
31 32 33 34 35 36 37 38 39
Frequency (GHz)
Fig. 2. On-wafer production RF-probe data.
To facilitate in-fixture testing separated die were soldered to
20mil thick CuMo carrier plates. The amplifier input and
output bond pads are connected to 10mil thick alumina de-
embedding lines with two short bond wires as shown in Fig. 1.
The MMIC is mounted on top of an 8mil tall pedestal that is
machined into the carrier plate such that the surface of the
2mil thick die will be flush with alumina de-embedding lines.
The carrier assembly is then inserted into an aluminum test
TM
fixture with an intervening layer Arctic Silver thermal grease
to ensure good thermal contact between the carrier plate and
fixture. The opposite ends of the alumina de-embedding lines
are contacted with 2.4mm connectorized launchers and the
entire fixture is placed on an aluminum heat sink. The
calibration procedure will de-embed the launchers and
alumina lines up to the start of the flare where the bond wires
attach.
Measured wideband s-parameter data for an amplifier
sample from each of the 4 wafers is shown in Fig. 3 for a
6.0V-1.05A quiescent condition. The small signal gain varies
between 20dB and 25dB over the 33-37GHz band, input and in Fig. 7 where the drain current does not drive up very much
output return losses are better than 8dB and 6dB respectively. from its quiescent value for some of the frequencies. The
Measured in-fixture continuous wave output power and bandwidth of this amplifier could likely be improved through
efficiency results for the same devices are shown in Fig. 4 for a re-optimization of the interstage matching networks.
a +18dBm input drive level. The devices are again biased at a
6V-1.05A quiescent condition for all cases. The measured
output power level is typically greater than 2W over a 30- 37
38GHz frequency range with a maximum value of 3.8W
occurring around 34GHz. The design target power level of 34

Output Power (dBm)

3W is typically achieved from about 32.5GHz to 36GHz.
Power added efficiency is typically greater than 20% from 31
30-38GHz with a maximum value of 36% around 34GHz.
The design goal of greater than 30% was achieved from about 28
33-36GHz.
25
30
22
20
3 5 7 9 11 13 15 17 19 21
Gain and Return Loss (dB)

Gain
10 Input Power (dBm)

0 ORL
Fig. 5. Output power versus input power.
-10
IRL
-20
40
-30
Power Added Efficiency (%)

-40 32

-50
24
5 10 15 20 25 30 35 40 45
Frequency (GHz)
16
Fig. 3. In-fixture CW small signal s-parameter data.
8

37 70 0
3 5 7 9 11 13 15 17 19 21
Power Added Efficiency (%)

35 60 Input Power (dBm)

Output Power (dBm)

33 50
Fig. 6. Power added efficiency versus input power.
31 40

29 30 2.0

27 20
1.8
Input Power = 18dBm
Drain Current (A)

25 10
30 31 32 33 34 35 36 37 38 1.6

Frequency (GHz)
1.4
Fig. 4. Measured CW power and efficiency at 18dBm input power.
1.2

Compression curves for one of the amplifier MMICs are 1.0

plotted in Figs. 5-7. The family of curves represent measured 3 5 7 9 11 13 15 17 19 21
data over a frequency range of 30GHz to 38GHz in 1GHz Input Power (dBm)
steps. The compression characteristics are well behaved with
no evidence of kink, odd-mode or driven oscillations. Some Fig. 7. Total MMIC drain current versus input power.
evidence of drive margin issues were observed however,
particularly for the lower band edge. This can be seen clearly
 The results presented here are compared to published
benchmarks in Table 2. The references listed are for two or
more stage GaAs based monolithic power amplifier MMICs of
similar output power that operate between 30GHz and 40GHz.
The reported gain is typical small signal gain over the claimed
operating band. The power added efficiency is the maximum
reported and the output power is that associated with the
maximum reported PAE. Note that for some of the references
the MMICs were tested under pulsed power conditions and/or
on-wafer where the impact of bonding wires is not included.
The results presented in this paper compare favorably with
state of the art published results, especially for power added
efficiency and die size.
34GHz. To the best knowledge of the authors, the power
added efficiency results presented here are among the highest
ever reported for a multi-stage GaAs power amplifier MMIC
operating at 34GHz with a greater than 3W output power
level.
ACKNOWLEDGEMENT
The work was funded under an Office of Naval Research
contract. The authors wish to thank Harry Dietrich for
guidance and encouragement during the course of this project,
Larry Giacoma for performing the thermal analysis and Terry
Montierth for designing the test fixture.

Table 2. Ka-band Power Amplifier Benchmarks. REFERENCES

Ref Freq. # Test Test Gain Power PAE Die Area [1] J. J. Komiak et al., “Fully Monolithic 4 Watt High Efficiency
# (GHz) Stages Method Signal (dB) (dBm) (%) mm 2 Ka-Band Power Amplifier,” 1999 IEEE Int. Microwave Symp.
[1] 30 2 On Wafer Pulsed 18 36.5 31 14.8 Dig., pp. 947-950.
[2] 29 3 Fixture CW 24 36.3 32 16.3 [2] F. Colomb et al., “2 and 4 watt Ka-band GaAs PHEMT power
[3] 30 3 Fixture CW 22 36.2 25 8.6 amplifier MMICs,” 2003 IEEE Int. Microwave Symp. Dig., pp.
[4] 30 3 Fixture CW 21 36.0 31 14.0
843-846.
[5] 35 3 Fixture Pulsed 22 35.5 26 12.7
[3] K. Kong et al., “Ka-Band MMIC High Power Amplifier (4W at
Here 34 3 Fixture CW 22 35.8 36 9.9
30 GHz) with Record Compact Size,” 2005 Compound
Semiconductor IC Symp. Dig., pp.232-235.
[4] S. J. Mahon et al., “A family of 1, 2 and 4-watt power amplifier
MMICs for cost effective VSAT ground terminals,” 2005
V. CONCLUSION
Compound Semiconductor IC Symp. Dig., pp.224-227.
The design and performance of a 0.15-μm PHEMT high [5] S. J. Mahon et al., “35 dBm, 35 GHz Power Amplifier MMICs
using 6-inch GaAs PHEMT Commercial Technology,” 2008
efficiency Ka-band power amplifier MMIC been presented.
IEEE Int. Microwave Symp. Dig., pp. 855-858.
Experimental results for the circuit demonstrate up to 3.8W
output power and 36% associated power added efficiency at