CS 322M Digital Logic & Computer Architecture

Control Unit

J. K. Deka
Professor
Department of Computer Science & Engineering
Indian Institute of Technology Guwahati, Assam.
Model of Control Unit
 Control Signals - output
• Within CPU
– Cause data movement
– Activate specific functions
• Via control bus
– To memory
– To I/O modules
 Example Control Signal Sequence - Fetch

• MAR <- PC
– Control unit activates signal to open gates
between PC and MAR
• MBR <- memory
– Open gates between MAR and address bus
– Memory read control signal
– Open gates between data bus and MBR
Single Bus Organization of CPU
Universal Shift Register
CPU with Internal Bus

ALU
Register and Bus Connection
Internal and External Bus
Read and Write Signal
Read and Write Signal
Timing Diagram
 Control Step for Execution
• ADD R1, R2, R3
– Add the contents of Register R1 and R2 and
store the result in R3
Single Bus Organization of CPU

Operation:

R3 ← R1+R2

Steps:

Y ← R1
Z ← Y+R2
R3 ← Z
 Control Step for Execution
• ADD R1, R2, R3
– Add the contents of Register R1 and R2 and
store the result in R3

Steps:

Y ← R1
Z ← Y+R2
R3 ← Z
 Clock Timing
• Time needed for micro-operation 2
– R2out, ADD, Zin
 Instruction Fetch and Execute
• ADD (R3), R1
– Add the content of Register R1 to the content
of memory location whose memory address is
in register R3 and store the result in R1

Addressing Mode:
(R3) : Register Indirect
R1: Register Direct
Single Bus Organization of CPU

PC contains the
Address of the
Instruction.

Issues for PC
Updates:
When and how

Assumption:
Instruction length
- one word
 Instruction Fetch and Execute
• ADD (R3), R1
– Add the content of Register R1 to the content
of memory location whose memory address is
in register R3 and store the result in R1
 Instruction Fetch and Execute
• ADD (R3), R1
– Add the content of Register R1 to the content
of memory location whose memory address is
in register R3 and store the result in R1
Fetch Phase:

t1: MAR <- PC, Read

t2: MDR <- Memory
PC <- PC + 1
t3: IR <- MDR
 Instruction Fetch and Execute
• ADD (R3), R1
– Add the content of Register R1 to the content
of memory location whose memory address is
in register R3 and store the result in R1
Execute Phase:

t1: MAR <- R3, Read

t2: MDR <- Memory
Y <- R1
t3: Z <- Y + MDR
t4: R1 <- Z
 Reference
Computer Organization and Architecture –
Designing for Performance
William Stallings, Seventh Edition

Chapter 16: Control Unit Operation

Computer Organization
Hamacher, Vranesic and Zaky, Fifth Edition

Chapter 07: Page No.: 411 - 429