Computer Organization and

Architecture
First step in learning design and working of computers and processors

Mr. Vijay S R ( SRV )

E & C dept., FC-3,
cabin No: 24
Course objectives
• arrangement of internal functional units and operation
of computer system
• Instruction Set Architecture, ISA
• ALU
• memory
• Input and output
• control unit
• Introduction to the techniques of increasing the
performance of processors and overall computing
About COA
• few questions about how computers work
• Why is RAM required, when we have a hard-disk and other storage devices?
• What happens inside a computer when I start a program?
• how does a CPU function?
• …

• possible situations where COA knowledge will be applicable

• Recommend a computer for a particular application
• Improve software and hardware performance
• designing processors, memory, embedded system etc.
• Selecting a processor or controller for a specific application
• Higher studies
• …
About COA and my classes
• Logic design is the basic for COA; microcontrollers subject is very
closely related to COA.
• interesting subject; score in LD?
• Notes will not be given; slides and lectures are only to understand the
concepts; they may not be sufficient
• Less theory, less numerical
• More conceptual; understanding is the easiest way to remember the
subject and score marks
• understand the concepts in class
About COA and my classes
• Syllabus is a lot; extra classes needed
• Attendance is important and strict
• Marking is as per scheme
• Expect discipline and honesty in class; helpful in long run
• questions and interactions in class are encouraged
• Your behavior is important
• Advised to read text books and make your own notes
Structure of computer- Top Level

Peripherals Computer

Central Main
Processing Memory
Unit

Computer
Systems
Interconnection

Input
Output
Communication
lines
Structure of computer- The CPU

CPU

Computer Arithmetic
Registers and
I/O Logic Unit
System CPU
Bus
Internal CPU
Memory Interconnection

Control
Unit
Structure of computer- The Control Unit

Control Unit

CPU
Sequencing
ALU Logic
Control
Internal
Unit
Bus
Control Unit
Registers Registers and
Decoders

Control
Memory
Computer: Hardware and software
Computer Design

Instruction Set Design Computer Hardware Design

Machine Language
Compiler View Machine Implementation
Logic Designer's View
"Computer Architecture"
"Instruction Set Architecture"
"Computer Organization”

"Building Architect“ “Construction Engineer”

On paper On ground
Levels of computer – software to hardware
• Application programs
• High-level programming languages From
• Assembly level and machine level languages software at
the top
• Micro-programmed and hardwired control level to
• Functional units- ALU, memory etc. hardware at
• Logic gates the bottom

• Transistors, diodes and wires

The Big Picture
Problem Focus
SPEC Requirements
f1 f2 i
p
Algorithms f5 f3 s q j
f2() { fp
f3(s2, &j, &i); f3
*s2->p = 10; f4
i = *s2->q + i; Prog. Lang./OS
} i1: ld r1, b <p1>
i2: ld r2, c <p1>
ISA i3: ld r5, z <p3>
i4: mul r6, r5, 3 <p3>
i5: add r3, r1, r2 <p1>
uArch
Performance Focus
S reg X reg
Add, Mult2
Sub,
Shift
Mac1 Mac2
Mult1

Circuit

Gate

Source Drain Device

BOX Si fin - Body!
 Architecture and Organization
• Architecture are those attributes visible to (used by) the
programmer; closely related to processor (instruction set)
• Instruction set, number of bits used for data representation, I/O
mechanisms, data addressing techniques.
• e.g. Is there a multiply instruction?
• Organization is how features are implemented. (transparent to the
programmer); closely related to computer hardware (including
processor hardware)
• Control signals, interfaces, memory technology.
• e.g. how is the multiply instruction implemented in hardware?
Architecture and Organization
• Will my old code run on the new upgraded processor or
computer?
• Will my old programs run when I switch from Macintosh to
windows PC? (Same with iphone and android)
• All Intel x86 family share the same basic architecture
• The IBM System/370 family share the same basic architecture
• This gives code compatibility
• Which printer should I buy?
• depends on the interface supported
 Instruction Set Architecture (ISA)

• Serves as an interface between software and hardware.

• Provides a mechanism by which the software tells the hardware
what should be done.

High level language code : C, C++, Java, Fortran,

compiler
Assembly language code: architecture specific statements
assembler
Machine language code: architecture specific bit patterns

software

instruction set
hardware
Examples of ISA
• IA- 32 – from Intel
• 80386, 80486, Pentium, Athlon etc
• PowerPC – from IBM – AIM alliance
• Power1, Power2, etc
• Motorola, IBM etc
tosrvmailbox
• Macintosh, ASIMO @gmail.com
• MIPS – from MIPS
• R2000, R3000, R4000 etc
• Sony Playstation and NEC Nitendo
• SPARC – from sun micro systems
• ARM – from ARM
Basic terms and concepts:
• Program or software or code; sequence of instructions
• 3 levels of programming
• HLL
• ALL
• LLL
• Stored Program Concept, SPC
• punched cards fed one after another
• stack of cards fed together at a time
• Fetch – decode – execute
Fetch-Decode-Execute Cycle

Get the instruction

Fetch from memory
registers and buses

Understand the
Decode instruction
Control Unit

Arithmetic and Logical

Execute Execute the instruction
Unit
 This is what computers do all the time!!!
Start
here
Instruction Cycle; IC
1. Fetch instruction to be executed, from memory
2. control unit decodes the fetched instruction
3. Execute the decoded instruction
• data (operands) may be fetched from memory, if needed for execution
• do some data processing (Arithmetic or logical)
• store results in memory if necessary
4. Goto step 1, i.e. repeat!!!
• The sequence of these three cycles is called as an Instruction cycle
• the processor goes through one instruction cycle to perform one instruction
1 3

Repeat
Central Processing Unit (CPU)
• Also called the “microprocessor” or “processor”
• The brain of the computer - It does all the processing
• Major components:
• Arithmetic Logic Unit (ALU)
• Does all the math and logic operations
• Control unit
• “Sequences the operations” of the processor
• Timing of operations
• Registers
• holds data that is “in process” at the moment
• Communication bus systems
CPU
• CPU is responsible for executing a sequence of instructions
• Each instruction is stored in memory along with data
• CPU is in charge of retrieving the next instruction from memory
(fetch), understand it, (decoding) and work it out (executing)
• Execution usually requires the use of ALU and temporary storage in
registers
• We divide the CPU into two areas
• Datapath – registers and ALU (the execution unit)
• Control unit – circuits in charge of performing the fetch-decode-
execute cycle
 ALU
• Consists of circuits to perform arithmetic and logic operations
• Adder
• Multiplier
• Shifter
• Comparator
• Operations in the ALU set status flags (carry, overflow, positive, zero,
negative)
• May have temporary registers to store data before moving final
results back to register or memory
Control Unit
• in charge of managing the fetch-decode-execute cycle
• It sends out control signals to all other hardware units
• control signal activates a device to perform it’s function
• For instance:
• Instruction fetching event or activity requires
• sending address of memory location (PC) to main memory
• signaling memory to read
• when the datum comes from memory, move it to a register (IR)
• increment PC to point to the next instruction
The System Clock
• In order to regulate when the CU issues control signals,
computers use a system clock
• At each clock pulse, the control unit goes on to the next task
• Register values are loaded or stored at the beginning of a clock pulse
• ALU circuits activate at the beginning of a clock pulse
Registers
• memory types:
• RAM; main memory
• Hard drives; secondary memory
• Registers are also memory
• Temporary storage of data inside the CPU
• Extremely fast, compared to RAM or hard-drives
• Very small storage capacity, few bytes
How does memory look like?
Address Data
• RAM, associated with two numbers 0 36
• Address and Data 1 45
• Address is the location 2 76
• Data is the value stored in the location 3 56
• Memory stores both data and 4 52
machine instructions 5 60
• everything stored in memory is in 6 23
bits 7 42
• Address and data are in hex 8 66
RAM
• 16 bytes of memory shown in the
diagram
• Data and code (instructions) are
represented using bits
• Memory stores both data and code
• What should be the number of
address lines for addressing 1KB of
memory?
• 8051 has 64KB of addressing
capacity, then how many address
lines it has?
Memory Organization
Memory can be organized into byte or word-sized blocks
• Each block has a unique address
• This can be envisioned as an array of cells
• The CPU accesses memory by sending an address of the intended location and a
control command to read or write
• The memory module then responds to the request appropriately

Byte addressable Word addressable

Memory device or IC
1. Address bus
2. Control bus
1. Read signal (input signal to memory device)
2. Write signal
3. Ready signal (output signal from memory device)
3. Data bus Address bus Memory Data bus
chip
• Power supply and ground control bus
Processor and Memory connections

• Memory stores both Data and Program

• Memory is accessed by processor
• a physical connection has to be established between
processor and memory
• Two options for connecting processor and memory
• Data memory and program memory separated physically
• Data and program are not separated physically
Von Neumann architecture

Address bus
Data,
program
processor memory
Data bus and I/O
ports
Harvard architecture
Address bus Data
memory
and I/O
Data bus ports

processor
Address bus
program
memory
Data bus
Harvard architecture Address bus Data
memory
and I/O
Data bus
• Harvard can’t use self modifying code ports
processor
• Allows two simultaneous memory fetches Address bus
program
• Most DSP’s use Harvard for streaming data Data bus
memory

• Greater memory bandwidth

• Different memory bit depth between instructions and data
• More predictable bandwidth
• Easy to implement pipelining
• Can have an efficient pipelining
Von Neumann architecture
• They have shared signals and memory for code and data
• program can be easily modified by itself since it is stored in read-write
memory
• More flexible and easy to implement
• Suitable for general purpose processors
Address bus Data,
program
processor memory
and I/O
Data bus
ports