Enter Sleep Mode:

A CPU must execute the following steps to enter sleep mode from normal run mode:
1. Disable interrupts. Execute cpsid if.
2. Con gure wake-up device.
3. Enable L2 cache dynamic clock ga ng. Set
l2cpl310.reg15_power_ctrl[dynamic_clk_ga ng_en]
= 1.
4. Enable SCU standby mode. Set mpcore.SCU_CONTROL_REGISTER[SCU_standby_enable] =
1.
5. Enable topswitch clock stop. Set slcr.TOPSW_CLK_CTRL[CLK_DIS] = 1.
6. Enable Cortex-A9 dynamic clock ga ng. Set
cp15.power_control_register[dynamic_clock_ga ng] = 1.
7. Put the external DDR memory into self-refresh mode. Refer to sec on 10.9.6 DDR Power
Reduc on.
8. Put the PLLs into bypass mode. Set slcr.{Arm, DDR, IO}_PLL_CTRL[PLL_BYPASS_FORCE] =1.
9. Shut down the PLLs. Set slcr.{Arm, DDR, IO}_PLL_CTRL[PLL_PWRDWN] = 1.
10. Increase the clock divisor to slow down the CPU clock. Set slcr.ARM_CLK_CTRL[DIVISOR]
=0x3f.
11. Execute the w instruc on to enter WFI mode.

Exit Sleep Mode :

Exi ng sleep mode is triggered by the con gured interrupt occurring. The interrupt wakes up
the CPU which resumes execu on. The newly star ng ac vity also triggers the topswitch,
SCU, and L2 cache controller to leave their idle states and con nue normal opera on. The
procedure for waking up is outlined below.

To exit from sleep mode:

1. Restore CPU clock divisor se ng. Set slcr.ARM_CLK_CTRL[DIVISOR] = <original value>.

2. Power on the PLLs. Set slcr.{ARM, DDR, IO}_PLL_CTRL[PLL_PWRDWN] = 0.
3. Wait for PLL power-on and lock. Wait for
slcr.PLL_STATUS[{ARM, DDR, IO}_PLL_LOCK] == 1.
4. Disable PLL bypass mode. Set slcr.{ARM, DDR, IO}_PLL_CTRL[PLL_BYPASS_FORCE] = 0.

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5. Disable L2 cache dynamic clock ga ng. Set

l2cpl310.reg15_power_ctrl[dynamic_clk_ga ng_en] = 0.
6. Disable SCU standby mode. Set
mpcore.SCU_CONTROL_REGISTER[SCU_standby_enable] = 0.
7. Disable Interconnect clock stop. Set slcr.TOPSW_CLK_CTRL[CLK_DIS] = 0.
8. Disable Cortex-A9 dynamic clock ga ng. Set
cp15.power_control_register[dynamic_clock_ga ng] = 0.
9. Enable all required peripheral devices, including DDR controller clocks.
10. Re-enable and serve interrupts. Execute cpsie if.

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