Digital Communication Lab Manual Provides Hands-On Learning

Maharaja Agrasen Institute of Technology
(AICTE approved, Affiliated to GGSIPU, Delhi & ISO 9001:2008 Certified )
Lab Manual
Name of Programme – B. Tech.
Subject – Digital Communication Lab
Course code – ETEC-357
Branch – Computer Science and Engineering
Course Status – Mandatory
Semester in which to be taught – V Semester

MAHARAJA AGRASEN INSTITUTE OF
TECHNOLOGY
VISION
To nurture young minds in a learning environment of high academic value and imbibe spiritual
and ethical values with technological and management competence.
MISSION
The Institute shall endeavour to incorporate the following basic missions in the teaching
methodology:
Engineering Hardware – Software Symbiosis: Practical exercises in all Engineering and

Management disciplines shall be carried out by Hardware equipment as well as the related
software enabling deeper understanding of basic concepts and encouraging inquisitive nature.
Life – Long Learning: The Institute strives to match technological advancements and
encourage students to keep updating their knowledge for enhancing their skills and inculcating
their habit of continuous learning.
Liberalization and Globalization: The Institute endeavors to enhance technical and

management skills of students so that they are intellectually capable and competent
professionals with Industrial Aptitude to face the challenges of globalization.
Diversification: The Engineering, Technology and Management disciplines have diverse fields
of studies with different attributes. The aim is to create a synergy of the above attributes by
encouraging analytical thinking.
Digitization of Learning Processes: The Institute provides seamless opportunities for

innovative learning in all Engineering and Management disciplines through digitization of
learning processes using analysis, synthesis, simulation, graphics, tutorials and related tools to
create a platform for multi-disciplinary approach.
Entrepreneurship: The Institute strives to develop potential Engineers and Managers by

enhancing their skills and research capabilities so that they emerge as successful entrepreneurs
and responsible citizens.
DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING
MAHARAJA AGRASEN INSTITUTE OF TECHNOLOGY
VISION
To Produce “Critical thinkers of Innovative Technology”
MISSION
“To provide an excellent learning environment across the computer science discipline to
inculcate professional behavior, strong ethical values, innovative research capabilities and
leadership abilities which enable them to become successful entrepreneurs in this globalized
world.”
 To nurture an excellent learning environment that helps students to enhance their problem
solving skills and to prepare students to be lifelong learners by offering a solid theoretical
foundation with applied computing experiences and educating them about
their professional, and ethical responsibilities.
 To establish Industry-Institute Interaction, making students ready for the industrial
environment and be successful in their professional lives.
 To promote research activities in the emerging areas of technology convergence.
 To build engineers who can look into technical aspects of an engineering solution thereby
setting a ground for producing successful entrepreneur.

Introduction to Digital Communication Lab
The main aim of this lab is to explore digital communication systems at the practical level.
The lab will primarily explain the process of analog to digital conversion mainly the sampling
aspect. During the lab, the students would get acquainted with analog to digital conversion
techniques on various hardware kits. Also, different digital modulation techniques along with
the multiplexing techniques are being dealt in detail. The sole purpose is to provide hands-on
experience to the students so that they are able to put theoretical concepts to practice. At the
end of the course, the student can use these skills in the course of his/her own experimental
research projects in various fields.
Program Outcomes (POs)
Engineering Graduates will be able to:

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering
problems.
2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems
and design system components or processes that meet the specified needs with
appropriate consideration for the public health and safety, and the cultural, societal, and
environmental considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and
research methods including design of experiments, analysis and interpretation of data,
and synthesis of the information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to
assess societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional
engineering solutions in societal and environmental contexts, and demonstrate the
knowledge of, and need for sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or
leader indiverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and
write effective reports and design documentation, make effective presentations, and give
and receive clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a
member and leader in a team, to manage projects and in multidisciplinary
environments.
12. Life-long learning: Recognize the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context of technological
change
Program Specific Outcomes (PSOs)
PSO 1: Professional Skills

To demonstrate basic understanding of engineering fundamentals, professional/social ethics
and apply mathematical foundations to design and solve computational problems.
PSO 2: Problem Solving Skills
An ability to apply algorithmic principles, innovate Computer Science and Engineering
design and implementation skills to provide optimal solutions to complex problems and
provide the platform for research in emerging areas.
PSO 3: Successful Career and Entrepreneurship
Demonstrate ability to communicate effectively with a range of audiences to analyze the local
and global impact of computing on individual organization and society with an aim for
holistic professional development and optimizing resources as an successful Entrepreneur.
Program Educational Objectives (PEOs)
PEO1: To train students to have successful careers in computer engineering field or to be

able to successfully pursue advanced degrees.
PEO2: To imbibe in students an ability to provide solutions to challenging problems in their
profession by applying computer Engineering principles.
PEO3: Train students to communicate effectively, work collaboratively and exhibit high
levels of professionalism and ethical responsibility.
PEO4: To motivate graduates to engage in life-long learning and professional development
to adapt to rapidly changing work environment.
Course Outcome (CO)
ETEC357.1 Demonstrate the concept of Sampling and Quantization.
Experiment with different techniques of analog to digital conversion by

ETEC357.2 inspecting the different performance criteria
ETEC357.3 Develop an understanding of digital multiplexing techniques
ETEC357.4 Demonstrate different digital modulation techniques
ETEC357.5 Compare and classify different line coding techniques
ETEC357.6 Implement the concept of M-ary digital modulation techniques.

INSTRUCTIONS TO THE STUDENTS
1. Students are required to attend all labs.
2. Students will work in a group of two in hardware laboratories and individually in computer
laboratories.
3. While coming to the lab bring the lab file cum observation book, record etc.
4. Take only the lab file, calculator (if needed) and a pen or pencil to the work area.
5. Utilize 3 hours time properly to perform the experiment and noting down the readings. Do the
calculations, draw the graph and take signature from the instructor.
6. If the experiment is not completed in the prescribed time, the pending work has to be done in the
leisure hour or extended hours.
7. You will be expected to submit the completed record book according to the deadlines set up by
your instructor.
8. For practical subjects there shall be a continuous evaluation during the semester. Each Lab
experiment will be evaluated out of 10 marks as per the Lab Assessment Criterion (LAC) Rubrics.
INSTRUCTIONS TO LABORATORY TEACHERS
1. Observation book and lab records submitted for the lab work are to be checked and
signed before the next lab session.
2. Students should be instructed to switch ON the power supply after the connections are checked
by the lab assistant / teacher.
3. The promptness of submission should be strictly insisted by awarding the marks accordingly.
4. Ask viva questions at the end of the experiment.
5. Do not allow students who come late to the lab class.
6. Encourage the students to do the experiments innovatively.
MARKING SCHEME FOR THE PRACTICAL EXAMS
There will be two practical exams in each semester.
Internal Practical Exam
External Practical Exam
INTERNAL PRACTICAL EXAM
It is taken by the concerned lecturer of the batch.
MARKING SCHEME FOR THIS EXAM IS:
Total Marks: 40
Continuous evaluation is undertaken during the semester. Each Lab experiment is evaluated
out of 10 marks as per the Lab Assessment Criterion (LAC) Rubrics.
Grading Rubrics
LAC Experiment Max.
Sr No. Component (LAC) Marks
2 marks 1 mark
Incomplete practical,
Completeness of practical, unformatted, lacks
Practical
LAC 1 2 exhibits proficiency in using comments,
Performance
different types of inputs. Demonstrates no
proficiency.
Output contains few
Output is free of errors and
logical errors and/or
output is obtained.
no output is obtained.
Output and Demonstrates excellent
LAC 2 2 Demonstrates partial
Validation understanding of the
understanding of the
concepts relevant to the
concepts relevant to
experiment.
the experiment.
1. One mark for attendance

Attendance and 2. Three marks for answering more than 75%
LAC 3 Viva Questions 4 questions
Answered
3. Two marks for answering more then 50%
questions.
4. One mark for answering less then 50% questions.
Timely Submission
LAC 4 2 On time submission Late submission
of Lab Record
EXTERNAL PRACTICAL EXAM
It is taken by the concerned lecturer of the batch and by and external examiner. In the exam
student needs to perform the experiments allotted at the time of the examination, a sheet will
be given to the student in which some details asked by the examiner needs to be written and at
the last viva will be taken by the external examiner.
MARKING SCHEME FOR THIS EXAM IS:
Total Marks: 60
Division of 60 marks is as follows:
a. Written Work: 20
b. Viva Voice: 20
c. Experiment performance: 20
NOTE:
Internal Marks + External Marks = Total marks given to the students
(40 marks) (60 marks) (100 marks)
Experiments given to perform can be from any section of the lab.

LIST OF EXPERIMENTS
Paper code: ETEC 357 P C
Paper: Digital Communication Lab 2 1
1. To perform Signal Sampling and Reconstruction Techniques.

2. To perform Time Division Multiplexed – Pulse Code Modulation transmission and
reception.
3. To perform Delta Modulation & Demodulation.
4. To perform Adaptive Delta Modulation & Demodulation.
5. To perform Differential Pulse Code Modulation & Demodulation.
6. To perform different Line Codes – NRZ-L, NRZ-M, RZ, Biphase (Manchester),
Biphase (Mark) and AMI.
7. To perform ASK Modulation & Demodulation.
8. To perform PSK Modulation & Demodulation.
9. To perform FSK Modulation & Demodulation.
10. To perform QPSK Modulation & Demodulation.
LIST OF EXPERIMENTS BEYOND CURRICULUM

11. To perform Analog Time Division Multiplexing & Demultiplexing and also Digital
Time Division Multiplexing & Demultiplexing.
12. To perform QAM Modulation & Demodulation
DIGITAL COMMUNICATION LAB (ETEC-357)
V SEMESTER (ECE, CSE)
LIST OF EQUIPMENTS
S. No. Name of Equipment Model & Make Qty. Cost
Scientech (ST-2101) 1 7260

1 Sampling Reconstruction Trainer Scientech (ST-2151) 1 7125
2 (a) TDM/PCM Tx. Trainer Scientech (ST-2103) 1 12375
2 (b) TDM/PCM Rx. Trainer Scientech (ST-2104) 1 12375
Delta Adaptive delta & delta sigma Scientech (ST-2105) 1 15375

3 Scientech (ST-2105) 1 15375
mod/Demodulation Trainer
Excel Technology 2 14500
Scientech (ST2113) 1 15437
4 DPCM Trainer
Data formatting & Carrier Scientech (ST2106) 1 12375
5 (a)
modulation Tx Trainer Scientech (ST2106) 1 16060
Data formatting & Carrier Scientech (ST2107) 1 12375
5 (b)
modulation Rx Trainer Scientech (ST2107) 1 16060
ASK,FSK & DBPSK Mod. & Scientech (ST2807) 1 16625
6
Demodulation Trainer
TDM-Time Division Multiplexing
7
Trainer

8 QAM Trainer Kit Scientech (ST-2136) 1 22125
9 (a) Block Code Encoder Trainer Scientech (ST2121A) 1 16625
9 (b) Block Code Decoder Trainer Scientech (ST2121B) 1 16625
Error Det. & Correction Cyclic Code

10 Scientech (ST2120) 1 15675
Trainer
Scientech (DSO-7040C) 1 37125
Scientech (DSO-7040C) 1 37125

11 Digital Storage OSC Scientific ( SM-5045) 1 25175
Scientific ( SM-5045) 1 25175
Scientech (ST-201C) 12712
12 CRO Scientific (SM-410) 11 20000
Scientific (HM-203) 26000
13 Data Logger (SI-232) 4
Scientech
14 Function Generator 5
Scientific
15 Power Supply Multiple
DIGITAL COMMUNICATION LAB (ETEC-357)
V SEMESTER (ECE, CSE)
LIST OF SOFTWARE & HARDWARE
S. No. Name of Equipment Model & Make Quantity Cost
1 CPU 1
2 UPS 2
(LG- 04)
3 TFT 5
(HP- 01)
(LG-05)
4 KEY BOARDS 6
(HP-01)
5 MOUSE 6
COMMSIM
6 1
SOFTWARE
TABLE OF CONTENTS
S. Page
Experiment
No. No.
1 Expt. 1- To perform Signal Sampling and Reconstruction Techniques. 1
Expt. 2- To perform Time Division Multiplexed Pulse Code Modulation

2 12
transmission and reception.
3 Expt. 3- To perform Delta Modulation and Demodulation. 30
Expt. 4- To perform Adaptive Delta Modulation and Demodulation.
4 42
Expt. 5- To perform Differential Pulse Code Modulation and
5 Demodulation. 49
Expt. 6- To perform different Line Codes – NRZ-L, NRZ-M, RZ, Biphase
6 (Manchester), Biphase (Mark) and AMI. 56
Expt. 7- To perform Amplitude Shift Keying Modulation and
7 Demodulation. 65
Expt. 8- To perform Phase Shift Keying Modulation and Demodulation.

8 71
Expt. 9- To perform Frequency Shift Keying Modulation and
9 Demodulation. 79
Expt. 10- To perform Quadrature Phase Shift Keying Modulation and
10 Demodulation. 85
Expt. 11- To perform Analog Time Division Multiplexing &

Demultiplexing and also Digital Time Division Multiplexing &
11 97
Demultiplexing.
Expt. 12- To perform Quadrature Amplitude Modulation and

12 Demodulation. 102
Experiment 1
Objective:
To perform Signal Sampling and Reconstruction Techniques.
Equipment Required:
1. 2101 with power supply cord
2. CRO with connecting probe
3. Connecting cords
Theory:
The signals we use in the real world, such as our voice, are called "analog" signals. To
process these signals for digital communication, we need to convert analog signals to
"digital" form. While an analog signal is continuous in both time and amplitude, a
digital signal is discrete in both time and amplitude. To convert continuous time
signal to discrete time signal, a process is used called as sampling. The value of the
signal is measured at certain intervals in time. Each measurement is referred to as a
sample.
Principle of sampling
Consider an analogue signal x(t) that can be viewed as a continuous function of time,
as shown in Figure 1.1. We can represent this signal as a discrete time signal by using
values of x(t) at intervals of nTs to form x(nTs) as shown in Figure 1.1. We are
"grabbing" points from the function x(t) at regular intervals of time, Ts, called the
sampling period.
Figure 1.1 Basic Sampling Process
1
Figure 1.2 Sampling of signal at sampling interval (period) Ts
Figure 1.2 depicts the sampling of a signal at regular interval (period) t =nTs where n
is an integer. The sampling signal is a regular sequence of narrow pulses δ (t) of
amplitude 1. Figure 1.3 shows the sampled output of narrow pulses δ (t) at regular
interval of time.
Figure 1.3 Sampled Output of narrow pulses δ (t)
The time distance Ts is called sampling interval or sampling period, fs=1/Ts is

called as sampling frequency (Hz or samples/sec), also called sampling rate.
2
The Sampling Theorem
The Sampling Theorem states that a signal can be exactly reproduced if it is sampled
at a frequency Fs, where Fs is greater than twice the maximum frequency Fmax in the
signal.
Fs > 2· Fmax
The frequency 2· Fmax is called the Nyquist sampling rate. Half of this value, Fmax, is
sometimes called the Nyquist frequency.
The sampling theorem is considered to have been articulated by Nyquist in 1928 and
mathematically proven by Shannon in 1949. Some books use the term "Nyquist
Sampling Theorem", and others use "Shannon Sampling Theorem". They are in fact
the same sampling theorem.
The sampling theorem clearly states what the sampling rate should be for a given
range of frequencies. In practice, however, the range of frequencies needed to
faithfully record an analog signal is not always known beforehand. Nevertheless,
engineers often can define the frequency range of interest. As a result, analog filters
are sometimes used to remove frequency components outside the frequency range of
interest before the signal is sampled.
For example, the human ear can detect sound across the frequency range of 20 Hz to
20 KHz. According to the sampling theorem, one should sample sound signals at least
at 40 KHz in order for the reconstructed sound signal to be acceptable to the human
ear. Components higher than 20 KHz cannot be detected, but they can still pollute the
sampled signal through aliasing. Therefore, frequency components above 20 KHz are
removed from the sound signal before sampling by a band-pass or low-pass analog
filter.
Procedure:
A. Set up for Sampling and reconstruction of signal.

Initial set up of trainer:
Duty cycle selector switch position: Position 5 (to set 50% duty cycle)
Sampling selector switch : Internal position
1. Connect the power cord to the trainer. Keep the power switch in ‘Off’ position.
2. Connect 1 KHz Sine wave to signal Input.
3. Switch ‘On’ the trainer's power supply & Oscilloscope.
4. Connect BNC connector to the CRO and to the trainer’s output port.
5. Select 320 KHz (Sampling frequency is 1/10th of the frequency indicated by the
illuminated LED) sampling rate with the help of sampling frequency selector
switch.
6. Observe 1 KHz sine wave (TP12) and Sample Output (TP37) on Oscilloscope.
The display shows 1 KHz Sine wave being sampled at 32 KHz, so there are 32
3
samples for every cycle of the sine wave. (figure 1.1)
7. Connect the Sample output to Input of Fourth Order low pass Filter & observe
reconstructed output on (TP46) with help of oscilloscope. The display shows the
reconstructed original 1 KHz sine wave. (figure 1.2)
8. By successive presses of sampling Frequency Selector switch, change the
sampling frequency to 2KHz, 4KHz, 8KHz, 16KHz and back to 32KHz
(Sampling frequency is 1/10th of the frequency indicated by the illuminated
LED). Observe how SAMPLE output changes in each cases and how the lower
sampling frequencies introduce distortion into the filter’s output waveform. This
is due to the fact that the filter does not attenuate the unwanted frequency
component significantly. Use of higher order filter would improve the output
waveform.
9. So far, we have used sampling frequencies greater than twice the maximum
input frequency.
Result:
As the sampling frequency increases the output of sample port has more number of
samples of applied input signal.
B. Setup for sample and hold output & reconstructed signal output.
1. Repeat the first five steps as above.

2. Connect Sample & Hold output to Fourth Order low pass Filter's Input. Set the
Duty Cycle Selector switch to position 5. (figure 2.1)
3. Observe the waveform at Sample & Hold output (TP39) on oscilloscope. Vary
the sampling frequency selector from 32 KHz to 2 KHz to illustrate how each
sample is held at the sample/hold output. Also observe the filter output at TP46.
(figure 2.2)
4. Vary the position of Duty Cycle Selector switch from 0 to 9 and note that in
contrast to step 7, the filter's output amplitude is now independent of the
sampling duty cycle and is equal to the amplitude of the original input signal.
This is an important result - with Sample and Hold Output, the proportion of
sampling time to holding time has no effect on reconstructed waveform
provided that Nyquist criteria has been followed. If sample/hold feature is
utilized in digital communication system many channels can be multiplexed
with maximum amplitude of reconstructed signal.
Result:
For transmitting the signal if a sample and hold amplifier is used just before the
transmission channel, the signal will be less suffered from distortion as
compared to when only sample amplifier is used.
4
C. Comparison of frequency response of 2nd order and 4th order low pass filter.
1. Repeat the first five steps above.
2. Connect sample output to input of the Second Order Low Pass Filter and to the
input of Fourth Order Low Pass Filter respectively. Observe the outputs of two filters
(TP42 and 46 respectively) on the oscilloscope. Vary the sampling frequency with
duty cycle set at 5 positions. Compare the output of filter in each case. Note, that the
output of fourth order filter always exhibits less distortion than second order filter.
This is because fourth order filter has a sharper roll-off and thus rejects (attenuates)
more unwanted frequency components caused by sampling.
3. Repeat the above procedure with sample and hold circuitry. Observe that the output
exhibits less distortion as compared to output in case of sample circuitry.
Result:
The output of IV order LPF will reconstruct the recovered signal more like the
transmitted signal. In both the cases of either sample amplifier or sample and hold
amplifier, when the order is increased the output retrieved is better.
5
Connection Diagram: Signal Sampling
Figure 1.4 Signal Sampling
6
Diagram: Signal Reconstruction
Figure1.5 Signal Reconstruction
7
Connection Block Diagram: for Sample /Sample and Hold output
Figure 1.6 Sampled O/P and Sample & Hold O/P
8
Connection Block Diagram: for Sample & Hold O/P and LPF O/P
Figure 1.7 Sample & Hold O/P & LPF O/P
9
Connection Block Diagram: for Low Pass Filter O/P
Figure 1.8 Low Pass Filter O/P
10
Viva Voce Questions
1. What do you mean by sampling?
2. What is sampling theorem?
3. What is Nyquist frequency?
4. List different sampling techniques?
5. What is under sampling?
6. What do you mean by aliasing?
11
Experiment 2
Objective:
To perform Time Division Multiplexed Pulse Code Modulation transmission and
reception.
Equipment Required:
1. 2153 and 2154 with power supply cord
3. Connecting cords
Theory
Time Division Multiplexing
Time division multiplexing is a technique of transmitting more than one information
on the same channel. As can be noticed from the figure 2.1 below the samples consists
of short pulses followed by another pulse after a long time intervals. This no-activity
time intervals can be used to include samples from the other channels as well. This
means that several information signals can be transmitted over a single channel by
sending samples from different information sources at different moments in time. This
technique is known as time division multiplexing or TDM. TDM is widely used in
digital communication systems to increase the efficiency of the transmitting medium.
TDM can be achieved by electronically switching the samples such that they inter
leave sequentially at correct instant in time without mutual interference. The basic 4
channel TDM is shown in next figure 2.1.
The switches S1 & S2 are rotating in the shown direction in a synchronized manner,
where S1 is sampling channel to the transmission media. The timing of the two
switches is very important to ensure that the samples of one channel are received only
by the corresponding channel at the receiver. This synchronization between S1 & S2
must be established by some means for reliable communication. One such method is
to send synchronization code (information) along itself to the transmitter all the time.
In practice, the switches S1 & S2 are simulated electronically.
12
Figure 2.1 Principle of 4-Channel TDM System
Bit 0: This bit is reserved for the synchronization information generated by the Pseudo
random sync code generator block more about its operation in the later section. When
the Pseudo Random Sync Code is switched OFF a '0' is transmitted.
Bit 1 to 7: These carry a 7 bit data word corresponding to the last sample taken from
the analog channel CH.I Remember that the TechBook transmits lowest significant bit
(LSB) first. This time interval during which the coded information regarding the
analog information is transmitted is called as the timeslot. Since the present timeslot
corresponds to channel 0 it is known as timeslot 0.
Bit 8 to 14: This timeslot termed as timeslot 1 contains the 7 bit word corresponding
to the last sample taken of analog channel1. As with channel 0 the least significant bit
is transmitted first. The receiver requires two signals for its correct operation &
reliable communication, namely.
● Receiver clock operating at the same frequency as that of the transmitter clock.
● Synchronization signal which allows the receiver to synchronies its

clock/operation with the transmitter’s clock operation. All these requirements can
be achieved by transmitting two essential information signals:
I. A Transmit clock signal.

II. A Frame synchronization signal.
The simplest method is to transmit the synchronization information & the clock over a
separate transmission link. This results in a simplest receiver. It is used in data
communication LAN (Local Area Network) & in telemetry systems. However it is
waste of media & is not economical for long distance communications.
13
Procedure:
Set up the following initial conditions on Scientech 2153:
● Mode Switch in 320 KHz (FAST mode) position
● DC signal (I) & DC signal (II) Controls in function generator block fully
clockwise.
● ~ 2 KHz and ~4 KHz control levels set to give 10Vpp.
● Pseudo - random sync code generator on/off switch in OFF Position.
● Error check code generator switch A & B in A=0 & B=0 position (OFF
Mode)
● All switched faults off.

First, connect only the 2 KHz output to CH I
Turn ON the power. Check that the PAM output of 2 KHz sine wave is available
sample and hold input of the Scientech 2153.
Connect CH1(Y) of the oscilloscope to ‘CH I sampling signal’ output of De-

multiplexer block & CH2(X) of the oscilloscope to input of sample and hold
block. Observe the timing & phase relation between the CH I sampling signal &
the sampled waveform at input of Sample & hold block.
Figure 2.2 ‘CH I sampling signal’ & Sample and Hold output in Dual
Mode
14
Figure 2.3 ‘CH II sampling signal’ & Sample and Hold output in Dual
Mode
Turn OFF the power supply. Now connect also the 4 KHz supply to CH II.
Connect CH1(Y) of the oscilloscope to ‘CH II sampling signal’ output of
Demultiplexer block & CH2(X) of the oscilloscope to input of sample and hold
block.
Observe & explain the timing relation between the signals at
● CH I sampling signal,
● 2 KHz Sine wave of Function Generator,
● 4 KHz Sine wave of Function Generator,
● CH II sampling signal,
● Multiplexed output at input of Sample and hold block
Figure 2.4 CHI input and Sample and hold output when only one input
signal is present
15
Figure 2.5 CHII input and Sample and hold output when only one input
signal is present
16
Objective:
Study of Three Modes of Transmission
Procedure:
Set up following initial conditions on the Scientech 2153:
● Mode Switch in 320 KHz (FAST mode) position.

● DC signal (I) & DC signal (II) controls in function generator block fully
clockwise.
● Pseudo random sync code generator switched 'OFF'.
● Error check code selector switches A & B in A=0 & B=0 Position.
● All switched faults off.

Set up following initial conditions on Scientech 2154:
● Mode Switch in 320 KHz (FAST mode) position.

● Pseudo random sync code detector switched OFF.
● Error check code selector switches A & B in A=0 & B=0 position.
● All switched faults 'off'.
● Pulse generator delay adjusts control in fully clockwise position.
17
Connection Diagram:
Figure 2.6 Mode 1
18
Mode 1: 3 Wire communication between Transmitter & Receiver
Make connections as shown in figure 2.6
● ON Scientech 2153:
I. ~2 KHz Signal to CH I Input.
II. ~4 KHz Signal to CH II Input.
● Between Scientech 2153 & Scientech 2154,
Scientech 2153 Scientech 2154

Tx. Clock output Rx. Clock input
Tx. TO output Rx. TO input
PCM output PCM data input
Turn ON the power. Observe that the 2 KHz sine wave input appears at
CHIinput & 4 KHz sine wave input appears at CH II input.
Connect
CH1(Y) of oscilloscope to CH I unity gain buffer amplifier’s output at
transmitter
CH2(X) of oscilloscope to Low pass filter CH1 output at receiver

Trigger the oscilloscope with CH I input. Observe the two waveforms. Vary the
Transmitter’s ~2 KHZ and ~4 KHz controls (which vary the amplitude of the
two sine waves) and note how the transmitter data changes.
Figure 2.7 Output Waveforms at Low Pass filters of Scientech 2154 when
connected in 3 wire link with input as 2 KHz on both channel
19
Display TX clock ofScientech 2153& RX Clock ofScientech 2154on
twochannels of the oscilloscope. Notice that the two outputs are identical to that
transmitter and the receiver. Observe the receiver channel output with the
corresponding transmitter channel input on a dual trace oscilloscope. The output may
get flattened at peaks if the input sinusoidal signal voltage exceeds 10Vpp. This is
because the input exceeds the dynamic range of the A/D Converter. Vary the
amplitude of the input signal observe that the same changes are reflected at the
receiver.
Figure 2.8 Tx clock input TP45 of Scientech 2153 and Regenerated clock
(TP8) of Scientech 2154
Mode 2: 2 Wire communication between Transmitter & Receiver
● Switch the boards to 320 KHz (FAST mode)
● Remove the link connecting Tx. TO & Rx. TO.
● Switch ON the pseudo random sync code generator on Scientech 2153.
● Switch ON the pseudo random sync code detector on Scientech 2154.
● Connect DC signal (I) to CH I & CH I to CH II
The above mode is termed as 'connecting Mode 2'.

The transmitter / Receiver can be configured in this mode as shown in next figure 2.9.
20
Figure 2.9 Mode 2 
21
Turn ON the power. Vary the DC signal (I) control. Observe on the
oscilloscopeat CH I output. The amplitude should vary between -5V to + 5V.
Variation of the input voltage from -5V to +5V will cause the output of A/D
Converter to vary from 00 Hex to 7F Hex. The A/D converter 7 Bit word output
can be monitored on LED's provided in the A/D converter block.
Observe that the D/A Converter LED contain the same data for a particular set
of input amplitude. Notice the output waveform at CH I Low pass filter or CH II
Low pass filter output of Scientech 2154.
The sequence of operation onScientech 2153is fully synchronized to the

TX.clock signal. This clock signal can be monitored at Rx TO. Each clock
cycle is known as timeslot. The operations of the TechBook repeat after 15
timeslots. These 15 timeslots are collectively called as 'Timing Frame'. The start
of the timing frame or Bit 0 is indicated by high level at Tx. TO output. The data
appears at the output logic block at the start of each timeslot. The output logic
block adds a half timeslot delay to it. Thus the TDM PCM output of output logic
block contains transitions halfway through each timeslot. The information
appearing at the middle of the timeslots is as follows.
BIT 0: This carries the synchronization information (sync. code). The Pseudo
random sync code generator outputs a single bit in this timeslot. Since the
length of the code is 15 bits, the Sync code repeats after 15 timing frames. At
this instance the pseudo random sync code generator is OFF, a '0' is transmitted
in this timeslot.
BIT 1 to 7: These bits carry the 7 Bit data word of the last sample taken from
the channel o. Notice that the least significant bit (LSB) is transmitted first.
BIT 8 to 14: These bits carry the 7 bit data word of the last sample taken from
channel 1. In this case also the least significant bit is transmitted first.
Observe the PCM output with respect to the input signal to output logic block &
with Tx. clock signal.
As it has been discussed earlier, for correct operation the receiver needs to
beclocked" at the same rate as the transmitter & it should be able to decide
which timeslot is for which information transmit Tx. Clock & Tx. TO signals on
separate links. Tx. Clock signals clocks the receiver at the same rate whereas the
Tx. TO signal helps the receiver to identify the timeslot 0.
The three wire connections can be reduced to two wires by developing

transmitter's ability to transmit the synchronization information along the data.
22
Similarly, the receiver must be able to detect & distinguish these sync bits from
the normal information bits.
This ability is imparted by the Pseudo random sync code generator & detector
present on transmitter & receiver TechBook respectively. The pseudo random
sync code is a sequence of 15 bits generated by the pseudo random sync code
generator.
0 0 0 1 0 0 1 1 0 1 0 1 1 1 1 .............................................................. Repeating.
One bit of this sequence is transmitted in every frame at timeslot 0. The receiver
detects it & use it to decide which timeslot is for which.
Figure 2.10 Low pass filter input CH I & low pass filter input CH II of
Scientech 2154 when connected in 2 wire link with input as 2 KHz on both
channel
Figure 2.11 Low pass filter output CH I & low pass filter output CH II of
channel When sync is removed
23
Vary DC signal (I) and note that the LED's on the A/D converter block
onScientech 2153 & D/A converter of Scientech 2154 always carries the
same code.
Also observe that the sync bit counter LED in the pseudo random sync code
detector block is 'ON'. This signifies that the receiver knows the transmitted
timeslot & can identify them. We say that the receiver is 'Frame Synchronized'
to the transmitter. Once the transmitter & receiver are frame synchronized, the
Tx. TO & Rx. TO signals are identical. You can observe the two waveform at
Tx TO of Scientech 2153 & at RX TO of Scientech 2154 respectively.
Switch OFF the pseudo random sync code generator. Notice that the
A/Dconverter block output observed on LED's is not similar to the D/A
Converter Block input. We say that the receiver has lost the frame
synchronization. The Receiver indicates this by turning 'OFF' the sync bit
counter led in pseudo random sync code detector block.
If you desire to examine the timing of data flow & control signal in
detail,switch the transmitter & receiver into SLOW mode.
Figure 2.12 Low pass filter output CH I & low pass filter output CH II of
channel when sync is ON with same input
Mode 3: Single Wire Communication

Configure the transmitter & receiver as shown in next figure 2.13 and ensure the
following statements:
● Both TechBooks are switched in 320 KHz (FAST mode)

● Link between Tx. Clock & Rx. Clock has been removed.
● PCM data input on TDM PCM Receiver is connected to the input of phase
locked loop circuit on the same TechBook.
● The phase locked loop output is connected to the Rx. Clock input on the
Scientech 2154.
24
Figure 2.13 Mode 3
25
Before operating in connecting Mode 3 it may necessary to trim the voltage controlled
oscillator (VCO) frequency, so that the regenerated clock remains in synchronization
with the incoming data even when few transitions occur. (This happens when there is
a long stream of '0's to '1's in the. NRZ (L) waveform).
Follow the procedures given below to trim the VCO frequency:
● Turn the DC signal (I) control in the function generator block on Scientech
2153 fully clockwise.
● Slowly, turn the VCO frequency adjust control on Scientech 2154 until the
sync bit counter led in the pseudo random sync code detector block turns
ON.
● Repeat the above steps till position of the control is found such that the
sync bit counter led remains ON for both fully clock wise & anticlockwise
positions of the DC signal (I) control.
At the transmitter, remove the CH.I & CH.II inputs & connect
● ~ 2 KHz Signal to CH.I input

● ~ 4 KHz Signal to CH.II input.
Note: Turn 'OFF' the power when new connections are made or disconnected.
Adjust the outputs of the two generators to 8 Vpp by the amplitude controls
provided in the Function generator block. You can observe the two signals at
CH 1 & CH II inputs.
Observe the receiver analog outputs. Verify that the two outputs are identical
tothat applied at the transmitter's inputs.
The TechBooks have on board error check generator & detector (on TDM
PCMtransmitter & Scientech 2154 respectively). This provides an
opportunity to detect & if possible to correct the erroneous TechBook data. The
Error check code generator replaces some least significant bits of the 7 Bit word
with some error check bits. The following error check options are available on
board:
 Off: The error check generator is 'OFF' when this mode is selected by
switching the A & B switches in the error check code generator block in
Scientech 2153 in A = 0 & B = 0 position.
No error check code is inserted in the 7 Bit word. The word format is
D7 D6 D5 D4 D3 D2 D1
Where D7-D1 are the A/D Converters latched outputs.

 Even Parity: This option is selected by placing A & B switches in the error
check code generator block in Scientech 2153. In A = 0 & B=1 position. The
least significant bit of the 7 bit word is replaced by a single parity bit.
26
The word format is:
D7 D6 D5 D4 D3 D2 C1
Where C1 is the parity check bit which is chosen such that the total no of '1's
in the 7 bit word are even. If the error check code detector in Scientech 2154
is also configured in this mode, it can detect the error in the transmitted data,
but it cannot tell which bit is in error. It indicates 'the error by switching 'ON'
of the Parity Error LED.

 Odd Parity: This option is selected by placing the A & B switches in the
error check generator block in A = l & B = 0 position. The least significant
bit of the 7 - Bit word is replaced by a single parity bit.
The word format is.
D7 D6 D5 D4 D3 D2 C1
Where C1 is the parity check bit such that the total no of '1's in the 7 bit word
are odd.
If the error check code detector in Scientech 2154 is also included in this
mode, it can detect the error in the transmitted data, but cannot tell which bit
is in error. It indicates the error by switching 'ON' of the parity error LED.

 Hamming Code: This option is selected when the A & B switches in the
Error check code generator on Scientech 2153 are placed in A=1 & B=1
position.
In this case the three check bits replace the three least significant bits of the
7 bit word. The word format is:
D7 D6 D5 D4 C3 C2 C1
Where C3, C2 & C1 are the Hamming check bits. If the Error Check Code
Detector in Scientech 2154 is switched into same .mode, it can detect the
error & even connect the erroneous transmitted data bit (only single). It
indicates the erroneous bit by lighting the corresponding LED in hamming
code error block. Illustration of various check codes are given in steps 22 nd
to 29th.
Connect the receiver's CH.I output & CH.II output to the two channels of
theoscilloscope. Now introduce the switched fault '2' in the TechBook
system by switching ON the pole 2 of switched faults Block. This fault
forces the D7 bit (MSB) of the transmitted 7 bit word to be always '1' even
when there must have been a '0'. Notice the distortion in the output in the
output sine waves at the receiver's CH I output & CH II output.
27
Switch OFF the fault. Introduce even parity error check code option on both
theTechBooks by switching the A & B switches in the corresponding block to
A=0 & B=1 position.
Observe the two output waveforms at TDM PCM Receiver's CH I & CH

IIoutputs are distortion less & also observe the LED's in the error check code
detector block are 'OFF'.
Switch ON fault '2' again.

Observe that the parity error indicator LED in error check code detector glows
i.e. the receiver has detected the error in transmitted data but is not in a position
to locate which bit is in error. Therefore the output at CH.I & CH.II on
Scientech 2154 still remains distorted.
You can carry the same experiment by selecting odd parity option. You will
getthe same result as the earlier ones. Note switch off the fault prior to
selecting the Error check code option.
Switch 'OFF' the fault. Select the hamming code option by placing the A &
Bswitches in the corresponding block to A = 1 & B = 1 position.
Switch 'ON' fault '2'\

Observe that the D7 LED marked in error check code detector's hamming code
error bit glows. Since its 3 bit hamming code, it can detect as well as correct
one bit error in a sample. It reveals the erroneous bit in the data format by
lighting the corresponding LED (D7 in the present case). Notice, now that the
outputs at CH.I & CH.II on TDM PCM Receiver are now distortion less. This is
because the erroneous bit has even been corrected by the receiver.
Result: All the three modes of transmission in TDM-PCM are verified and
TDM_PCM Transmission and Reception is done.
28
Viva Voce Questions
1. Write the advantages of TDM?
2. What is Crosstalk?
3. When do you prefer TDM to FDM?
4. Define the term ‘Frame’ in case of TDM?
5. Is TDM a digital technique of encoding, decoding, multiplexing or
demultiplexing?
29
Experiment 3
Objective:
To perform Delta Modulation and Demodulation.
Equipment Required:
1. ST2105 with power supply cord
3. Connecting cords
Theory
Delta modulation is a system of digital modulation developed after pulse code

modulation. In this system, at each sampling time, say the Kth sampling time,
the difference between the sample value at sampling time K and the sample
value at the previous sampling time (K-1) is encoded into just a single bit. i.e.
at each sampling time we ask simple question.
Has the signal amplitude increased or decreased since the last sample was
taken?
If signal amplitude has increased, then modulator's output is at logic level 1.
If the signal amplitude has decreased, the modulator output is at logic level 0.
Thus, the output from the modulator is a series of zeros and ones to indicate
rise and fall of the waveform since the previous value. One way in which delta
modulator and demodulator is assembled is as show in figure 3.1 and figure
3.2.
Figure 3.1 Delta Modulator
30
Figure 2.2 Delta Modulator
Working of Delta Modulator:
The analog signal which is to be encoded into digital data is applied to the
+ve input
of the voltage comparator which compares it with the signal applied to its - ve
input from the integrator output (more about this signal in forth coming
paragraph).
The comparator's output is logic '0' or '1' depending on whether the input
signal at +ve terminal is lower or greater then the -ve terminals input signal.
The comparator's output is then latched into a D-flip- flop which is clocked
by the transmitter clock. Thus, the output of D-flip-Flop is a latched 'l' or '0'
synchronous with the transmitter clock edge.
This binary data stream is transmitted to receiver and is also fed to the
unipolar to bipolar converter. This block converts logic '0' to voltage level of
+ 4V and logic 'l' to voltage level - 4V.
The Bipolar output is applied to the integrator whose output is as follows:
a. Rising linear ramp signal when - 4V is applied to it, (corresponding to
binary 1)
b. Falling linear ramp signal when + 4V is applied to it (corresponding to
binary 0).
The integrator output is then connected to the -ve terminal of voltage
comparator, thus completing the modulator circuit.
Let us understand the working of modulator circuit with the analog input
waveform applied as below:
31
Figure 2.3 Technique of Delta Modulation
Suppose at some time-instance t = 0, the integrator output voltage is lower than

the analog input. This causes the voltage comparator voltage to go high i.e. logic
'1'. This data is latched in the D- Flip- Flop at the rising edge of transmitter
clock., The latched '1' output of D- flip is translated to - 4V by the unipolar to
bipolar converter block. The integrator then ramps up to catch analog signal.
At the next clock cycle t = 1, the integrator output becomes more than the
analog input, so a '0' is latched into D-Flip -Flop. The integrator now ramps
downward as +4V voltage signal from unipolar to bipolar converter appears at
its input. Thus, the ramp signal again tries to catch the fallen analog signal.
As we can observe, after several clock cycles the integrator output is
approximation of the analog input which tries to catch up the analog input at
each sample time. The data stream from D-flip-flop is the delta modulators
output.
The delta demodulator consists of a D- Flip-Flop a unipolar to bipolar
converter followed by an integrator and a low pass filter. The delta
demodulator receives the data from D-Flip-Flop of delta modulator. It latches
this data at every rising edge of receiver clock, which is delayed by half clock
period with respect to transmitter clock.
This has been done so that the data from transmitter may settle down before
being latched into the receiver Flip-Flop.
The unipolar to bipolar converter changes the output from D-Flip-Flop to either
- 4V or + 4V for logic '1' and '0' respectively.
As it has been seen in case of modulator when the output from unipolar to
bipolar converter is applied to integrator, its output tries to follow the analog
signal in ramp fashion and hence is a good approximation of the signal itself.
The integrator's output contains sharp edges, which are 'smoothened out' by the
low - pass filter, whose cut-off frequency is just above the audio band.
Delta modulation offers many advantages as listed below
32
 Simple system / circuitry
 Cheap
Single bit encoding allows us to increase the sampling rate or to transmit more
information at some sampling rate for given system bandwidth.
Unfortunately, the practical use of delta modulation is limited due to the
following several drawbacks.
a. Noise
Noise is defined as any unwanted unpredictable random waveform
accompanying the information signal. Whenever the signal is received
at the received by any communication medium, it is always
accompanied by noise.
b. Distortion
Distortion means that the receiver's output is not the true copy of the
analog input signal at the transmitter.
Distortion in delta modulation occurs due to following causes:
As it has been seen, when the analog signal is greater then the integrator
output, the integrator ramps up to meet the analog signal. The ramping rate of
integrator is constant. Therefore, if the rate of change of analog input is faster
than the ramping rate, the modulator is unable to catch up with the information
signal. This causes a large disparity between the information signal and its
quantized approximation. This error / phenomenon is known as slope -
overloading and causes the loss of rapidly changing the information.
Figure 3.4 Information Loss due to Rapid input Changes
At first it may look as though the problem of slope overloading can be solved
increasing the ramping rate of the integrator. But as it can be seen from the
figure 3.4 the effect of the large step-size is to add large sharp edges at the
integrator output and hence it adds to noise problem faced at receiver. This
effect itself leads to distorted receiver output.
Increasing sampling rate cannot be the solution to the slope - overloading
problem as it determines how fast the samples are taken and not the ramping
rate of the integrator.
33
Figure 3.5 Effect of Sampling Rate on Quantization Noise &
Step-
Procedure:
1. Connect the mains supply.
2. Make connection on the board as shown in the figure 3.7.
3. Ensure that the clock frequency selector block switches A & B are in A =
0 and B = 0 position.
4. Ensure that integrator 1 block's switches are in following position:
a) Gain control switch in left-hand position (towards switch A & B).
b) Switches A & B in A=0 and B=0 positions.
5. Ensure that the switches in integrator 2 blocks are in following position:
a) Gain control switch in left-hand position (towards switch A & B)
b) Switches A & B are in A = 0 and B = 0 positions.
6. Turn 'ON' of the trainer.
7. In order to ensure for correct operation of the system, we first take the
input to 0V. So connect the '+' input of the delta modulator's voltage
comparator to 0V and monitor on an oscilloscope the output of integrator
1 (TP17) and the output of the transmitter's level changer (TP15)
If the transmitter's level changer output has equal positive and negative
output levels. Integrator’s output will be a triangle wave centered around
'0' Volts, as shown in figure 3.6 (Case A). However, if the level changer's
negative level is greater than the positive level, the integrator's output will
appear as shown in figure 3.6 (Case B). Should the level changer's
positive output level be the greater of the two levels, the integrator's
output will resemble that shown in figure 3.6 (Case C).
8. The relative amplitudes of the level changer’s positive and negative
output levels can be varied by adjusting the level adjust present in the
34
bistable and level changer circuit 1 block when it is turned anticlockwise,
the negative level increases relative to the positive level, when turned
clockwise, the positive level increases relative to the negative.
Prove that you can obtain all the three waveforms shown in figure 3.6 by
turning the potentiometer from one extreme to another. Try explaining
the reason behind it.
Case A: Bipolar output – Positive level = Negative level
Case B: Bipolar output – Positive level < Negative level
35
Case C: Bipolar output – Positive level > Negative level
Figure 3.6
9. Adjust the transmitter's level changer preset until the output of integrator
1 (TP17) is a triangle wave centered around 0 Volts, as shown in figure
3.6 (Case A). The peak-to-peak amplitude of the triangle wave at the
integrator's output should be 0.5V (approximately), this amplitude is
known as the integrator step size.
The output from the transmitter's bistable circuit (TP14) will now be a
stream of alternate '1' and '0', ‘s' this is also the output of the delta
modulator itself. The delta modulator is now said to be 'balanced' for
correct operation.
10. Examine the signal at the output of integrator 2 (TP47) at the receiver.
This should be a triangle wave, with step size equal to that of integrator 1,
and ideally centre around 0 Volts. If there is any DC bias at the output of
integrator 2, remove it by adjusting the receiver's level adjust preset (in
the bistable & level changer circuit 2 block). This preset adjusts the
relative amplitudes if the positive and negative output levels from the
receiver's level changer circuit only when these levels are balanced will
there be no offset at the output of integrator2.
36
Figure 3.7
37
11. Disconnect the voltage comparators '+' input from 0V, and reconnect it to
the ~250Hz output from the function generator block; the modulator's
analog input signal is now a 250Hz sine wave.
Monitor this analog signal at the voltage comparator's '+' input TP9 trigger
the scope on this signal together with the output of, integrator 1 (TP17)
Note how the output of the transmitter' integrator follows the analog input,
as was illustrated in figure 3.1.
Note :- It may be necessary to readjust slightly the transmitter's level adjust
preset (in the bistable & level changer circuit 1 block) in order to obtain a
stable, repeatable trace of the integrator's output signal.
12. Display the data of the transmitter's bistable (at TP14), together with the
analog input at TP9 (again trigger on this signal), and note that the 250 Hz
sine wave has effectively been encoded into a stream of data bits at the
bistable's output, ready for transmission to the receiver.
13. For a full understanding of how the delta modulator is working, examine
the output of the voltage comparator (TP11), the bistable's clock input
(TP13), and the level changer's bipolar output (TP15)
14. Display the output of integrator 1 (TP17) and that of integrator 2 (TP47) on
the scope. Note that the two signals are very similar in appearance,
showing that the demodulator is working as expected.
15. Display the output of integrator 2 (TP47) together with the output of the
receiver's low pass filter block (TP51). Note that although the integrator’s
output has been smoothed out somewhat by the low pass filter, some
unwanted 'ripple' still remains at filter's output This 'ripple' is due to
'quantization noise' at the integrator's output, which is caused by the
relatively large integrator step size. This step size can be reduced by
increasing the rate at which the system is clocked (i.e. the sampling
frequency), since this reduces the sampling period, and hence the time
available between samples for the integrators to charges up and down.
16. The current system clock frequency is 32 KHz. This is set by the A, B
switches in the clock frequency selector block, which are currently in the
A= 0, B= 0 positions. While monitoring the same signals, increase the
system clock frequency to 64 KHz, by putting the switches in the A = 0, B
= 1 positions.
Note :- If the integrator's output (TP47) no longer gives a stable trace after
changing the clock frequency, make a slight adjustment to the transmitter's
level adjust preset (in the bistable & level changer circuit 1 block), until the
trace is once again stable.
Notice that, at the integrator's (TP47), the frequency of the triangular error
signal doubles, and the peak-to-peak amplitude of that error signal (i.e. the
step size) is now halved.
38
Examine the ripple at the low-pass filter's output (TP51). Note that this is now less than it
was before.
17. By changing the system clock frequency to first 128 KHz (clock frequency selector
switches in A=l, B=0 positions), and then to 256 KHz (switches in A=l, B=0 positions),
note the improvement in the low - pass filter's output signal (TP51).
Once again, it may be necessary to adjust slightly the transmitter's level adjust preset, in
order to obtain a stable oscilloscope trace.
18. Using a system clock frequency of 256 KHz (which gives a step size of approximately
60mV), compare the low pass filter's output. (TP51) with the original analog input (TP9).
There should now be no noticeable difference between them, other than a slight delay.
19. While continuing to monitor the transmitter's analog input (TP9) and the receiver's low-
pass filter output (TP51), disconnect the comparator's + input from the 250Hz sine wave
output, and reconnect it no the 500Hz, 1 KHz and 2 KHz outputs in turn. Note that, as the
frequency of the analog signal increases, so the low pass filter's output becomes more
distorted and reduced in amplitude.
20. In order to understand what has caused this distortion, leave the comparator's + input
connected to the 2 KHz sine wave output of the function generator, and examine the output
of integrator 2 (TP47). Note that the integrator's output is no longer an approximation to the
analog input signal, but is instead somewhat triangular in shape.
Compare this with the output of integrator 1 (TP17), and note that the two signals are
exactly the same; the problem obviously starts in the delta modulator circuit
21. Compare the 2 KHz analog input signal (TP9) with the output of integrator 1 (TP17) it
should now become clear what has happened.
The analog signal is now changing so quickly that the integrator's output cannot ramp fast
enough to 'catch up' with it, and the result is known as 'slope overloading.'
22. Although the system clock frequency i.e. the sampling frequency determines how often the
integrator's output direction (up or down) can change, it does not affect how quickly the
integrator's output can ramp up and down. Consequently, changing the system clock
frequency will not help the slope overload problem; prove this by changing the clock
frequency selector switches, and noting that the problem is still present.
Return the switches to the A= 1, B=1 (256 KHz clock frequency) position before
continuing.
23. If slope overloading is to be avoided in a practical delta modulation system, the transmitter
integrator must be able to ramp up or down at a rate which is at least as great as the
maximum rate of change at the transmitter's analog input. If the incoming analog signal is a
sine wave, its maximum rate of change occurs at the zero crossing point, and is
proportional to both the frequency and the amplitude of the sine wave.
Hence, the likelihood of slope overloading can be reduced by either reducing the maximum
input frequency, or by reducing the maximum input amplitude to the delta modulator. We
have already seen how slope overloading can be avoided by reducing the frequency of the
analog input signal since there was no problem with the ~ 250 Hz analog inputs. Now
check that the problem can also be avoided if the amplitude of the input signal is reduced,
do this by slowly turning the ~2 KHz preset anticlockwise.
Note that there comes a time when the integrator's output can once again follow analog
input signal.
39
24. Another possible way of overcoming slope overloading is to increase the gain of the
integrators so that they can ramp up and down faster, and so follow even those analog input
waveforms that change very quickly.
To illustrate this, first return the ~2 KHz preset to its clockwise (maximum amplitude)
position, so that slope overloading can once again be seen on the scope.
In each of the two integrator blocks, there are two red switches labeled A and B. The 2bit
binary code produced by these switches selects one of four integrator gains, the lowest gain
selected when the switches are in the A=0, B=0 positions. For each increasing step in the
switch code from A=0, B=0 to A=1, B=1, the integrator gain is doubled.
Change the codes produced by the switches (in both integrator 1 and integrator 2 blocks)
from A=0, B=0 to A = 1, B=1, to double the gain of the two integrators; note that slope
overloading still occurs.
Then change both sets of switches to the A=1, B=0 position, and finally to the A=1, B= 1,
position, to show that slope overloading can be eliminated if the integrator gain is large
enough. Once again, it may be necessary to make a slight adjustment to the transmitter's
level adjust pressed, in order to obtain a stable trace on oscilloscope.
Note that, although it is the gain of integrator 1 alone which determines whether or not
slope overloading will occur, integrator 2 must have the same gain if the amplitude of the
demodulator's analog output is to be equal in amplitude to the modulator's analog input.
25. We have observed slope over loading can be overcome by changing anyone of the three
following options:
 Reducing the maximum input frequency to the delta modulator.

 Reducing the maximum input amplitude, or
 Increasing the integrator gain.
In a practical delta modulation communications system, the signal at the modulator's
analog input would normally be in the audio band, so that the maximum input frequency
could not be reduced below about 3.4 KHz without losing information. This rule out
solution (a) above.
The problem with reducing the amplitude for input signals solution (b) is that smaller input
signals then becomes lost in the quantization noise, they become smaller in amplitude than
the integrator's step size. Finally, if the integrator gain is increased solution (c), much the
same problem results as for solution (b), since the larger step size increase quantization
noise and once against 'drowns out' the smaller signals. In experiment 2, we will
investigate another solution to the problem of slope cover loading which allows us to use
high integrator gains for fast-changing analog input signals, and low integrator gains for
those smaller signals which would otherwise be 'Drowned out'.
Result: Delta Modulation and Demodulation are verified in the hardware kit and its waveforms are
studied.
40
VIVA VOCE QUESTIONS
1. Define Delta Modulation? Why it is better?
2. What are the disadvantages of Delta Modulation?
3. What is the condition for avoiding Slope Overload error?
4. What is the Signalling rate of Delta Modulation?
5. Define granular noise?
41
Experiment 4
Objective:
To perform Adaptive Delta Modulation and Demodulation.
Equipment Required:
3. Connecting cords
Theory
As it has been seen, delta modulation system is unable to chase the rapidly changing
information of the analog signal, which gives rise to distortion & hence poor quality
reception. This is known as slope overloading phenomenon. The problem can be
overcome by increasing the integrator gain (i.e. step-size). But using high step-size
integrator would lead to a high quantization noise.
Quantization Noise:
It is defined as error introduced between the original signal, & the quantized signal
due to the fixed step size in which the signal (quantized) is incremented. As the
error is random in nature & hence unpredictable, it can be treated as noise. High
quantization noise may play havoc on small amplitude signals. The solution to this
problem is to increase the integrator gain for fast-changing input & to use normal
gain for small amplitude signals.
The basic idea is to increase the integrator the integrator gain (it is doubled on this
trainer) when slope overload occurs. If still it is unable to catch up with the signal,
the integrator gain is doubled again. The integrator on board has four available gains
standard, standard X2, standard X4, and standard X8. The integrator thus adopts it
self to the gain where its lowest value can just overcome the slope overloading
effect. See figure 4.1.
Figure 4.1 Principal of Adaptive Delta Modulation
42
Functionally, the adaptive delta modulator/demodulator is shown in figure 4.2 &
figure 4.3. As it can be observed, the adaptive delta modulator is similar to the delta
modulator except for few blocks namely the counter & the control circuit.
The input to the control circuit is the latched data from the D Flip- Flop. The counter
is reset whenever 'high' appears at the output of the control circuit. Both the counter
& the control circuit are clocked by the same TX clock. The input to the integrator
from the counter is a two-bit control word, which controls the gain of the integrator.
When the output of counter is '00' the gain is lowest (standard) where as it is highest
(standard X8) for counters output '11'.
Table 4.1
Control Word Integrator Gain
00 Standard
01 Standard X2
10 Standard X4
11 Standard X8
Figure 4.2 Adaptive Delta Modulator
43
Figure 4.3 Adaptive Delta Demodulator
The Control Circuit Works as Follows:

The control circuit compares the preset data bit from D flip-flop with the previous two
data bits. Its output to the counter is high when the three bits are identical, the control
circuits output goes low, thus letting the counter advance with every clock cycle. This
advancement continues till the output from the control circuit does not go 'high'. Each
time the counter is incremented from ‘00’ integrator gain is doubled till the counter
reached '11' where it remains in that state until it is reset by the counter. Similarly, the
adaptive delta demodulator is a like delta demodulator except for two blocks namely,
the control circuit & the counter. They function in the same way as in modulator part,
except for the fact that they are clocked by the receiver clock.
Consider the adaptive delta modulator in operation. In normal case, when slope
overloading is not occurring, the integrator output always hunt above & below the
analog input even after it has caught up with it. The output from the D-Flip-Flop is a
constantly changing' l' to '0' at each TX clock edge. Even when the analog input is
changing at a slightly higher rate, the integrator ramp output is able to catch it in two
clock cycles. Thus, the output of the D-Flip-Flop is never a three or more
consecutive '0' or ‘1’s.
The changing input to the control circuit ensures that its output to the counter is high
& hence the counter is reseted at every clock cycle. Thus the control word from
counter is always '00' forcing the integrator gain at its lowest value, thereby reducing
quantization noise. Here the adaptive delta modulator is behaving just as a delta
modulator.
Suppose, now a fast changing analog signal appears at the input of the modulator
such that the slope overloading occur. The integrator output no longer follows the
analog signal but it spends its time trying to catch up the analog signal (either it
ramps down or up continuously). As a result of continuous ramping in one direction,
the D- Flip-Flops output is either '0' or '1' for three or more consecutive time. As
soon as the third continuous 1/0 is sensed by the control circuit its output goes low.
The counter now advances to 01 doubling the integrator gain. This increases the
ramping rate of the integrator & it is able to catch the analog signal more faster. In
the next clock cycle if the same situation continues the counter advances to ‘10' thus
forcing the integrator gain to quadruple its standard value. This situation continues
44
till the counter advances to '11' where it remains locked until the control logic does
not detect a change in the bit level at its input
As soon as the control circuit detects a change in the bit level, its output goes high,
thus resting the counter & thus normalizing the integrator gain. In adaptive delta
demodulator the control circuit receives the same bit stream as the transmitted one
except for the fact that it is received after a half clock cycle delay. The functioning
of the receiver's control circuit & counter is same as that of the transmitter's block.
Therefore, the demodulator output which itself is a good approximation of the
analog input signal accepts for the inhere spikes. The output from integrator is
passed to a low pass filter to 'smooth out 'the waveform. Thus, adaptive delta
modulation system is thus able to reduce slope-over load error at an expense of
small increase in quantization error. It turns out that in matter of speech transmission
the reduced slope error provides a net advantage in spite of slight increase in
quantization error & that the adaptive delta.
Modulator can operate at the bit rate of 32 KB/S with performance comparable to
that obtained using PCM at 64 KB/S.
Procedure:
1. Connect the mains supply.
2. Connect the board as per figure 4.4.
3. Ensure that the clock frequency selector switches A & B are in A=0 & B=0
position.
4. Ensure that the switches in TX. Integrator gain control block are in following
positions.
a) Gain control switch at the L.H.S. position. (towards switches A & B)
b) Switches A & B in position A=0 & B=0.
5. Ensure that the switches in receiver's integrator gain control block are in
following positions:
a) Gain control switches at the R.H.S. position. (towards switches A & B)
b) Switches A & B in Position A=0 & B=0.
6. Turn all the potentiometers of function, generator block namely 250Hz to
2 KHz to their fully clockwise positions.
7. Turn ON the supply.
8. As the gain control switch is towards A & B switches the gain setting is still
manual, connect the voltage comparator's +ve input to 0V & check whether
the modulator & demodulator are balanced for correct operation as in delta
modulation experimentation.
Change the clock frequency selector switches to the A=1, B=1, positions (256
KHz Clock Frequency) before continuing.
9. Disconnect the voltage comparators '+' input from 0V and reconnect it to the 2
KHz output from the function generator block.
10. Monitor the 2 KHz analog input at TP9 and the output of integrator 1 at TP17.
Note that slope overloading is still occurring, as indicated by the fact that the
integrator's output is not an approximation of the analog input signal.
11. At the transmitter, move the slider of the gain control switch in the integrator 1
block to the right-hand position (towards the sockets labeled A, B). At the
receiver, move the slider of the gain control switch in the integrator 2 blocks
to the left-hand position (again towards the sockets labeled A, B). The gain of
each integrator is now controlled by the outputs of the counter connected to it.
45
Functionally, the transmitter and receiver are now configured as shown in the
figure 4.2 & 4.3 i.e. as adaptive delta modulator and demodulator respectively.
12. Once again examine the 2 KHz analog input at TP9 and the output of
integrator 1 at TP17, noting that the" slope overloading problem has been
eliminated, and that the integrator's output once again follows the analog input
signal. Again, it may be necessary to adjust slightly the transmitter's level
adjust preset, in order to obtain a stable trace of the integrator's output signal.
13. Compare the output of integrator 1 (TP17) with that of integrator 2 (TP47);
noting that, as expected, both are identical in appearance.
14. Examine the output of the low pass filter (TP51) and the output of integrator 2
(TP47). The filter has removed the high-frequency components from the
integrator's output signal, to leave goods, clean 2 KHz sine wave.
15. Compare the original 2 KHz analog input signal (at TP9) with the output
signal from the receiver's low pass filter at TP47).
Note that the demodulator's output signal is equal in amplitude to the
modulator's input signal, but is delayed somewhat.
16. Disconnect the voltage comparator’s '+' input from the 2 KHz function
generator output, and reconnected it in turn to the 1 KHz, 500Hz and 250Hz
outputs, noting in each case that the demodulator’s output signal is identical to
the modulator's input signal, but delayed in time.
17. The adaptive delta modulator/demodulator system has therefore eliminated
any slope overloading problems. To examine in detail how it does this,
reconnect the voltage comparator's '+' input to the function generator's 2 KHz
output, then reduce the system clock (i.e. sampling) frequency to 32 KHz, by
putting the clock frequency selector switches in the A=0, B=0 positions.
Although a 32 KHz sampling frequency is too low to ensure that an
undistorted output is obtained from the demodulator's low pass filter, it does
increase the step size to a level, which makes it easier to understand how the
system is operating.
18. Monitor the 2 KHz analog input signal at TP9 and at the output of integrator 1
(TP17). It should now become a little clearer as to how the adaptive delta
modulator is operating. It will be noted that the slope of the integrator's output
signal is no longer constant, but increases in a series of discrete steps, in order
to 'catch up' with the fast-changing analog input signal.
If the integrator output does not 'catch up' with the analog input within two
clock periods of its direction changing, the slope of the integrator's output
signal (i.e. the integrator gain) is doubled. If it has still not caught up with the
analog input signal by the end of the third clock period, the integrator gain
will once again be doubled. If the integrator output still lags behind at the end
of the fourth clock period, the integrator's gain is doubled once again, to its
maximum value. It then remains at this value until the integrator output
'catches up' with the analog input signal. Once the integrators output
'overtakes' the analog input signal, its direction changes, and its rate of change
reverts to the minimum value.
19. Examine also the test points in the adaptive control circuit 1 block (TP20-24),
to ensure you have a complete understanding of how the adaptive delta
modulator is operating.
20. While monitoring the outputs of the modulator's binary counter (TP21 and 22),
slowly turn the 2 KHz preset anticlockwise, in order to reduce the amplitude of
the 2 KHz analog input signal. Notice that once the analog input signal becomes
46
small enough, both the counter's outputs becomes permanently low, causing the
integrator to have minimum gain. This happens because the input signal is now so
small that the integrator can always follow it, even with minimum gain.
The result is that small-amplitude input signals can be transmitted with
minimum integrator gain, thereby keeping quantization noise to a minimum at
the demodulator’s output.
Result: Adaptive Delta Modulation and Demodulation are verified in the hardware
kit and its waveforms are studied.
Figure 4.4
47
VIVA VOCE QUESTIONS
1. What is the difference between DM and ADM?
2. State the advantages of ADM over DM?
3. What is the condition for avoiding Slope Overload error?
4. What is the Signalling rate of Delta Modulation?
5. Are we able to avoid granular noise in ADM?
48
Experiment 5
Objective:
To perform Differential Pulse Code Modulation and Demodulation.
Equipment Required:

3. Connecting cords
Theory
ST2113, Differential Pulse Code Modulation Trainer is a manifestation of our increasing

efforts to present the modern technology in a best way to the people who want to unfold the
mysteries behind ever increasing communication super highway. To present it in a best way the
trainer incorporates the practical operating frequencies for sampling, audio processing and data
processing that are commonly used in our public telephone networks.
ST2113, DPCM trainer comprises of following major blocks:

 Audio Signal generator (with sine and square wave output).
 Modulator block which consists of :
a. Difference amplifier with sign manipulation circuit
b. ADC
c. Parallel to serial converter
d. Sample Predictor
 Demodulator block which consists of :
a. Serial to parallel converter
b. Adder and subtractor units
c. Bus latches
d. DAC
e. Output Low pass filter
 Audio input processing circuit.
 Audio output processing circuit.
 Clock and entire control Signal section.
49
Differential Pulse-Code Modulation
In Practical system bandwidth requirement for transformation of information is very important

aspect, since if bandwidth requirement is less, more number of channels can be multiplexed on a
single line and full utility of transmitting media is extracted out.
In a system in which a base band signal m (t) is transmitted by sampling, there is available a
scheme of transmission which is an alternative to transmitting the sample values (quantized or
not) at each sampling time. We can instead, at each sampling time, say the kth sampling time,
transmit the difference between the sample value m(k) at sampling time k and the sample value
m(k - 1) at time k - 1. If such changes are transmitted, then simply by adding up (accumulating)
these changes we shall generate at the receiver a waveform identical in form to m (t). There can
be a difference in dc components between transmitted and received signals but, almost
invariably; such dc components are of no interest.
Such a differential scheme has special merit when these differences are to be transmitted by
pulse code modulation. For we may well anticipate that the differences m(k) - m(k - 1) will be
smaller than the sample values themselves. Hence fewer levels will be required to quantize the
difference than are required to quantize m (k) and correspondingly, fewer bits will be needed to
encode the levels. For example, suppose that m (k) extends over a range VH - VL, and using
PCM, m (k) is encoded using 28 = 256 levels. Then the step size is S = (VH - VL)/28, that is VH-
VL = 256S. If, however, the difference signal m (k) - m (k - 1) extends only over the range ± 2S
then the quantized levels needed are at ± O.5S and at ± l.5S. There are now only four levels and
two bits per sample difference are adequate.
In an analog system, where we are able, at least in principle, to transmit the differences exactly,
the differential system described above would operate in accordance with our description. In a
digital (quantized) system we encounter the complication that the differences are not generally
transmitted exactly because of the quantization. Further, we have the problem that the difference
may be larger than the maximum that can be accommodated because of the restricted number of
encoding bits we have provided. Hence it might well be that at some time there might be a large
discrepancy between the original signal m(t) and the signal m(t) generated at the receiver by
accumulation. Suppose that over a number of samplings, while m (t) is increasing, the
transmitted differences were too small so that m (k) had fallen substantially short of keeping up
with m (t). Suppose, further, that in the interval sampling times k and k + 1, m (t) should
decrease slightly. Clearly if we transmitted the negative change of m (t) we would be giving the
wrong signal.
In a digital differential system we circumvent the difficulty we have just described by making
available at the transmitter a duplicate of the receiver accumulator so that at the transmitter we
have available the same signal m (t). Then we arrange that the transmitted signal should not
convey the most recent change in m (t) but conveys instead the difference between m (t) and m’
(t).
50
Figure 5.1 DPCM Transmitter / Receiver
In an analog system, this difference m (t) – m’ (t) is precisely the last change in m(t). In a
quantized system, as we have noted, such is not the case. In short, in a quantized system we add
or subtract from m (t) a value which is appropriate to bring m(t) closer to m (t). The waveform
m’ (t) is generally referred to as the approximation to m (t).
Altogether, then, the quantized differential transmission scheme is as shown in figure 5.1 (we
ignore initially the "predictors" that appear in the figure 5.1). The receiver consists of an
accumulator which adds up the received quantized differences Q (k) and a filter which smooths
out the quantization noise. The output of the accumulator is the signal approximation m’ (k)
which becomes m (t) at the filter output. At the transmitter we need to know whether m (t) is
larger or smaller than m (t), and by how much. We may then determine whether the next
difference Q (k) needs to be positive or negative and of what amplitude in order to bring m’ (t) as
close as possible to m(t). For this reason we have a duplicate accumulator at the transmitter. At
each sampling time, the transmitter difference amplifier compares m’ (t) and m (t) and the
sample and hold circuitry holds the result of that comparison (t) for the duration of the interval
between sampling times. The quantized generates the signal So (t) = Q(k) both for transmission
to the receiver and to provide input to the receiver accumulator in the transmitter. In a practical
system the quantized differences would first be encoded into a binary bit stream before
51
transmission and decoded at the receiver. For simplicity the encoder and decoder are not
included in the above figure 5.1.
It needs to be emphasized that the basic limitation of the scheme we have just described is that
the transmitted differences are quantized and are of limited maximum value. The quantization
means that almost never will the increment Q (k) added to m (k) make m’ (t) precisely equal to m
(t). The limitation on the maximum value of (k) means that when m (t) changes monotonically at
a rapid rate, m’ (t) may simply not be able to keep up.
Procedure:
1. Connect the sine wave output of the audio signal generator to one of the inputs of the
difference amplifier as shown in the figure 5.2.
2. Connect the output of the difference amplifier to the input of the ADC.
3. Connect the output of parallel to serial converter to the input of serial to parallel
converter of the receiver accumulator.
4. Connect the output of the DAC to the other input of the difference amplifier as shown in
the above figure 5.2.
5. Now switch ‘On’ the power supply. Observe the sine wave output of the sine wave
generator on the CRO. Adjust the frequency of sine wave at 1 KHz.
6. Observe the signal at the output of DAC. You will see the stair case approximation of the
input signal at the output of DAC. Also observe the output of low pass filter and see that
it is nearly same as the input signal.
7. Now observe various controls and clock signal shown in the control and clock section
and try to relate these signals with the timing diagram of figure 5.3.
8. Note that the sampling starts with the R/W signal pulse that has a frequency of 8 KHz.
For a small duration when pulse is high, ADC reads the input port and for the rest of the
low period it provides this data at the output of the ADC.
9. Now observe the clock and reset signal of the parallel to serial converter. Observe that for
the time period when reset is low, exactly five clock pulses shift the content of the shit
register.
10. Observe the LE2 and OE 2of previous data latch and relate them with timing diagram of
figure 5.3.
11. You may find it difficult to appreciate the entire control signals simultaneously with a
normal two channels CRO but nevertheless an intuitive sense of relative time based
occurrences of all these signals can make the task easier. You can see all these signals
simultaneously on the screen with the help of logic analyzer too.
12. Also it is to be taken into consideration that the data flow through the entire system is fast
enough random as well so it is not feasible to observe the data exactly at any point. But
still you can have an overview of the data statistics at any test point of the data bus.
52
Figure 5.2 Setup for study of DPCM Process
53
Figure 5.3 Timing Diagrams
54
VIVA VOCE QUESTIONS
1. What is the operating principle of differential PCM System?

2. Why is the signalling rate of DPCM less than that of PCM System?
3. What is the role of Predictor in DPCM System?
4. Give one merit of DPCM?
5. What is the disadvantage of DPCM over delta modulation?
55
Experiment 6
Objective:
To perform different Line Codes – NRZ-L, NRZ-M, RZ, Biphase (Manchester),

Biphase (Mark) and AMI.
Equipment Required:
1. ST2156 and ST2157 with power supply cord
3. Connecting cords
Theory:
Line Coding and Decoding:
Line coding consists of representing the digital signal to be transported, by an

amplitude- and time-discrete signal that is optimally tuned for the specific properties
of the physical channel (and of the receiving equipment). The waveform pattern of
voltage or current used to represent the 1s and 0s of a digital signal on a transmission
link is called line encoding. The common types of line encoding are unipolar, polar,
bipolar and Manchester encoding.
Line codes are used commonly in computer communication networks over short
distances.
Each of the various line formats has a particular advantage and disadvantage. It is not
possible to select one, which will meet all needs. The format may be selected to meet
one or more of the following criteria:

 Minimize transmission hardware
 Facilitate synchronization
 Ease error detection and correction
 Minimize spectral content
 Eliminate a dc component
The Manchester code is quite popular. It is known as a self-clocking code because

there is always a transition during the bit interval. Consequently, long strings of zeros
or ones do not cause clocking problems.
56
Figure 6.1 Various Data formatting techniques
Figure 6.2 Classification of Line codes
Different Data Formatting techniques:

Non return to zero- level (NRZ-L):
Representation : +5V for data bit 1 and 0V for data bit 0.
Bandwidth : Low bandwidth.
DC Level : High DC component.
Timing Information : No timing information (For long stream of 1s
and 0s)
57
Figure 6.3 Waveforms of NRZ-L
Non return to zero- level (NRZ-M):

Representation : Level transition for bit 1 and unchanged level
for bit 0.
Bandwidth : Low bandwidth.
Timing Information : No timing information (For long stream of 0s)
Figure 6.4 Waveforms of NRZ-M
Return to zero (RZ):

Representation : 0V for bit 0 and for bit 1, for half bit duration +5V
and the rest of the bit duration is represented as 0V.
Bandwidth : Twice as that required for the NRZ.
Timing Information : No timing information (For long stream of 0s)
Figure 6.5 Waveforms of RZ-L
58
Biphase (Manchester):
Representation : For bit 1, +5V for first half bit time and 0V during
the second half and for bit 0, 0V for first half bit
time and +5V during the second half.
DC Level : No DC component.
Timing Information : Good clock recovery.
Figure 6.6 Waveforms of Manchester
Biphase (Mark):
Representation : For any bit either 1 or 0, first half bit duration +5V
or 0V and invert of first half during next half bit
duration. Bit 0 Bit Pattern remains the same.
Bit 1 Phase Reversal.
Timing Information : Good clock recovery.
Figure 6.7 Waveforms of Mark
59
Return to Bias (RB):
Representation: During the first half a period, positive level for bit 1
and a negative level for bit 0 and during the second
half bit time, both returns to the bias level.
Bandwidth: Twice as that required for the NRZ.
DC Level: The DC component depends on the string of 1’s and
0’s.
Timing Information: Good clock recovery (Self clocking system).
Figure 6.8 Waveforms of RB
Alternate Mark Inversion (AMI):

Representation : Like RB encoding, the AMI always returns to the
bias level during second half of the bit time interval
and during the first half the transmitted level can be a
positive, a negative or bias level, as for a bit 0 bias
level and for a bit 1 either a positive level or negative
level, the level being chose opposite to what it was
used to represent the previous bit 1.
Timing Information : No timing information (For long sequence of 0’s).
Figure 6.9 Waveforms of AMI
60
Circuit Diagram:
Figure 6.10
61
Procedure:
1. Connect the power supply of Scientech 2156 but do not turn on the power
supplies until connections are made for this experiment.
2. Make the connections as shown in the figure 6.10.
3. Switch 'ON' the power.
4. Connect oscilloscope CH1 to ‘Data In’ and CH2 to ‘Clock In’ and observe the
waveforms.
5. Connect oscilloscope CH1 to ‘Data In’ and CH2 to ‘NRZ (L)’ and observe the
waveforms.
6. Connect oscilloscope CH1 to ‘Data In’ and CH2 to ‘NRZ (M)’ and observe the
waveforms.
7. Connect oscilloscope CH1 to ‘Data In’ and CH2 to ‘RZ’ and observe the
waveforms.
8. Connect oscilloscope CH1 to ‘Data In’ and CH2 to ‘Biphase (manchester)’ and
observe the waveforms.
9. Connect oscilloscope CH1 to ‘Data In’ and CH2 to ‘Biphase (Mark)’ and
observe the waveforms.
10. Connect oscilloscope CH1 to ‘Data In’ and CH2 to ‘RB’ and observe the
waveforms.
11. Connect oscilloscope CH1 to ‘Data In’ and CH2 to ‘AMI’ and observe the
waveforms.
Observations:
1. The output at ‘Data In’ is repeating sequence of bits generated by Parallel to

serial Converter.
2. The ‘NRZ (L)’ data is same as ‘Data In’ but it is one bit shifted.
3. Verify all the formatting techniques according to example patterns given on the
Scientech 2156 board.
Conclusions:
1. The NRZ(L) waveform simply goes low for one bit time to represent a data ‘0’
and high for one bit time to represent a data ‘1’.
2. In the NRZ (M) line codes the present level is related to the previous level that
is when logic ‘1’ is to be transmitted change in level occurs and for logic ‘0’ the
level remains unchanged.
3. In the RZ line codes, the maximum signal frequency of ‘RZ’ signal occurs when
a string of ‘1’ is transmitted. It is equivalent to sending two logic levels in each
clock period. Thus bandwidth requires is twice as that required for the NRZ
waveforms.
4. The Biphase Manchester codes always contain at least one transition per bit
time, irrespective of the data being transmitted. Hence the maximum frequency
of the biphase code is equal to the data clock rate when a stream of consecutive
62
data ‘1’ & ‘0’ is transmitted. Therefore the required bandwidth is same as that of
RZ code & double as that of NRZ (L) code.
5. In the ‘Biphase Mark’ if a data ‘0’ is to be transmitted, the sequence of the
transmitted levels will remain same as for the previous bit interval and if a ‘1’ is
to be transmitted , the sequence of the transmitted levels will reverse i.e. phase
reversal will occur.
6. The Biphase Mark code being very similar to the Biphase (Manchester) coding
requires same amount of bandwidth which is double as that of NRZ (L).
7. The maximum signal frequency in RB code is equal to the data clock frequency;
the bandwidth requirements is same as that for RZ, Biphase codes and double
that for NRZ codes.
8. The maximum transition rate for AMI can only occur during a stream of all ‘1s’
thus the bandwidth required is twice that required for the NRZ codes.
63
VIVA VOCE QUESTIONS
1. What is Baseband binary data transmission System?
2. What is Equalization?
3. What do you mean by Eye diagram?
4. What are the other names for Bipolar and Manchester Coding?
5. What is the difference among uniploar, polar and bipolar coding?
64
Experiment 7
Objective:
To perform Amplitude Shift Keying Modulation and Demodulation.
Equipment Required:

3. Connecting cords
Theory
Amplitude Shift Keying (ASK) Technique:
The simplest method of modulating a carrier with a data stream is to change the
amplitude of the carrier wave every time the data changes. This modulation
technique is known as Amplitude Shift Keying.
The simplest way of achieving amplitude shift keying is by switching 'ON' the
carrier whenever the data bit is '1' & switching it 'OFF' whenever the data bit is '0'
i.e. the transmitter outputs the carrier for a' 1 ' & totally suppresses the carrier for a
'0'. This technique is also known as ON-OFF keying. Figure 7.1 illustrates the
amplitude shift keying for the given data stream.
Thus,
Data = 1 carrier transmitted
Data = 0 carrier suppressed
Figure 7.1 Amplitude Shift Keying modulation waveform
65
The ASK waveform is generated by a balanced modulator circuit, also known as a
linear multiplier as shown in the figure 7.2 given below. As the name suggests, the
device multiplies the instantaneous signal at its two inputs. The output voltage being
product of the two input voltages at any instance of time. One of the inputs is AC
coupled 'carrier' wave of high frequency. Generally, the carrier wave is a sinusoidal
signal since any other waveform would increase the bandwidth, without providing
any advantages. The other input which is the information signal to be transmitted, is
DC coupled. It is known as modulating signal.
Figure 7.2 Amplitude Shift Keying Modulator
The data stream applied is unipolar i.e. 0 volts for logic '0' & + 5 Volts for logic '1'.
The output of balanced modulator is a sine wave, unchanged in phase when a data bit
‘l' is applied to it and is zero when the data bit '0' is applied.
The ASK modulation result in a great simplicity at the receiver. The method to
demodulate the ASK waveform is to rectify it, pass it through the filter & ‘shape up’
the resulting waveform. The output is the original data stream. Figure 7.3 shows the
functional blocks required in order to demodulate the ASK waveform at receiver.
Figure 7.3 Amplitude Shift Keying Demodulator
66
Connection diagram:
Figure 7.4
67
Procedure:
1. Connect the power supplies of Scientech 2156 and Scientech 2157 but do not
turn on the power supplies until connections are made for this experiment.
4. On Scientech 2156, connect oscilloscope CH1 to ‘Clock In’ and CH2 to ‘Data
In’ and observe the waveforms.
5. On Scientech 2156, connect oscilloscope CH1 to ‘NRZ (L)’ and CH2 to
‘Output’ of modulator Circuit (l) on Scientech 2156 and observe the
waveforms.
6. Vary the gain potentiometer of modulator circuit (l) on Scientech 2156 to adjust
the amplitude of ASK Waveform.
‘Output’ of comparator on Scientech 2157 and observe the waveforms.
Observations:
1. The output at ‘Data In’ is repeating sequence of bits generated by Data Source.
2. The output at Modulator Circuit (l) is the ASK waveform which contains carrier
transmitted for Data ‘1’ and carrier suppressed Data ‘0’.
3. The output at comparator on Scientech 2157 is the same as ‘Data In’ on
Scientech 2156.
Figure 7.5 Waveforms Of ASK Modulation
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Figure 7.6 Waveforms Of ASK Demodulation
Conclusions:
1. Amplitude shift keying is fairly simple to implement in practice, but it is less

efficient, because the noise inherent in the transmission channel can deteriorate
the signal so much that the amplitude changes in the modulated carrier wave due
to noise addition, may lead to the incorrect decoding at the receiver.
2. The technique is not widely used is practice. Application wise, it is however
used in diverse areas and old as emergency radio transmissions and fiber-optic
communications.
69
VIVA VOCE QUESTIONS
1. What are the types of Digital Modulation techniques?

2. Define Coherent Digital Modulation technique?
3. State the bandwidth requirement in ASK System?
4. What is the major demerit of ASK?
5. Which are the techniques which can remove the disadvantage of ASK?
70
Experiment 8
Objective:
To perform Phase Shift Keying Modulation and Demodulation.
Equipment Required:

3. Connecting cords
Theory
Phase Shift Keying (PSK) Technique:

Phase shift keying involves the phase change of the carrier wave between 0 and 180
in accordance with the data levels to be transmitted. Phase shift keying is also known
as phase reversal keying (PRK). The PSK waveform for a given data is as shown in
figure 8.1.
For Binary PSK

S0 (t)  Acos(wt) represents binary ‘0’
S1 (t)  Acos(wt+ ) represents binary ‘1’
Figure 8.1 Phase Shift Keying Waveform
Functionally, the PSK modulator is very similar to the ASK modulator. Both uses
balanced modulator to multiply the carrier with the modulating signal. But in contrast
to ASK technique, the digital signal applied to the modulation input for PSK
generation is bipolar i.e. have equal positive and negative voltage levels. When the
modulating input is positive the output of modulator is a sine wave in phase with the
carrier input. Where as for the negative voltage levels, the output of modulator is a
sine wave which is shifted out of phase by 180 from the carrier input. This happens
because the carrier input is now multiplied by the negative constant level. The
functional block representation of the PSK modulator is shown in the figure 8.2.
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Figure 8.2 Phase Shift Keying Modulator
For PSK signal demodulation the square loop detector circuit is used. The PSK
demodulator is as shown in figure 8.3.
Figure 8.3 Phase Shift Keying Demodulator
The incoming PSK signal with 0 & 180 phase changes is first fed to the signal
squarer, which multiplies the input signal by itself. The output of this block is a signal
of having twice the frequency to that of the input carrier frequency. As the frequency
of the output doubled, the 0 & 180 phase changes are reflect as 0 & 360 phase
changes. Since phase change of 360 is same as 0 phase change, it can be said that
the signal squarer simply removes the phase transitions from the original PSK
waveform.
The PLL block locks to the frequency of the signal square output & produces a clean
square wave output of same frequency. To derive the square wave of same frequency
as the incoming PSK signal, the PLL output is divided by two.
The following phase adjust circuit allows the phase of the digital signal to be adjusted
with respect to the input PSK signal. Also its output controls the closing of an analog
switch. When the output is high the switch closes & the original PSK signal is
switched through the detector. When the output of phases adjust block is low, the
switch opens & the output of detector output falls to 0 Volts. The demodulator output
contains positive half cycles when the PSK input has one phase & only negative half
cycles when the PSK input has another phase. The phase adjust potentiometer is
adjusted properly. The average level information of the demodulator output which
contains the digital data information is extracted by the following low pass filter. The
low pass filter output is too rounded to be used for digital processing. Therefore it is
'Squared Up' by a voltage comparator.
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Figure 8.4 Phase Shift Keying Receiver System
Since the sine wave is symmetrical, the receiver has no way of detecting whether the
incoming phase of the signal is 0 or 180 This phase ambiguity create two different
possibilities for the receiver output i.e. the final data stream can be either the original
data stream or its inverse.
This phase ambiguity can be corrected by applying some data conditioning to the
incoming stream to convert it to a form which recognizes the logic levels by changes
that occur & not by the absolute value. One such code is NRZ (M) where a change or
the absence of change conveys the information. A change in level represents data '1'
& no change represents data '0'. This NRZ (M) waveform is used to change the phase
at the modulator. The comparator output at receiver can again be of two forms, one
being the logical inverse of the other. But now it is not the absolute value in which we
are interested. Now the receiver simply locks for changes in levels, a level change
representing a '1' and no level changes representing a '0' thus the phase ambiguity
problem does not makes difference any more. This is known as differential phase shift
keying. This process is known as differential encoding.
73
Circuit diagram:
Figure 8.5
74
Procedure:
‘Output’ of Modulator Circuit (l) on Scientech 2156 and observe the waveforms.
6. Adjust the ‘Gain’ potentiometer of the Modulator Circuit (l) on Scientech 2156
to adjust the amplitude of PSK waveform at output of Modulator Circuit (l) on
Scientech 2156.
7. Now on Scientech 2157 select Carrier frequency selection switch to 1.6MHz
and connect oscilloscope CH1 to ‘Input’ of PSK demodulator and connect CH2
one by one to output of double squaring circuit, output of PLL, output of Divide
by four (÷ 2) observe the wave forms.
8. On Scientech 2157 connect oscilloscope CH1 to output of Phase adjust and
CH2 to ‘output’ of PSK demodulator and observe the waveforms. Set all toggle
switch to 0 and compare the waveform now vary the phase adjust potentiometer
and observe its effects on the demodulated signal waveform. (Note: If there is
problem in setting the waveform with potentiometer then toggle the switch
given in PSK demodulator block two to three times to get the required
waveform).
9. Now connect oscilloscope CH1 to ‘PSK’ output of PSK demodulator on
Scientech 2157 and connect CH2 ‘Output’ of Low Pass Filter on Scientech
2157 and observe the waveforms.
10. Connect oscilloscope CH1 to ‘Output’ of Low Pass Filter on Scientech 2157
then connect CH2 to ‘Output’ of Comparator on Scientech 2157 and observe the
waveforms, now vary the reference voltage potentiometer of first comparator to
generate desired data pattern.
12. Now try to match the LED sequence by once pressing the reset switch on
Scientech 2156.
Observations:
2. The ‘Output’ of Modulator Circuit (l) is Phase Shift Keying modulated signal.
3. The output of Double squaring circuit is sinusoidal signal (carrier signal) but
frequency is four times higher than that of carrier used for modulation.
4. The output of Phase Lock Loop (PLL) is clock signal of same frequency as that
of the output of double squaring circuit and output of Divide by two (÷ 2) is
clock signal of frequency two times less than the output of PLL signal.
75
5. The output of PSK demodulator is a signal having group of positive half cycles
and group of negative half cycles of the carrier signal.
6. A low pass filter removes high frequency component from demodulated PSK
signal and it makes the signal smooth.
7. The variation in reference voltage potentiometer affect the Data, to recover Data
correctly potentiometer adjustment is necessary.
8. The Phase Adjust potentiometer on Scientech 2157 matches the phase of
regenerated clock and carrier with input clock and carrier signal.
Figure 8.6 Waveforms of PSK Modulation
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Figure 8.7 Waveforms of PSK Demodulation
Conclusions:
Now we can observe that the final data stream can be either the original data stream
or its inverse, this is because the sine wave is symmetrical, the receiver has no way of
detecting whether the incoming phase of the signal is 0 or 180 This phase ambiguity
create two different possibilities for the receiver output i.e. the final data stream can
be either the original data stream or its invers
77
VIVA VOCE QUESTIONS
1. What is the bandwidth of BPSK?
2. What is the role of bit synchronizer in BPSK Receiver?
3. What is the disadvantage of BPSK Receiver?
4. What type of receiver is used for BPSK detection?
5. What is the basic difference between coherent and non-coherent BPSK?
78
Experiment 9
Objective:
To perform Frequency Shift Keying Modulation and Demodulation.
Equipment Required:

3. Connecting cords
Theory
Frequency Shift Keying Modulator:
On a closer look at the FSK waveform, it is apparent that it can be represented as the
sum of two ASK waveforms. This is illustrated in figure 9.1.
Figure 9.1 Generation of FSK Waveform from the sum of two ASK Waveforms
The functional blocks required in order to generate the FSK signal is as shown in
figure 9.2. There are two ASK modulator, each has different carrier frequencies but
the digital data is inverted in one of the modulator. These two different ASK
modulated signal are applied to the suming amplifier to get FSK modulated signal.
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Figure 9.2 Frequency Shift Keying Modulator
The demodulation of FSK waveform can be carried out by a phase locked loop. As
known, the phase locked loop tries to 'lock' to the input frequency. It achieves this by
generating corresponding output voltage to be fed to the voltage controlled oscillator,
if any frequency deviation at its input is encountered. Thus the PLL detector follows
the frequency changes & generates proportional output voltage. The output voltage
from PLL contains the carrier components. Therefore the signal is passed through the
low pass filter to remove them. The resulting wave is rounded to be used for digital
data processing. Also, the amplitude level may be very low due to channel
attenuation. The signal is 'Shaped Up' by feeding it to the voltage comparator. The
functional block diagram of FSK demodulator is shown in figure 9.3.
Figure 9.3 Frequency Shift Keying Demodulator
Advantages and limitations of Frequency Shift Keying Modulation
Since the amplitude change in FSK waveform does not matter, this modulation
technique is very reliable even in noisy & fading channels. But there is always a price
to be paid to gain that advantage.
The price in this case is widening of the required bandwidth. The bandwidth increase
depends upon the two carrier frequencies used & the digital data rate. Also, for a
given data, the higher the frequencies & the more they differ from each other, the
wider the required bandwidth. The bandwidth required is at least doubled than that in
the ASK modulation. This means that lesser number of communication channels for
given band of frequencies.
80
Circuit diagram:
Figure 9.4
81
Procedure:
‘Output’ of Summing Amplifier on Scientech 2156 and observe the waveforms.
6. Adjust the potentiometers of both the Modulator Circuit (l) &(ll) onScientech
2156 to adjust the amplitude of FSK waveform at Summing Amplifier’s output
on Scientech 2156.
Observations:
1. The output at Summer Amplifier is the FSK waveform, Observe that for data bit
'0' the FSK signal is at lower frequency (960KHz) & for data bit '1’ the FSK
signal is at higher frequency (1.6 MHz)The output at comparator on Scientech
2157 is the same as ‘Data In’ on Scientech 2156.
Figure9.5 Waveforms of FSK Modulation & Demodulation
82
Conclusions:
1. The amplitude change in FSK waveform does not matter, therefore FSK
modulation technique is very reliable even in noisy & fading channels.
83
VIVA VOCE QUESTIONS
1. What is the bandwidth of BFSK?
2. What is meant by orthogonal BFSK?
3. What type of receiver is used in BFSK System?
4. What is the advantage of M-ary FSK over BFSK?
5. What is the advantage of FSK over ASK?
84
Experiment 10
Objective:
To perform Quadrature Phase Shift Keying Modulation and Demodulation.
Equipment Required:

3. Connecting cords
Theory
If we define four signals, each with a phase shift differing by 90 degree then we have
Quadrature Phase Shift Keying (QPSK).
d d
The input binary bit stream k , k = 0,1,2,..... arrives at the modulator input at a rate
d (t) d (t)
1/T bits/sec and is separated into two data streams I and Q containing odd
and even bits respectively.
d (t)
I = d0, d2, d4.....
d (t)
Q = d1, d3, d5.....
Figure 10.1 Serial to Parallel Conversion
85
A convenient orthogonal realization of a QPSK waveform, s(t) is achieved by
amplitude modulating the in-phase and quadrature data streams onto the cosine and
sine functions of a carrier wave as follows:
s(t)=1/ 2 dI(t) cos (2ft + /4) + 1/ 2 dQ(t) sin (2ft + /4)
Figure 10.2 Quadrature Phase Shift Keying Waveforms
In quardrature Phase Shift keying each pair of consecutive data bit is treated as a two
bit (or Dibit) code which is used to switch the phase of the carrier sine wave between
one of four phases 90° apart. The four possible combination of Dibit code are 00, 01,
10 and 11. Each code represents either a phase of 45°, 135°, 225°, and 315° lagging,
relative to the phase of the original un-modulated carrier. The choice of these phases
is arbitrary as it is convenient to produce them. Quadrature phase shift keying offers
an advantage over PSK, in a manner that now each phase represents a two bit code
rather than a single bit. This means now either we can change phase per second or the
same amount of data can be transmitted with half as many phase changes per second.
The second choice results in a lowering of bandwidth requirement.
The four phases are produced by adding two carrier waves of same frequency but 90°
out of phases. The 0° phase carrier is called In-phase carrier and is labeled 1 The other
is 90° (lagging) phase carrier termed as the quadrature carrier and is labeled Q.
The I-carrier is controlled by the MSB (most significant bit) of the Dibit code. When
the MSB is a level ‘0' the phase is 0 degrees when the MSB goes to level 1 the phase
reverses to 180°
The Q-carrier starts with 90° out of phase (with respect to reference I carrier). This
carrier is controlled by the LSB (least significant bit) of the digit code when the LSB
is a level 0, the phase is 90° degrees with reference to I-carrier). When the LSB goes
to a level 1, the phase reverses to 270°. See figure 10.3.
86
Figure 10.3 Phasor Diagram
Assume the digit code be 00. This would give a 0° phase to the in phase carrier and 0°
phase to quadrature carrier (90° out of phase with respect to I-carrier). If we add these
two waves we would get a 45° resultant.
Figure 10.4 Phasor Diagram for data bit 00
At any instance of time, there is always a +/- 90° phase difference between the two
modulation outputs. As a result, the amplitude of the resultant phasor will always be
Ö2 times the amplitude of input phase or if they are equal. The creation of four phases
by vector addition is as shown in figure 10.5.
87
Figure 10.5 Phasor Diagram
It can be appreciated from the above phasor diagram that each phasor switches its
phase depending on the data level exactly in the same way as the same way as the
PSK modulator does. The only difference is that QPSK is sum of two such PSK
modulators.
The QPSK modulator can be configured as shown in the figure 10.6.
Figure 10.6 Quadrature Phase Shift Keying Modulator
The two carriers namely I & Q as has been stated, have same frequency but differ in
phase by 90°. Also,the data refer to the Dibit MSB & Q data refers to the Dibit LSB.
Each modulator performs phase-shift keying on its respective carrier input in

accordance with respective data input such that,
88
 The output of modulator 1 is a PSK signal with phase shift of 0° and 180°
respectively, relative to the I-carrier, and
 The output of modulator 2 is a PSK signal with phase shift of 90° and 270°
respectively, relative to the I-carrier.
The output of the two modulators is summed by a summing amplifier. As it is clear

from the earlier phasor diagram, the phase of the summing amplifier's output signal
relative to I-carrier, at any instance of time takes one of the four phases 45° 135°,
225°, and 315° depending on the applied debit code. When these Dibit codes alter, the
phase of the QPSK output changes by 0°, 90°, 180° or 270° from its previous phase
position. Thus the output of the summing amplifier is a QPSK waveform. The
demodulation of QPSK signal is performed by the fourth power loop detector. The
demodulator is quite similar to the one used in PSK system as can be seen from figure
10.7.
Quadrature Phase Shift Keying Demodulator:

The incoming QPSK signal is first squared in the signal squarer 1. The functioning of
the signal squarer has already been discussed in the PSK Modulator section. The
output of the signal squarer 1 is a signal at twice the original frequency with phase
changes reduced to 0° & 180°. This is because all the phase changes are also doubled.
The 0° & 180° phase changes becomes 0° (as 2 x 180 = 360° = 0° phase shift.) and
the 90° and 270° phases both become 180° (since 270° + 270° = 540° = 180° phase
shift).
Figure 10.7 Quadrature Phase Shift Keying Demodulator
The output of the signal squarer 1 is fed to signal 1. The output of the signal squarer 1
is fed to signal squarer 2. This circuit is identical to signal squarer with frequency
double that of the signal at its input (Quadrupled with respect to the original QPSK
input signal frequency). The 0° and 180° phases changes are also reduced to a 0°
phase changes are also reduced to 0° phases shift, since the phases are also doubled
(Also 2 x 180 = 360° = 0° phase shift).
Therefore, the output from signal squarer 2 is a sinewave at four times the frequency
of the original QPSK carrier signal with no phase changes.
The output of signal squarer 2 is fed to the phase locked loop (PLL) which locks on
the incoming signal & produces a square wave of same frequency as that of the input.
The output of PLL is divided in frequency by a factor of 4 by a ÷ 4 circuit. Now the
frequency is same as that of the QPSK carrier signal.
89
The next stage in demodulation is a phase adjusts Circuit. The output of the phase
adjust circuit are two square waves of same frequency as the input signal applied and
with 90° phase shift between them. Also the phase of the two output signals can also
be adjusted relative to the original QPSK signal. Note that the 90° phase difference
between the two outputs is maintained.
The output of the phase circuit controls the two analog switches. The switch is closed
when the corresponding output goes high. The original QPSK signal is then switched
through to one of the QPSK demodulator. How output can be input with a low level,
the switches are open & the output is pulled down to 0V.
The two outputs from the demodulator are labeled I & Q. Once the correct phase
relation between QPSK signal & phase adjust output have been set, the I & Q outputs
will contain information about original two bit code. This is illustrated in phase or
diagram. See figure 10.9.
Figure 10.9 All Angles represent phase LAG with respect to Phasor Diagram
The average level of the I & Q outputs contains information about the Dibit code.
The average level of the two outputs is extracted by passing them through the low
pass filter. The output of the filters is rounded & cannot be used for digital
processing. The wave 'Squared Up' by a voltage a comparator circuit. As shown in
the figure 10.10.
Figure 10.10 Quadrature Phase Shift Keying Receiver
90
Circuit diagram:
Figure 10.11
91
Procedure:
5. On Scientech 2156, connect oscilloscope CH1 to ‘Clock Output’ and CH2 one
by one to ‘Sine’ and ‘Cosine’ output of 960 KHz and observe the waveforms.
6. On Scientech 2156, connect oscilloscope CH1 to ‘Data In’ and connect CH2 one
by one to ‘I Data’ and ‘Q Data’ outputs and observe the waveforms.
7. Now connect oscilloscope CH1 to ‘I Data’ output on Scientech 2156 and
connect CH2 one by one to ‘Signal In’, ‘Carrier In’ and ‘Output’ of modulator
circuit (l) on Scientech 2156 and observe the waveforms.
8. Now connect oscilloscope CH1 to ‘Q Data’ output on Scientech 2156 and
connect CH2 one by one to ‘Signal In’, ‘Carrier In’ and ‘Output’ of modulator
circuit (ll) on Scientech 2156 and observe the waveforms.
9. Now connect oscilloscope CH1 to ‘Data Out’ on Scientech 2156 and CH2 to
‘Output’ of Summing Amplifier on Scientech 2156 and observe the waveforms.
10. Set ‘Carrier frequency’ selection switch to ‘960 KHz’ on Scientech 2157.
11. Now on Scientech 2157 connect oscilloscope CH1 to ‘Input’ of QPSK
demodulator and connect CH2 one by one to output of double squaring circuit,
output of PLL, output of Divide by four (÷ 4) observe the wave forms.
12. On Scientech 2157, connect oscilloscope CH1 to ‘I’ output of QPSK
demodulator and CH2 to ‘Q’ output of QPSK demodulator and observe the
waveforms. Set all toggle switch to 0, now vary the phase adjust potentiometer
and observe its effects on the demodulated signal waveforms.
13. Connect oscilloscope CH1 to ‘I’ output of QPSK demodulator on Scientech
2157 then connect CH2 one by one to output of low pass filter, output of
Comparator on Scientech 2157 and observe the waveforms.
14. Connect oscilloscope CH1 to ‘Q’ output of QPSK demodulator on Scientech
2157 then connect CH2 one by one to output of low pass filter, output of
Comparator on Scientech 2157 and observe the waveforms.
15. Compare the output of comparators on Scientech 2157 with the output ‘I Data’
and ‘Q Data’ on Scientech 2156 respectively.
16. Connect oscilloscope CH1 to ‘Data In’ then connect CH2 output to Bit decoder
and observe the waveforms. If both data does not matches then try to match it by
varying the phase adjust potentiometer on QPSK Demodulator.
17. Now try to match the LED sequence by once pressing the reset switch on
Scientech 2156.
92
Observations:
2. The ‘I Data’ and ‘Q Data’ output are even and odd bit sequence of input data
sequence and bit duration is double of input data sequence as shown in the
figure 10.11.
3. The ‘Output’ of Modulator Circuit (l) and Modulator Circuit (ll) are Phase Shift
Keying modulated signals, and summation of these two signals are Quadrature
Phase Shifted signal as shown in the figure 10.2.
4. The output of Double squaring circuit is sinusoidal signal (carrier signal) but
frequency is four times higher than that of carrier used.
5. The output of Phase Lock Loop (PLL) is clock signal of same frequency as that
of the output of double squaring circuit and output of Divide by four (÷ 4) is
clock signal of frequency four times less than the output of PLL signal.
6. The output of QPSK demodulator is a signal having group of positive half
cycles and group of negative half cycles of the carrier signal as shown in the
figure 10.3.
7. A low pass filter removes high frequency component from demodulated QPSK
signal and it makes the signal smooth as shown in the figure 10.12.
8. The variation in reference voltage potentiometer affect the Data, to recover Data
correctly potentiometer adjustment is necessary and recovered Data.
93
Figure 10.12 QPSK modulation waveforms
94
Figure 10.13 QPSK demodulation waveforms
Conclusion:
The Quadrature Phase Shift Keying modulation is correct for different Data pattern
and also correct for clock and carrier frequencies.
95
VIVA VOCE QUESTIONS
1. What is meant by Quadrature Modulation?
2. What is QPSK?
3. What are the advantages of QPSK?
4. What are I and Q signals in QPSK?
5. What is the bandwidth of QPSK?
96
Experiment 11
Objective:
To perform Analog Time Division Multiplexing & Demultiplexing and also Digital Time
Division Multiplexing & Demultiplexing.
Equipment Required:

3. Connecting cords
Theory: Time Division Multiplexing (TDM):
It is a technique of transmitting multiple information on the same channel. As can be

noticed from the figure 11.1 below; the samples consist of short pulses followed by
another pulse after a long time interval. This no-activity time intervals can be used to
include samples from the other channels as well. This means that several information can
be transmitted over a single channel by sending samples from different information
sources at different moments in time. This technique is known as Time Division
Multiplexing.
TDM is widely used in digital communication systems to increase the efficiency of the
transmitting medium.
Figure 11.1 Time Division Multiplexing of two signals
Analog TDM:
In this technique of multiplexing, analog signals appear at the input of multiplexer and
samples of signals are taken at different instants of time and are transmitted on the same
channel by interweaving them.
97
Digital TDM:
In this technique, digital signals like TTL or CMOS is multiplexed. It is different from
analog multiplexer since no sampling is done instead each input signal is selected by
digital control logic. Output at any time depends on the control bit governing input data
selection.
Objective: This experiment investigates the analog time division multiplexed signal
using the ST2503.
Procedure:
1. Turn all potentiometers of analog signal block to their minimum position.

2. Make connection as shown in figure 11.2.
3. Turn ‘On’ power to the ST2503 board.
4. Set analog signal amplitude equal to 4V.
5. Observe output of multiplexer on oscilloscope by connecting OUT terminal of 4
channel TDM block to oscilloscope.
6. Trigger the signal to view clean multiplexed signal.
Connection Diagram: Analog TDM Multiplexing
Figure 11.2
98
Objective: This experiment investigates the analog Time Division Demultiplexed signal
using the ST2503.
Procedure:

2. Turn ‘On’ power to the ST2503 board.
3. Observe all four outputs of demultiplexer on oscilloscope.
4. Decrease analog signal amplitude to observe corresponding change in demultiplexd output.
Connection Diagram: Analog TDM De-Multiplexing
Figure 11.3
Objective: This experiment investigates 16 Channel TDM using ST2503.
Procedure:

2. Turn On power to the ST2503 board.
3. Observe multiplexed data on oscilloscope.
4. Connect Out terminal of multiplexer to IN terminal of demultiplexer.
5. Observe demultiplexed 16 channel output on oscilloscope. Take output signal as external
trigger signal to oscilloscope to trigger demultiplexed output.
99
Connection Diagram: 16 Channel TDM
Figure 11.4
100
VIVA VOCE QUESTIONS
1. In what situation multiplexing is used?
2. Distinguish between the two basic multiplexing techniques?
3. Why guard bands are used in FDM?
4. Why sync pulse is required in TDM?
5. What is the difference between FDM & WDM?
101
Experiment 12
Objective:
To perform Quadrature Amplitude Modulation and Demodulation.
Equipment Required:

3. Connecting cords
Theory
The 16 – QAM Modulation Signal is the combination of I channel and Q channel. It has 16
symbol, each symbol consist of 4 bits (i.e. I – 2 bits and Q- 2 bits) is explained in the
constellation Diagram. In the 16-QAM, the number of amplitude shift is fewer than the phase
shifts. This is because, the amplitude changes are susceptible to noise and require greater shift
difference than do phase changes, the number of phases shifts used by a QAM system is larger
than the amplitude shifts. This meant that even with noise problem associated with amplitude
shifting is reduced. So QAM is lower susceptibility to noise. QAM is used to obtain higher
spectral efficiency, which potentially results in higher throughput of packetized data.
Figure 12.1 Block Diagram for 16-QAM Modulation
Figure 12.2 Output of 16-QAM Modulation Signal with Variable Data
102
The QAM Receiver (Demodulator) takes the modulated output from transmitter signal as input,
and it is multiplied with NCO Generated sine and cosine carriers to get I Demodulation and Q
Demodulation Signals. It is apparent that the demodulator performs the complement functions to
those in the modulator to get the transmitted data in the receiver.
Figure 12.3 QAM Receiver
Procedure:
1. Switch ‘On’ Power Switch.
2. For hardware mode Set DIP D1 to logic 0 (down position).
3. Observe and measure System clock at Test Point TP1.
4. Set DIP D2, D3, D4 to 000.
5. Observe Clock frequency at test point TP2 with respect to Ground, it should be150Hz.
6. Set DIP D1, D2, D3, D4 to 0000,0001,0010,0011, 0100, 0101, 0110, 0111 and Observe
their respective frequencies at Test point TP2.
7. Set pattern length by using DIP D5, D6 (00 – 64 bits, 01 – 32 bits, 10 – 16 bits, 11 – 8
bits), use Reset switch to analyze the better results for different pattern lengths and
observe corresponding Bit patterns at Test Point TP3.
8. Observe 4 Bit Encoded data at test point TP3.
9. Observe the 4 Bit Encoded ouputs of I [1] at test point TP4, I [0] at test point TP5, Q [1]
at test point TP6, Q [0] at test point TP7.
10. Observe the Binary to Gray coded outputs of IG [1] at test point TP8, IG [0] at test point
TP9, QG[0] at test point TP10, QG[1] at test point TP11.
11. Observe the Symbol Mapper outputs of I Channel at test point TP12 and Q Channel at
test point TP13.
12. Observe the ouput of the Constellation Patterns for I Channel at test point TP12 and Q
Channel at test point TP13 by setting the DSO in X-Y Mode.
103
13. Observe the outputs of I Channel Modulation at test point TP16 and Q Channel
Modulation at test point TP17.
14. Observe the outputs of Sine wave Generator at test point TP14 and Cosine wave
Generator at test point TP15.
15. Observe the output of 16-QAM Modulation at test point TP18.
16. Observe the outputs of I Channel Demodulation at test point TP21, Q Channel
Demodulation at test point TP22, NCO Sine wave Generator at test point TP19 and NCO
Cosine wave Generator at test point TP20.
Observations:
Figure 12.4 Output of QAM Signal with Variable Data
Figure 12.5 Outputs of Sine and Cosine Demodulator
104
VIVA VOCE QUESTIONS
1. What is meant by Quadrature Modulation?
2. What is QASK?
3. What is the bandwidth of QASK?
4. Out of amplitude, frequency and phase, what is varied in QAM carrier?
5. Is QAM an analog or digital scheme or both?
105

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Maharaja Agrasen Institute of Technology

(AICTE approved, Affiliated to GGSIPU, Delhi & ISO 9001:2008 Certified )

Name of Programme – B. Tech.

Subject – Digital Communication Lab

Course code – ETEC-357

Branch – Computer Science and Engineering

Course Status – Mandatory

Semester in which to be taught – V Semester

Engineering Hardware – Software Symbiosis: Practical exercises in all Engineering and

Liberalization and Globalization: The Institute endeavors to enhance technical and

Digitization of Learning Processes: The Institute provides seamless opportunities for

Entrepreneurship: The Institute strives to develop potential Engineers and Managers by

foundation with applied computing experiences and educating them about

their professional, and ethical responsibilities.

 To establish Industry-Institute Interaction, making students ready for the industrial

environment and be successful in their professional lives.

 To promote research activities in the emerging areas of technology convergence.

setting a ground for producing successful entrepreneur.

Engineering Graduates will be able to:

PSO 1: Professional Skills

Program Educational Objectives (PEOs)

PEO1: To train students to have successful careers in computer engineering field or to be

ETEC357.1 Demonstrate the concept of Sampling and Quantization.

Experiment with different techniques of analog to digital conversion by

ETEC357.3 Develop an understanding of digital multiplexing techniques

ETEC357.4 Demonstrate different digital modulation techniques

ETEC357.5 Compare and classify different line coding techniques

ETEC357.6 Implement the concept of M-ary digital modulation techniques.

INSTRUCTIONS TO LABORATORY TEACHERS

There will be two practical exams in each semester.

Internal Practical Exam

External Practical Exam

INTERNAL PRACTICAL EXAM

It is taken by the concerned lecturer of the batch.

MARKING SCHEME FOR THIS EXAM IS:

1. One mark for attendance

MARKING SCHEME FOR THIS EXAM IS:

Division of 60 marks is as follows:

Internal Marks + External Marks = Total marks given to the students

(40 marks) (60 marks) (100 marks)

Experiments given to perform can be from any section of the lab.

Paper code: ETEC 357 P C

Paper: Digital Communication Lab 2 1

1. To perform Signal Sampling and Reconstruction Techniques.

LIST OF EXPERIMENTS BEYOND CURRICULUM

S. No. Name of Equipment Model & Make Qty. Cost

Scientech (ST-2101) 1 7260

Scientech (ST-2105) 1 19800

Delta Adaptive delta & delta sigma Scientech (ST-2105) 1 15375

Scientech (ST-2112) 1 16125

9 (b) Block Code Decoder Trainer Scientech (ST2121B) 1 16625

Error Det. & Correction Cyclic Code

Scientech (DSO-7040C) 1 37125

Scientech (DSO-7040C) 1 37125

S. No. Name of Equipment Model & Make Quantity Cost

1 Expt. 1- To perform Signal Sampling and Reconstruction Techniques. 1

Expt. 2- To perform Time Division Multiplexed Pulse Code Modulation

Expt. 8- To perform Phase Shift Keying Modulation and Demodulation.

Expt. 11- To perform Analog Time Division Multiplexing &

Expt. 12- To perform Quadrature Amplitude Modulation and

1. 2101 with power supply cord

2. CRO with connecting probe

Figure 1.1 Basic Sampling Process