Form # IST-F-32/04

Institute of Space Technology Date of Issue 08-May-2014

CS No: EE-VD-LP-00
Lesson Plan
Page No. 1 of 4

DEPARTMENT & PROGRAM: Electrical Engineering & BS-Electrical Engineering

COURSE CODE-COURSE NAME: 508138-VLSI Design CR: 3-0

COURSE DESCRIPTION:
This course covers basic theories & techniques of Digital CMOS VLSI technology, including fundamental
concepts and structures of CMOS Fabrication processes, CMOS design rules, static & dynamic logic
structures interconnect analysis, and CMOS chip layout, power techniques, design tools and methodologies.

PRE-REQUISITE: Electronic Circuits & Devices, Electronic Devices

CO-REQUISITE: Nil

TEXT AND MATERIALS:

Textbook
1. CMOS VLSI Design by Neil, David

References Material:
1. VLSI Design by M. Michael Vai

RELEVANT PROGRAM LEARNING OUTCOME:

The course is designed so that students will achieve the PLO/s:
1. Design/Development of Solution : An ability to design solutions for complex electrical engineering
problems and design systems, components or processes that meet specified needs with appropriate
consideration for public health and safety environments. (PLO-3)

COURSE LEARNING OUTCOMES:

Upon successful completion of the course, the student will be able to:

1. Be able to use mathematical methods and circuit analysis models in analysis of CMOS digital VLSI
circuits.
2. Be able to create / analyze models of moderately sized CMOS Circuits that realize specified digital
functionality with required performance parameters.
3. Be able to apply CMOS technology specific design rules in the placement routing of transistors and
interconnects and to verify their timing power and parasitic effects.
4. Be able to have and utilize the understanding of CMOS construction, Fabrication processes
5. Be able to complete a significant VLSI design project
 Form # IST-F-32/04
Institute of Space Technology Date of Issue 08-May-2014
CS No: EE-VD-LP-00
Lesson Plan
Page No. 2 of 4

MAPPING BETWEEN PLO VS CLO:

PLO No.
CLO No. 3

1 
2 

3 

4 

5 

PRACTICAL APPLICATIONS:
The course will provide students with the insight of VLSI design along with hands on experience on industrial
standard EDA tools. The course will enable the students to develop their VLSI design skills so they can work
in fabless industry either as an employee or freelancer.
LECTURE PLAN:
Instruction 50%
Discussion 20%
Project 20%
Exercises/Tutorial 10%
Module Topic Reference Week/Lecture
I. Introduction 1-2
1.1. Brief history
1.2. Preview
1.3. MOS transistor
1.4. CMOS Logic Ch-1
1.5. CMOS fabrication & Layout
1.6. Logic Design
1.7. Circuit Design
1.8. Physical Design
I. CMOS Transistor Theory 3-4
2.1 Introduction
2.2 Long Channel IV Model
2.3 CV Model
Ch-2
2.4 Non Ideal IV Effects
2.5 DC Transfer Characteristics
2.6 Pitfalls/Summary
2.7 Exercises
 Form # IST-F-32/04
Institute of Space Technology Date of Issue 08-May-2014
CS No: EE-VD-LP-00
Lesson Plan
Page No. 3 of 4

II. CMOS Processing Technology 5-6

3.1 Introduction Ch-3
3.2 Wafer formation
3.3 Photo lithography
3.4 Oxidation
3.5 Source drain formation (ion
implantation)
3.6 Contacts and metallization
(PVD)
3.7 Layout Design rules
3.8 CAD
III. Delay Ch-4 7-8
4.1 Introduction
4.2 Transient Response
4.3 RC Delay Model & Elmore Delay
4.4 Logical Effort of Paths

III Power Ch- 5 9-10

5.1 Introduction
5.2 Dynamic power
5.3 Static power
5.4 Energy Delay optimization
5.5 Low Power Techniques

III Interconnects Ch- 6 11-12

6.1 Introduction
6.2 Dynamic power
6.3 Static power
6.4 Energy Delay optimization
6.5 Low Power Techniques

IV Combinational Circuit Design Ch- 9 13-14

7.1 Introduction
7.2 Circuit Families
7.3 Silicon on Insulator (SOI)
7.4 Subthreshold Circuit Design
7.5 Historical Perspective
7.6 Circuit Pitfalls

IV Sequential Circuit Design Ch- 10 15-16

8.1 Introduction
8.2 Sequencing Static Circuits
 Form # IST-F-32/04
Institute of Space Technology Date of Issue 08-May-2014
CS No: EE-VD-LP-00
Lesson Plan
Page No. 4 of 4

8.3 Circuit Design of Latches & Flip

Flops
8.4 Static Sequencing Element
Methodology
8.5 Sequencing Dynamic Circuits
8.6 Synchronizers

Final Examination
COURSE TARGETS:

Learning Domain with

Module No. CLO No. Teaching Methodology Assessment Methodology
Level
I 1 Lecture, Discussion Exam C3
2 Lecture, Discussion Exam C3
III
3 Lecture, Discussion Exam C3
II 4 Lecture, Discussion Exam C3
Mini Presentation
IV 5 Discussion/Project C3
Project

ASSESMENT:
Assignments 5%
Quizzes 5%
OHT Exam 30%
Presentation 10%
Project 10%
Final Exam 40%
_____________________________
Total 100%

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