BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani

Pilani Campus
Instruction Division

Course Handout (Part – II)

Course No : EEE/INSTR/CS F241

Course Title : CS/EEE/INSTR F241 Microprocessor Programming & Interfacing
Instructor-in- Charge : Dr. Nitin Chaturvedi
Instructor : Dr. Vinay Chamola, Dr. Puneet Mishra, G S Sesha Chalapathi, Devesh
Samaiya , Kari Babu Ravi Teja
email : nitin80@pilani.bits-pilani.ac.in

1. Scope and Objective :

This course is a basic introduction to processor ISA, Assembly programming, Computer &
Embedded Architecture. Intel 80x86 is used as a platform through the course. 8086 - 80486
Programmers model of processor, processor architecture; Instruction set, modular assembly
programming using subroutines, macros etc.; Timing diagrams; Concept of interrupts: hardware
& software interrupts, Interrupt handling techniques, Interrupt controllers. Types of Memory &
memory interfacing. Programmable Peripheral devices and I/O Interfacing, DMA controller and
its interfacing. Design of processor based system.

2. Text Book:

Barry B Brey, The Intel Microprocessors .Pearson, Eight Ed. 2009.

3. Reference Books:

Douglas V Hall, Microprocessor and Interfacing, TMH, Second Edition.

4. Course Plan :

Lect. Learning Objectives Topics to be covered Reference to Text

No.

1. Introduction to Compute Architecture, Chapter 1

Microprocessor and Memory & I/O organization,
Microcomputers CISC/RISC processors

2-4 Microprocessor & its Programming Model, Real & Chapter 2

architecture Protected Addressing mode,
memory paging, Flat mode

_
 BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani
Pilani Campus
Instruction Division

memory

5-6 Assembly Programming Addressing Modes Chapter 3

7-12 Assembly Programming Instruction Set & ALP Chapter 4-6, 8

13-15 8086/8088 Hardware Pin Out, Modes of operation, Chapter 9

Specifications Clocking, Buses

16-19 Memory Interface Memory Devices, Address Chapter -10

Decoding- Memory Interface
8086- 80386

20 I/O Interfacing Basic I/O interfacing (I/O Chapter 11.1, 11.2

mapped I/O and Memory
mapped I/O)
I/O port address decoding

21 Interrupts Types of interrupts, Vector Chapter 12.1, 12.2,

tables, Priority Schemes

22-29 Programmable Peripheral 8255,8254,ADC,DAC, 8259 Chapter 11.3-11.6 & 12.3 -12.6
Devices

30-32 DMA controller 8Basic Operation, 8237, Chapter -13

Shared Bud, Disk Memory
Systems, Video Displays

33-35 Bus Interace ISA, PCI, Com, USB,AGP Chapter 15

36-38 Advanced Processors 80186-80286 Chapter 16

39-41 Advanced Processors 80386-80486 Chapter 17

Self-Study Topics-
Microcontroller
Architecture -8051

5. Evaluation Scheme :

SL. No Component & Nature Duration Weightage Date Nature

1 Quizzes ---- 40 (13.3%) Continuous Continuous

_
 BIRLA INSTITUTE OF TECHNOLOGY AND SCIENCE, Pilani
Pilani Campus
Instruction Division

2 Lab Quiz/Assignments ---- 40 (13.3%) Continuous Continuous

3 Mid-Semester Test 90 min. 80 (~26%) 6/3 9:00 - OB/CB
10:30 AM
4 Design Assignment -- 20 (~7%) Tentative
20/04/2018

5 Comprehensive Exam 3 hours 120 (40%) 3/5 FN OB/CB

6. Chamber Consultation Hour: To be announced in the class

7. Make-up Policy: Make up will be allowed for genuine cases. Prior application should be sent for
seeking the same. No make up for Quiz, Lab.
8. Course Notice: Will be displayed on Nalanda Notice board

Instructor-in-Charge
CS/EEE/INSTR F241