Behavioral Modeling I

1
Structural vs. Behavioral Descriptions
module my_module(…);
…
assign …; // continuous assignment
and (…); // instantiation of primitive
adder_16 M(…); // instantiation of module

always @(…) Structural, no order

begin … end

initial Behavior, in order in each procedure

begin … end
endmodule

2
Behavioral Descriptions In General
Co-exists with gate instantiations
Not all descriptions synthesize
Not all synthesized descriptions are desirable
Non-structural behaviors
◼ Continuous assignment
◼ initial Behavioral
◼ always Procedural
Within a module
◼ Multiple behaviors are allowed
◼ Nested behaviors are not allowed

3
Behavioral Statements
initial | always initial
single_statement; | ◼ Activated from tsim = 0
Executed once
begin ◼

◼ Initialize a simulation
block_of_statements;
always
end
◼ Activated from tsim = 0
◼ Executed cyclically
◼ Continue till simulation
terminates

4
Example of Behavioral Statement
module clock1 ( clk );
parameter half_cycle = 50;
parameter max_time = 1000;
output clk;
clk
reg clk;
initial
clk = 0;
always
begin 50 100 150 200 tsim
#half_cycle clk = ~clk;
end
initial
#max_time $finish;
endmodule

ELEN 468 Lecture 7 5

Assignment
Continuous assignment
◼ Values are assigned to net variables due to some
input variable changes
◼ “assign …=… “
Procedural assignment
◼ Values are assigned to register variables when
certain statement is executed in a behavior
◼ Procedural assignment, “=“
◼ Procedural continuous assignment, “assign …=…
[deassign] “
◼ Non-blocking assignment, “<=“

6
Blocking and Non-blocking Assignment
initial Blocking assignment “=“
begin
◼ Statement order matters
a = 1;
b = 0; ◼ A statement has to be
a = b; // a = 0; executed before next
b = a; // b = 0; statement
end Non-blocking assignment
initial “<=“
begin
a = 1;
◼ Concurrent assignment
b = 0; ◼ If there are multiple non-
a <= b; // a = 0; blocking assignments to same
b <= a; // b = 1; variable in same behavior,
end latter overwrites previous
7
Procedural Continuous Assignment

Continuous assignment establishes

static binding for net variables
Procedural continuous assignment
(PCA) establishes dynamic binding for
variables
◼ “assign … deassign” for register
variables only
◼ “force … release” for both register and
net variables

8
“assign … deassign” PCA
module flop ( q, qbar, preset,
Binding takes effect clear, clock, data );
when PCA statement is …
assign qbar = ~q;
executed initial
Can be overridden by q = 0;
another PCA statement always @ ( negedge clk )
q = data;
“deassign” is optional always @ ( clear or preset )
“assign” takes control, begin
“deassign” release if ( !preset ) assign q = 1;
else if ( !clear ) assign q = 0;
control else deassign q;
end
endmodule

9
Example of assign
module mux4_PCA(a, b, c, d, select, y_out);
input a, b, c, d; input [1:0] select;
output y_out; reg y_out;

always @(select) y_out changes with a;

begin
if (select == 0) assign y_out=a;
else if (select == 1) assign y_out=b;
else if (select == 2) assign y_out=c;
else if (select == 3) assign y_out=d;
else assign y_out=1’bx;
end

endmodule

10
Alternative
module mux4_PCA(a, b, c, d, select, y_out);
input a, b, c, d; input [1:0] select;
output y_out; reg y_out;

always @(select or a or b or c or d)
begin Value of ‘a’ is assigned to
if (select == 0) y_out=a; y_out at this time
else if (select == 1) y_out=b;
else if (select == 2) y_out=c;
else if (select == 3) y_out=d;
else y_out=1’bx;
end

endmodule

11
“force … release” PCA
force sig1 = 0;
force sig2 = 1; modA
Sig3 = 0;
sig1
#9 sig3 = 1;
… sig2
modB
release sig1;
sig3
release sig2;

Similar to “assign…deassign”
Can be applied to net variables
Often applied in testing

12
Comparisons of Assignment
mode
Output of Continuous Procedural assign … force …
primitive assignment assignment deassign release
PCA PCA
Variable Net Net Register Register Net and
Seq-reg register
description Structural Structural Behavioral Behavioral Behavioral

binding Static Static Dynamic, Dynamic, Dynamic,

one shot continuous continuous

13
Behavioral Descriptions II

14
Procedural Timing Control
Delay control
Event control
Named events
“wait” construct

15
Delay Control Operator (#)
initial
begin
#0 in1 = 0; in2 = 1;
#10 in3 = 1;
#40 in4 = 0; in5 = 1;
#60 in3 = 0;
end

16
Event Control Operator (@)
… Event -> identifier or expression
@ ( eventA or eventB ) begin When “@” is reached
… ◼ Activity flow is suspended
@ ( eventC ) begin ◼ The event is monitored
… ◼ Other processes keep going
end posedge: 0->1, 0->x, x->1
end
negedge: 1->0, 1->x, x->0
Cannot assign value to the event
variable inside the synchronized
behavior

17
Named Event
module modA (…);
…
Also called abstract event
event sth_happens; // declaration Declared only in module
always
with keyword event
…
->sth_happens; // trigger event Must be declared before
end it is used
endmodule
Event is triggered by “->”
module modB(…); Provide high level inter-
…
module communication
always @
(top_mod.modA.sth_happens) without physical details
…
endmodule

18
Example of Named Event
module flop_event ( clk, reset, data, q, q_bar );
input clk, reset, data;
output q, q_bar;
reg q;
event up_edge;

assign q_bar = ~q;

always @ ( posedge clk ) -> up_edge;

always @ ( up_edge or negedge reset )

begin
if ( reset == 0 ) q = 0; else q = data;
end
endmodule

19
The “wait” Construct
module modA (…); Activity flow is
…
suspended if
always
begin
expression is false
… It resumes when the
wait ( enable ) ra = rb; expression is true
…
end
Other processes keep
endmodule going

20
Intra-assignment Delay:
Blocking Assignment
// B = 0 at time 0
If timing control
// B = 1 at time 4
… operator(#,@) on LHS
#5 A = B; // A = 1 ◼ Blocking delay
C = D;
◼ RHS evaluated at (#,@)
…
A = #5 B; // A = 0 ◼ Assignment at (#,@)
C = D;
…
If timing control
A = @(enable) B; operator(#,@) on RHS
C = D; ◼ Intra-assignment delay
…
A = @(named_event) B;
◼ RHS evaluated immediately
C= D; ◼ Assignment at (#,@)
…

21
Intra-assignment Delay:
Non-blocking Assignment
always begin In 1st cycle, “acc” is sampled
@ ( posedge clk ) What if no “bus” change in the same
G <= @ (bus) acc; cycle?
C <= D; // not blocked In next cycle, “acc” is sampled again
end Value of “acc” from previous cycle is
overwritten
Warning message

Sampling RHS immediately in the latest cycle

Wait for time control to execute assignment
Subsequent assignments are not blocked

22
Be Cautious
module or8( y, a, b ); Model combinational logic
input [7:0] a, b;
by one-shot (initial)
output [7:0] y;
reg [7:0] y;
behavior
Valid
initial begin
Not preferred
assign y = a | b;
end Not accepted by synthesis
endmodule tool

23
Example
initial begin
a = #10 1; t a b c d e f
b = #2 0; 0 x x x x x x
c = #3 1;
end
2 x x x x 0 x
3 x x x x 0 1
initial begin 10 1 x x 1 0 1
d <= #10 1; 12 1 0 x 1 0 1
e <= #2 0; 15 1 0 1 1 0 1
f <= #3 1;
end

24
Tell the Differences
always @ (a or b)
y = a|b; Which one describes or gate?

always @ (a or b)
#5 y = a|b; Event control is blocked
always @ (a or b)
y = #5 a|b;

always @ (a or b)
y <= #5 a|b;

25
Simulation of Assignments
For each given time step
◼ Evaluate all Right-Hand-Side
◼ Execute blocking assignment
◼ Execute non-blocking assignment that do not have
intra-assignment timing control
◼ Execute past non-blocking assignment that is
scheduled at this time
◼ Execute $monitor. However, $display is
executed whenever it is encountered.
◼ Increment time step

26
Simulation of Non-blocking Assignment

Normally the last always …

assignment at certain begin
simulation time step A <= B;
If it triggers other end
blocking assignments, it
…
is executed before the
blocking assignment it always …
triggers begin
C = @(A) D;
end

27
Example
initial begin initial begin
a = 1; a = 1;
b = 0; b = 0;
a <= b; a <= b;
b <= a; b <= a;
$display(“a=%b b=%b”, $monitor(“a=%b b=%b”,
a, b); a, b);
end end

a=1 b=0 a=0 b=1

28
Repeated Intra-assignment Delay
regA = repeat (5) @ ( negedge clk ) regB;

begin
tmp = regB;
@ ( negedge clk );
@ ( negedge clk );
@ ( negedge clk );
@ ( negedge clk );
@ ( negedge clk );
regA = tmp;
end

29
Indeterminate Assignment
module multi_assign();
reg a, b, c, d;
initial begin Multiple assignments
#5 a = 1; b = 0; end are made to same
always @ ( posedge a )
c = a;
begin
variable in different
end behavior
always @ ( posedge a ) begin
c = b; Value depends on
end code order or
always @ ( posedge a )
d = b;
begin
vendor specifications
end Similar to race-
always @ ( posedge a ) begin
d = a; conditions in
end hardware
endmodule

30
Behavioral Descriptions III

31
Activity Flow Control ( if … else )
if ( A == B ) P = d;
Syntax: if ( expression )
if ( B < C ); statement [ else statement ]
Value of expression
if ( a >= b )
◼ 0, x or z => false
begin
… ◼ Non-zero number => true
end

if ( A < B ) P = d;
else P = k;

if ( A > B ) P = d;
else if ( A < B ) P = k;
else P = Q;

32
Conditional Operator ( ? … : )
always @ ( posedge clock )
yout = ( sel ) ? a + b : a – b;

Conditional operator can be applied in

• either continuous assignments

• or behavioral descriptions

33
The case Statement
module mux4 ( a, b, c, d, select, yout );
input a, b, c, d;
Case items are
input [1:0] select;
output yout;
examined in order
reg yout; Exact match between
always @( a or b or c or d or select )
case expression and
begin
case ( select )
case item
0: yout = a; casex – don’t care bits
1: yout = b;
with x or z
2: yout = c;
3: yout = d; casez – don’t care bits
default yout = 1`bx; with z
endcase
endmodule

34
Expression Matching in case Construct
Expression or case casex casez
case_item
0 0 0 0
1 1 1 1
x x 01xz x
z z 01xz 01xz
? N/A N/A 01xz

always @ ( pulse )
casez ( word )
8`b0000???? : ;
……
35
Loops
repeat
for loop
while loop
forever
disable

36
The repeat Loop
…
word_address = 0;
repeat ( memory_size )
begin
memory [word_address] = 0;
word_address = word_address + 1;
end
…

37
The for Loop
reg [15:0] regA;
integer k;
… Loop variables have to be either
integer or reg
for ( k = 4; k; k = k – 1 )
begin
regA [ k+10 ] = 0;
regA [ k+2 ] = 1;
end
…

38
The while Loop
begin cnt1s Loop activities suspend
reg [7:0] tmp; external activities
module sth ( externalSig );
cnt = 0;
input externalSig;
tmp = regA;
while ( tmp )
always
begin
begin
cnt = cnt + tmp[0];
while ( externalSig );
tmp = tmp >> 1;
end
end
endmodule
end

Replacement for
while ?
39
The disable Statement
begin
k = 0;
for ( k = 0; k <= 15; k = k + 1 )
if ( word[ k ] == 1 ) disable ;
end

Terminate prematurely in a block of procedural

statements

40
The forever Loop
parameter half_cycle = 50;

initial
begin : clock_loop
clock = 0;
forever
begin
#half_cycle clock = 1;
#half_cycle clock = 0;
end
end

initial
#350 disable clock_loop;

41
“always” and “forever”

always forever
Declares a behavior Computational activity
flow within a behavior
Cannot be nested Can be nested
Executes when Executes when
simulation begins statement is reached

42
Parallel Activity Flow
… module race ( … );
fork // t_sim = 0 …
#50 wave = 1; fork
#150 a = b;
#100 wave = 0;
#150 c = a;
#150 wave = 1;
join
#300 wave = 0;
endmodule
// executes at t_sim = 300
join module fix_race ( … );
… …
fork
a = #150 b;
Not supported by c = #150 a;
synthesis join
endmodule
For simulation in
testbench 43
Tasks and Functions
Sub-programs that encapsulate and
organize a description
◼ Tasks – create a hierarchical organization
of the procedural statements
◼ Functions – substitute for an expression

44
Tasks
Declared within a module
Referenced in a behavior
◼ In module where the task is declared
◼ From any module through hierarchical de-referencing
All arguments to the task are passed by value, not pointer
Parameters can be passed to a task, variables and parameters
within the parent module of a task are visible to the task
A task may not be used within an expression
Statements in a task may contain delay and event control
A task can call itself

45
Example of Task
module bit_counter (data, count);
input [7:0] data;
output [3:0] count; reg [3:0] count;

always @(data) t(data, count);

task t;
input [7:0] a; output [3:0] c; reg [3:0] c;
reg [7:0] tmp;
begin c = 0; tmp = a;
while (tmp)
begin
c = c + tmp[0];
tmp = tmp >> 1;
end
end
endtask
endmodule

ELEN 468 Lecture 9 46

Functions
Implement only combinational behavior
Compute and return a value for given parameters
Have no timing/event control
May call other functions, not itself
Can be referenced anywhere an expression can exist
May not declare any output or inout port
Must have at least one input port

ELEN 468 Lecture 9 47

Example of Function
module word_aligner (w_in,
w_out);
input [7:0] w_in;
output [7:0] w_out;

assign w_out = align

(w_in);

function [7:0] align;

input [7:0] word;
begin
align = word;
if (align != 0)
while (align[7]
ELEN 468==
Lecture 9 48
Static vs. Dynamic Timing Analysis

Static timing analysis Dynamic timing analysis

◼ Fast ( simulation )
◼ Consider all paths ◼ Depends on input stimulus
◼ Pessimism by considering vectors
false paths which are ◼ Do not report timing on
never exercised false paths
◼ With large number of
testing vectors
 Accurate
 Slow

ELEN 468 Lecture 9 49

Example of Static Timing Analysis
7/4/-3 2
9/6/-3
5/3/-2 3 11

20/17/- 3 23/20/-
3
7 2
4/7/3 4 18/18/0 3
8/8/0 3 11/11/
0
Arrival time: input -> output, take max
Required arrival time: output -> input, take min
Slack = required arrival time – arrival time

ELEN 468 Lecture 9 50

Setup Time Constraint
$setup(data, posedge clock, 5);
It specifies an interval before the active
edge of clock
Data must arrive before the interval

5 5
clock

data
ELEN 468 Lecture 9 51
Hold Time Constraint
$hold(data, posedge clock, 2);
It specifies an interval after the active
edge of clock
Data must be stable in the interval

2 2
clock

data
ELEN 468 Lecture 9 52
Setup and Hold Time
$setuphold(data, posedge clock, 5, 2);

2 2
5 5
clock

data

ELEN 468 Lecture 9 53

Signal Period
$period(posedge clock, t_limit);
Signal period must be sufficiently long

clock cycle time

clock

t_limit

ELEN 468 Lecture 9 54

Pulse Width
$width(posedge clock, t_mpw);
The width of the clock pulse must not
be too small
clock pulse width

clock

t_mpw

ELEN 468 Lecture 9 55

Clock Skew
$skew(negedge clk1, negedge clk2,
t_skew);
Signal skew is the arriving time difference of
two clock signals
Clock skew should be limited

clk1
skew
clk2
ELEN 468 Lecture 9 56
Recovery Time
$recovery(negedge bus_control,
bus_driver, t_rec);
Time to go from Z to 0 or 1

Bus_control

Bus_driver Z

t_rec
ELEN 468 Lecture 9 57
No Signal Change
$nochange(posedge clk, data, -5, 2);
Equivalent to
◼ $setuphold(data, posedge clk, 5, 2);

ELEN 468 Lecture 9 58

Finer-grain and Conditional Events
Timing Check

$setup ( data, edge 01 clk, 5 );

$hold ( data, edge 10 clk, 2 );
$setup ( data, posedge clk &&& (!reset), 4 );

ELEN 468 Lecture 9 59

De-Reference
To reference a variable defined inside
a behavioral block
◼ X.Y.k

module X( … );
begin : Y
reg k;
…
end
end

ELEN 468 Lecture 9 60

ELEN 468
Advanced Logic Design

Lecture 10
Behavioral Descriptions IV

ELEN468 Lecture 10 61
Finite State Machines
Mealy Machine
input output
Next state and output
Combinational logic Register

clock

Moore Machine
input
Next state Output output
Register
Combinational logic Combinational logic
clock

ELEN468 Lecture 10 62
Explicit Finite State Machines 1
module FSM_style1 ( … );
input …;
output …;
parameter size = …;
reg [size-1:0] state;
wire [size-1:0] next_state;

assign outputs = …; // function of state and inputs

assign next_state = …; // function of state and inputs

always @ ( negedge reset or posedge clk )

if ( reset == 1`b0 ) state = start_state;
else state <= next_state;
endmodule

ELEN468 Lecture 10 63
Explicit Finite State Machines 2
module FSM_style2 ( … );
input …;
output …;
parameter size = …;
reg [size-1:0] state, next_state;

assign outputs = …; // function of state and inputs

always @ ( state or inputs )

begin
// decode for next_state with case or if statement
end

always @ ( negedge reset or posedge clk )

if ( reset == 1`b0 ) state = start_state;
else state <= next_state;
endmodule

ELEN468 Lecture 10 64
Explicit Finite State Machines 3
module FSM_style3 ( … );
input …;
output …;
parameter size = …;
reg [size-1:0] state, next_state;

always @ ( state or inputs )

begin
// decode for next_state with case or if statement
end
always @ ( negedge reset or posedge clk )
if ( reset == 1`b0 ) state = start_state;
else begin
state <= next_state;
outputs <= some_value ( inputs, next_state );
end
endmodule

ELEN468 Lecture 10 65
Summary of Explicit FSM
States are defined explicitly
FSM_style1
◼ Minimum behavioral description
FSM_style2
◼ Use behavioral to define next state, easier
to use
FSM_style3
◼ Output synchronized with clock

ELEN468 Lecture 10 66
FSM Example: Speed Machine
a = 1, b = 0

a: accelerator
low stopped b=1
b=1 b: brake
a = 1, b = 0

accelerator
b=1

brake speed
clock

b=1
medium high a = 1, b = 0

a = 1, b = 0

ELEN468 Lecture 10 67
Verilog Code for Speed Machine
// Explicit FSM style always @ ( state or accelerator or brake )
module speed_machine ( clock, if ( brake == 1`b1 )
accelerator, brake, speed ); case ( state )
stopped: next_state <= stopped;
input clock, accelerator, brake; s_low: next_state <= stopped;
output [1:0] speed; s_medium: next_state <= s_low;
s_high: next_state <= s_medium;
reg [1:0] state, next_state;
default: next_state <= stopped;
endcase
parameter stopped = 2`b00; else if ( accelerator == 1`b1 )
parameter s_slow = 2`b01; case ( state )
parameter s_medium = 2`b10; stopped: next_state <= s_low;
parameter s_high = 2`b11; s_low: next_state <= s_medium;
s_medium: next_state <= s_high;
assign speed = state; s_high: next_state <= s_high;
default: next_state <= stopped;
always @ ( posedge clock ) endcase
state <= next_state; else next_state <= state;
endmodule

ELEN468 Lecture 10 68
Implicit Finite State Machine
module speed_machine2 ( clock, always @ ( posedge clock )
accelerator, brake, speed ); if ( brake == 1`b1 )
case ( speed )
input clock, accelerator, brake; `stopped: speed <= `stopped;
output [1:0] speed; `low: speed <= `stopped;
reg [1:0] speed; `medium: speed <= `low;
`high: speed <= `medium;
`define stopped 2`b00 default: speed <= `stopped;
`define low 2`b01 endcase
`define medium 2`b10 else if ( accelerator == 1`b1 )
`define high 2`b11 case ( speed )
`stopped: speed <= `low;
`low: speed <= `medium;
`medium: speed <= `high;
`high: speed <= `high;
default: speed <= `stopped;
endcase
endmodule

ELEN468 Lecture 10 69
Another Implicit FSM Example
module speed_machine3 ( clock, always @ ( posedge clock )
accelerator, brake, speed ); case ( speed )
`stopped: if ( brake == 1`b1 )
input clock, accelerator, brake; speed <= `stopped;
output [1:0] speed; else if ( accelerator == 1`b1 )
reg [1:0] speed; speed <= `low;
`low: if ( brake == 1`b1 )
`define stopped 2`b00 speed <= `stopped;
`define low 2`b01 else if ( accelerator == 1`b1 )
`define medium 2`b10 speed <= `medium;
`define high 2`b11 `medium: if ( brake == 1`b1 )
speed <= `low;
else if ( accelerator == 1`b1 )
speed <= `high;
`high: if ( brake == 1`b1 )
speed <= `medium;
default: speed <= `stopped;
endcase
endmodule

ELEN468 Lecture 10 70
Handshaking
Server Client

data_out 8 data_in

server_ready server_ready

client_ready client_ready

ELEN468 Lecture 10 71
Algorithm State Machine (ASM) Chart
s_idle / SR = 0 c_idle / CR = 0
# #
s_wait / SR = 1 c_wait / CR = 1

0 0
CR SR
1 # 1 #

s_serve / SR = 1 c_client / CR = 1
# #
s_done / SR = 0 c_done / CR = 0

# #
1 0
CR 0 1 SR

ELEN468 Lecture 10 72
Verilog Code for Handshaking
module server ( d_out, s_ready, c_ready ); module client ( d_in, s_ready, c_ready );
output [3:0] d_out; output s_ready; input [3:0] d_in; input s_ready;
input c_ready; output c_ready;
reg s_ready; reg [3:0] d_out; reg c_ready; reg [3:0] data_reg;
task pause; task pause;
reg [3:0] delay; reg [3:0] delay;
begin delay = $random; begin delay = $random;
if ( delay == 0 ) delay = 1; if ( delay == 0 ) delay = 1;
#delay; end #delay; end
endtask endtask
always always begin
forever begin c_ready = 0; pause; c_ready = 1;
s_ready = 0; pause; s_ready = 1; forever begin
wait ( c_ready ) pause; wait ( s_ready ) pause;
d_out = $random; pause; data_reg = d_in; pause; c_ready = 0;
s_ready = 0; wait ( !s_ready ) pause; c_ready = 1;
wait ( !c_ready ) pause; end
end end
endmodule endmodule

ELEN468 Lecture 10 73
Polling Circuit
Each client cannot be served
for 2 consecutive cycles

client1 service
clock 3 request
Server client2 Polling
reset circuit 2
service
client3 code
Highest
priority

ELEN468 Lecture 10 74
State Transition Graph for Polling Circuit
100

Client3
Service request
11
-01
-1- 1--
1-- 000 1--

010 000 000 001

Client2 None Client1
10 01- 00 001 01
000 0-1
Service code 01-

ELEN468 Lecture 10 75
Verilog Code for Polling Circuit
module polling ( s_request, s_code, clk, rst ); task poll_them;
`define client1 2`b01 input [1:0] present_client;
`define client2 2`b10 input [3:1] s_request;
`define client3 2`b11 output [1:0] next_client;
`define none 2`b00 reg [1:0] contender; integer N;
input [3:1] s_request; begin: poll
input clk, rst; output [1:0] s_code; contender = `none;
reg [1:0] next_client, present_client; for ( N = 3; N >= 1; N = N – 1 )
always @ ( posedge clk or posedge rst ) begin: decision
begin if ( rst ) if ( s_request[N] ) begin
present_client = `none; if ( present_client == N )
else present_client = next_client; contender = present_client;
end else begin next_client = N;
assign s_code[1:0] = present_client; disable poll; end
always @ ( present_client or s_request ) end end
begin if (( next_client == `none ) &&
poll_them ( present_client, s_request, ( contender ))
next_client ); next_client = contender; end
end endtask endmodule

ELEN468 Lecture 10 76
Test Bench for Polling Circuit
moduel test_polling; initial
reg [3:1] s_request; reg clk, rst; begin
wire [1:0] s_code; #20 s_request = 3`b100;
wire sreq3 = M1.s_request[3]; #20 s_request = 3`b010;
wire sreq2 = M1.s_request[2]; #20 s_request = 3`b001;
wire sreq1 = M1.s_request[1]; #20 s_request = 3`b100;
wire [1:0] NC = M1.next_client; #40 s_request = 3`b010;
wire [1:0] PC = M1.present_client; #40 s_request = 3`b001;
wire [3:1] s_req = s_request; end
wire [1:0] s_cd = s_code; initial
polling M1 ( s_request, s_code, clk, rst ); begin
initial begin #180 s_request = 3`b111;
clk = 0; forever #10 clk = ~clk; #60 s_request = 3`b101;
end #60 s_request = 3`b011;
initial #400 finish; #60 s_request = 3`b111;
initial begin #20 rst = 1;
rst = 1`bx; end
#25 rst = 1; #75 rst = 0; endmodule
end

ELEN468 Lecture 10 77
Exercise 2
ELEN468 Lecture 10 78
Find Error
module something_wrong ( y_out, x1, x2 );
output y_out;
input x1, x2;

`define delay1 3; // No “;”

`define delay2 4;
`define delay3 5;

nand #(delay1, delay2, delay3) ( y_out, x1, x2 );

// No turnoff delay for non-3-state gate
// Remove “delay3”, or replace “,” with “:”
endmodule

ELEN468 Lecture 10 79
Timing Models
Determine time values in simulation
◼ `timescale 10ns/1ps 2.447 24.470ns
◼ `timescale 1ns/100ps 2.447 2.4ns
What is the typical falling delay from a1
to y2?
◼(a1,a2 *> y1, y2) = (7:8:9, 6:10:12);
10

ELEN468 Lecture 10 80
Correct Error
module flop ( clock, data, q, qbar, reset );
input clock, data, reset;
output q, qbar;
reg q;

assign qbar = ~q;

// This cannot model flip-flop properly

// when reset rises and clock == 1
always @ ( posedge clock or reset )
begin
if ( reset == 0 ) q = 0;
else if ( clock == 1 ) q = data;
end
endmodule

ELEN468 Lecture 10 81
What will happen?
module A ( … );
…
initial
clock = 0;

// Nothing will happen

always @ ( clock )
clock = ~clock;

…
endmodule

ELEN468 Lecture 10 82