Dell/Compal confidential schematic document

A B C D E
MODEL NAME : FDQ50 / FDC55

PCB NO : LA-J191P DAC0000X000
1
MB
FB
KB
LA-J191P DAC0000X000
LS-H821P DA60027F00S
LS-H822P DA4002TR00S
Dell/Compal Confidential 1
EDP w/TS
EDP w/o TS
LF-H821P
LF-H824P
DA30001AF00
DA30001AD00 Schematic Document
CCD LF-H822P DA30001AC00
LED LF-F825P DA30001AE00
KBC
IO
LF-H82AP
LF-H823P
DA30001BD00
DA30001AB00
Fiorana CML CometLake H
2019-11-22
Rev: DVT2.1 0.4(X03)
@ N18PG62@
2 2
@EMC@ N19PQ1@
CONN@ N19PQ3Q@
TP@ N19PQVRAMS@
3PHASEI5@ N19PQVRAMH@
4PHASE62@ N19PQVRAMM@
4PHASE82@ NVPRO@
BreakDown@ VPRO@
EMC@ UMAP@
RF@ UMAX@
UMA@ XDP@
3
DIS@ QTJ0@
3
EMI@ QTJ1@
DAR@ QTJ2@
CNV@
4 4
Vinafix.com Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2019/11/30 Deciphered Date 2027/06/21 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P001-Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-J191P 0.4(X03)
Date: Friday, November 22, 2019 Sheet 1 of 100

A B C D E
A B C D E
256M*32 x4 =8Gb ,128-bit Memory SPI Flash (1.8V) USB2.0 Port3 CCG5 PD
GDDR6, VRAM * 4 (VBIOS 1MB) Memory Bus (DDR4) CYPD5126-40LQXIT
DDRIV EEC-SO-DIMM X2 P.48
8Gbit GDDR6 memory P.35~36 P.28 Intel Dual Channel P.23~24
CPU XDP 1.2V DDR4 2666 MHz
Conn. CML-H 32GB Max (4G, 8G,16G) USB3.1 Type C (TBT)
GB4D-128 R DDI x 1 port 3 DP/USB3 Re-driver
Conn.
GPU PS8802
1 GTX N18P-G0 4GB Processor CPU_DP3 P.47 (Gen 2 10Gbps) P.49
Power share
(AOZ1356) 1
Quadro PEG 3.0 x8 lane 45W 8C+2 USB_31 P.48

N19P-Q1 4GB 45W 6C+2
N19P-Q3 MaxQ /4GB
P.27~34
45W 4C+2 USB3.1 Type C (TBT) Power share
(AOZ1356)
42 x 28mm Conn. P.44
DDI x 1 port 2 TBT
(Gen 2 10Gbps) P.45
OLED/UHD/FHD 4096X2304 @60Hz BGA 1440 Balls DDI x 1 port1
Intel Titan Ridge
eDP *4 lane P.6~12
(4K*2K, eDP v1.4b, PSR2) CPU_DP1/DP2 (DP) - JHL7540 TBT Power share
P.3 PCI-E Gen3 x 4 PCH Port 13,14,15,16 P.42~43 USB3.1 Type C (TBT) (AOZ1356) P.44
DMI x4 Conn.
100MHz
P-SENSOR 8GB/s (Gen 2 10Gbps) P.45
SX9331 PCI-E Gen2 x 1 Port 7
P.40 PCI-E x4
M.2 Slot C Key-M
WLAN/BT 5.1 Solder down USB2.0 Port6 PCH Port 17,18,19,20
USB2.0 Port4 CCG5 PD
Harrison Peak 12x16 solder down SATA3.0 Port A7 (SATA/PCIe SSD Port2) CYPD5225-96BZXI
Samsung QC76_9D64T solder down CNVi P.69 USB2.0 Port5
MCU CYPD4126 P.44
Darwin2.0 antenna P.52
P.40
2
Port 1A 2
M.2 Slot C Key-M

RGB Camera for XPS USB2.0 Port11
IR Camera for Perision PCI-E x4 (SATA/PCIe SSD Port1)
720P HD P.38 Intel PCH Port 9,10,11,12 P.68
(leveraged with XPS 13 Modena )
Touch Panel I2C BUS Port0 (I2C0)

CNL-H-PCH SPI TPM 2.0
Conn. P.38 24 x 25mm ST33TPHF2XSPI
(Wacom G12+ Controller) x10 Common codeP.66
ARD NEED CHECK DMIC
connect to PCH
BGA 837 Balls
Digital MIC Conn. AMP TAS2770 Speaker x2(Main)P.57
P.38 P.57
QP21
I2S/I2C
ALS/P-Sensor Conn.
P.38
HD Audio Speaker x2
ALS/P-Sensor/DMIC Module
DMIC Audio Codec (twitter speaker)
Finger Print USB2.0 Port10 ALC3281
P.57
Conn.
contact USB 2.0 FFC P.66
3
(Power Button leveraged with (LaFerrari) )
P56
Headphone / Mic. Jack I/O Fuction Board 3
FB
( Combo ) ( Follow Italia)
SPI Flash
(BIOS 32MB)P.14 P13~22 PCI-E Gen3 x 1 Port 6
Redirver Card Reader SD4.0
x10 Common PCH Port 6
PI3EQX12902AZLE 3 in 1 Socket for UHS-II
FB RTS5243-GR SD/SDHC/SD3.0/SD 4.0
eSPI Bus FB FB
G3/SPI 48MHz I/O Fuction Board Connector P55

SMBUS
Power On/Off CKT. Keyboard Connector P59 KB Board
P.63
MEC 5107
DC/DC Interface CKT. LNG2DMTR
P.77~P.78 P.58
PWM PS/2 Battery Gauge

DC-IN Conn. I2C Port1 (I2C1)
P.82
Fan Control Touch Pad BCBUS KBC KSIO Int.KBD

ECE1117
4 4
P.64 P.63
HZH-1-TR C
Security Classification Compal Secret Data Compal Electronics, Inc.

P002-Block Diagram
0.4(X03)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-J191P
A B C D E
Vinafix.com
A
RE67 CE51 REV PHASE USB3.1 DESTINATION USB 2.0 DESTINATION USB OC# DESTINATION
240K 4700p PRE EVT
130K 4700p X00 EVT
1 USB3.0 PS8802 1 None 0
62K 4700p X00 DVT1
33K 4700p X01 DVT1.1
2 None 2 None 1
8.2K 4700p X02 DVT2
3 None 3 Type-C Conn 1 (Left Side) 2
4.3K 4700p X03 DVT2.1
2K 4700p
1K 4700p A00 PVT
4 None 4 Type-C Conn 1 (Right Side) 3 Type-C Conn 1 (Left Side)
5 None 5 Type-C Conn 2 (Right Side) 4 Type-C Conn 1 (Right Side)
6 None 6 None 5 Type-C Conn 2 (Right Side)
7 None 6
PCI EXPRESS DESTINATION USB3.0 DESTINATION 8 None 7
Lane 1 7 None 9 None
Lane 2 8 None 10 Finger Print

Titan Ridge
Lane 3 9 None 11 RGB CAMERA
Lane 4 10 None 14 NGFF-1 WLAN + BT
Lane 5 None
Lane 6 CNVi WLAN + BT CLKOUT_PCIE DESTINATION CLKOUT_PCIE DESTINATION
Lane 7 CARD READER 0 None 10 None
Lane 8 None 1 NGFF-2 SSD2 11 None
1 Lane 9 SSD 2 None 12 None 1
Lane 10 SSD SATA DESTINATION 3 NGFF-2 SSD1 13 None
Lane 11 SSD 0A N/A 4 CARD READER 14 None
Lane 12 SSD 1A SSD 5 Thunderbolt 15 None
Lane 13 None 0B N/A 6 NGFF-1 WLAN
Lane 14 None 1B N/A 7 GPU

Lane 15 None A2 N/A 8 None
Lane 16 None A3 N/A 9 None
Lane 17 SSD_2 A4 SSD
Lane 18 SSD_2 A5 N/A
Lane 19 SSD_2 The 30 HSIO lanes on PCH-H supports the following configurations:
1. Up to 24 PCIe* Lanes
— A maximum of 16 PCIe* Ports (or devices) can be enabled
‧ When a GbE Port is enabled, the maximum number of PCIe* Ports (or
devices) that can be enabled reduces based off the following:
Lane 20 SSD_2 Max PCIe* Ports (or devices) = 16 - GbE (0 or 1)
— PCIe* Lanes 1-4 (PCIe* Controller #1), 5-8 (PCIe* Controller #2), 9-12 (PCIe*
Controller #3), 13-16 (PCIe* Controller #4), 17-20 (PCIe* Controller #5), and
21-24 (PCIe* Controller #6) can be individually configured
2. Up to 6 SATA Lanes
— A maximum of 6 SATA Ports (or devices) can be enabled
— SATA Lane 0 has the flexibility to be mapped to Flex I/O Lane 16 or 18
— SATA Lane 1 has the flexibility to be mapped to Flex I/O Lane 17 or 19
DDI DESTINATION LPC DESTINATION 3. Up to 10 USB 3.1 Lanes
— A maximum of 10 USB 3.1 Ports (or devices) can be enabled
4. Up to 4 GbE Lanes
— A maximum of 1 GbE Port (or device) can be enabled
5. Supports up to 3 Remapped (IntelR Rapid Storage Technology) PCIe* storage
1 Titan Ridge ESPI/LPC0 MEC5107 devices
— x2 and x4 PCIe* NVMe SSD
— x2 IntelR Optane? Memory Device
— See the “ PC I Express * (PCIe*) ” chapt er f or t he P CH PCI e* Controllers,configurations
, and lanes that can be used for IntelR Rapid Storage Technology PCIe* storage support
2 Titan Ridge LPC1 DEBUG PORT 6. For unused SATA/PCIe* Combo Lanes, Flex I/O Lanes that can be configured as PCIe* or SATA,
the lanes must be statically assigned to SATA or PCIe* via the SATA/PCIe Combo Port Soft
Straps discussed in the SPI Programming Guide and
through the IntelR Flash Image Tool (FIT) tool.
3 DP/USB3 PS8802
Symbol Note : Security Classification Compal Secret Data Compal Electronics, Inc.
Vinafix.com Issued Date 2019/11/30 Deciphered Date 2027/06/21 Title
P003-Notes List
: means Digital Ground : means Analog Ground AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev

A
5 4 3 2 1
UZ1
Rail Name
PU400 RUN_ON_EC
Rail Name EM5209VF +3V_RUN
P.77
TPS51285BRUKR ALWON
Non VR-PG capable
Adapter _QFN20_3X3 +3.3VALW UZ5
Rail Name
P.83
PCH_3.3V_TS_EN
5-20V VR-PG capable G517AL1TP1U +3VS_TS
Type-C Port-L CCG5 PD P.77
CYPD5225-96BZXI FLAG capable
UZ37
Rail Name
D Type-C Port-L PWR Path ENVDD D
UZ6 Rail Name G517AL1TP1U +EDPVDD

P.77
G2176RB1U EN_INVPWR FLAG capable
EC +INV_PWR_SRC UZ17
MEC5107 P.38 Rail Name
VR-PG capable RUN_ON_EC
G517AL1TP1U +3VS_Hinge
ISL9538BHRTZ UZ7
P.77
-T_TQFN32_4X4 Rail Name FLAG capable
(NVDC) G2176RB1U IRCAM_EN UN3
Page:83 Rail Name
PD2 P.38 B+_CAM WLAN_PWR_EN
Type-C Port-R CCG5 PD VR-PG capable AOZ1336DI +3VS_WLAN
CYPD5126-40LQXIT P.77
P.82
Non VR-PG capable
UZ4
9-13.5V Rail Name
SIO_SLP_SUS#
APE8937GN2 +3V_PCH
P.77
Non VR-PG capable
Battery UN32
56/86W Rail Name
SSD_SCP_PWR_EN
APE8937GN2 +3.3VDX_SSD
P.77
Non VR-PG capable
UN36
Rail Name
SIO_SLP_SUS#
EM1109V-AD +1.2V_RUN
P.78
Non VR-PG capable
PU2700
MP2979AGQKT VR_ON Rail Name

-0130-Z_TQFN48
_6X6 Vcore_B+
P.88
VR-PG capable
PU400 UZ1
C Rail Name Rail Name C
TPS51285BRUKR ALWON RUN_ON_EC

+5VALW EM5209VF +5VS_RUN
_QFN20_3X3 P.77
Non VR-PG capable
P.83
VR-PG capable PU700
Rail Name
FBVDD_EN
RT8812AGQW-GP +1.35VS_VGA
P.96
Non VR-PG capable
PU1600 UZ30
Rail Name Rail Name
1V8_AON_EN
SY8286RAC SIO_SLP_SUS# AOZ1336DI +1.8V_GFX_AON
_QFN20_3X3 +1.8VALW P.37
Non VR-PG capable
P.94 UZ24
VR-PG capable Rail Name
1V8_MAIN_RUN_EN
AOZ1336DI +1.8V_GFX_RUN
P.37
Non VR-PG capable
UA3
Rail Name
AUD_PWR_EN
AOZ1336DI +1.8VS_AUDIO
P.57
Non VR-PG capable
PU500 UZ15
Rail Name Rail Name
SY8288RAC SIO_SLP_SUS# SUS_ON_EC_ST
+1VALW PS22961DNYR +VCCST
_QFN20_3X3 P.77
Non VR-PG capable
P.84
VR-PG capable UZ9
Rail Name
VCCSTG_EN
PS22961DNYR +VCCSTG
P.78
B
Non VR-PG capable
B
Rail Name UZ16

Rail Name
PU600 1.2V_DDR_EN VCCSTG_EN
1.2V_DDR TPS22961DNYR +1.2V_VCCPLL
NB685GQ-Z P.78
_QFN16_3X3 Non VR-PG capable
Rail Name
P.85 SM_PG_CTRL
VR-PG capable +0.6VS
PU800
Rail Name
NB681AGD-Z RUN_ON_P
_QFN13_2X3-SVR +0.95VS_VCCIO
P.87
VR-PG capable
PU900
Rail Name
NB691GG-Z PEX_VDD_EN
_QFN11_2X2 +1VS_GFXP
P.94
VR-PG capable
A A
Vinafix.com Security Classification

Issued Date 2019/11/30
Compal Secret Data
Deciphered Date 2017/08/24 Title
Compal Electronics, Inc.
P004 - Power MAP
Si ze Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Dat e: Friday, November 22, 2019 Sheet 4 of 100

5 4 3 2 1
5 4 3 2 1
G3->S5 [Battery only, AC absent]

[RTC in] +RTCV CC
tPCH01 < 9ms
PCH_RTCRST#
+TBT_V BUS1
Type-C
[AC in] +TBT_V BUS2
Ta
+3V_PDLDO_P
+PBATT
Tb
+3V _PDLDO_OUT Tm
B+
Tc
TI GPIO EN_PD_HV _1 Ti
+3V _PDLDO_OUT
Ti
EC Output DCIN1_EN
Td
+CHG_VIN_20V 1ns < Tj < 4s
EC Input ACAV_IN
Te
B+ Tk
EC Input POWER_SW_IN#
Tf
EC Input ACAV_IN Te
+3VALW
Tg
EC Output ALWON Tf
D
+5VALW D
Th
+3VALWP Tg
1ns < Tj < 4s
+5VALWP Th
+5VALW/+3VALW tPCH04_Min : 9 ms
+5VD/+3VD
RTC Standup EC_Output RTCRST#SRTCRST#

tPCH05_Min : 10 ms
VCCDSW_EN
tPCH02_Min : 1 us
DSW_PWROK
BATLOW#
tPCH32_Min : 95 ms
PCH_Output SLP_SUS#
PCH_Output EXT_PWR_GATE#
PCH_Output SIO_SLP_S0#
PCH_Output CPU_C10_GATE#
+3V_PCH VCCPRIM_3P3
+1.8V_PCH VCCPRIM_1P8
G3 to S5
+VCCPRIM_CORE VCCPRIM_CORE_1P05
+1.0V _MPHY GT VCCPRIM_GATED_1P05
+1V_PCH_PRIM VCCPRIM_1P05
EC Output PCH_RSMRST# tPCH32 : DSW_PWROK high to RSMRST# high
EC Output ESPI_RESET#
PCH_Output SUSWARN#
tPCH02_Min : 10 ms
PCH_Output SUSCLK tPCH32_Min : 105 ms
EC Output AC_PRESENT
EC Output SUSACK
C
PCH_Output SIO_SLP_A# C
PCH_Output CL_RST# (Vpro and nVpro different)
PCH_Output SLP_WLAN
EC Output SUS_ON_EC
SUS_ON_EC_P (UZ22)
+2.5V_MEM(VPP PU800)
SUS_ON_EC_ST (UZ15)
VCCST/+1.0V_VCCSFR
+1.2V_VDDQ (UZ16)
EC Output RUN_ON_EC
T = 40msec
RUN_ON_P (UZ20)
tCPU12 Min : 1 ms
tCPU03 Max : 25 ms
VCCSTG/+1.2V_VCCPLL_OC (UZ9)
+VCCIO(+0.95V , PU800)
tCPU10 Min : 1 ms
T <=10msec
+5VS/+3VS(UZ2/UZ23)
T = 20msec
EC Iutput
RUNPWROK (ALL_SYS_PWRGD)
EC Output tCPU01_Min : 1 ms
H_VCCST_PWRGD_P (UZ19)
tCPU00_Min : 1 ms
EC Output
IMVP_VR_ON_EC(UZ11)
B
tCPU19 Max : 100 ns B
tCPU05 Min : 100 ns
CPU Output DDR_VTT_CTRL (SM_PG_CTRL) UC6 VDDQ ramping and stable before VCCSA/
VCCIO ramps tCPU18 Max : 35 us
+0.6VS_VTT
tCPU09 Min : 1 ms
tCPU06 Min : 100 ns
+VCCSA
IMVP_VR_PG
tPLT04 Min : 1 ms
PCH Iutput PCH_PWROK (UH7)
PROCPWRGD (H_CPUPWRGD)
T = 100msec
SYS_PWROK (RESET_OUT#)
PCH_PLTRST#
+VCC_CORE
+V CCGT
DDR_DRAMRST#
A A

Issued Date 2019/11/30
Compal Secret Data
Deciphered Date 2018/12/31 Title
P005-Power Sequence
Si ze Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 0.4(X03)
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5 4 3 2 1
5 4 3 2 1
CFL-H
UH1C
PEG_CRX_GTX_P15 E25 B25 PEG_CTX_GRX_P15 @ CH5 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_P15
PEG_CRX_GTX_N15 D25 PEG_RXP_0 PEG_TXP_0 A25 PEG_CTX_GRX_N15 @ CH6 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N15
PEG_CTX_C_GRX_P[0..15] PEG_RXN_0 PEG_TXN_0
<27> PEG_CTX_C_GRX_P[0..15] PEG_CRX_GTX_P14 PEG_CTX_GRX_P14 PEG_CTX_C_GRX_P14
E24 B24 @ CH7 1 2 0.22U_0201_6.3V6M
PEG_CTX_C_GRX_N[0..15] PEG_CRX_GTX_N14 F24 PEG_RXP_1 PEG_TXP_1 C24 PEG_CTX_GRX_N14 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N14
<27> PEG_CTX_C_GRX_N[0..15] @ CH8
PEG_RXN_1 PEG_TXN_1
PEG_CRX_GTX_P[0..15] PEG_CRX_GTX_P13 E23 B23 PEG_CTX_GRX_P13 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_P13
<27> PEG_CRX_GTX_P[0..15] @ CH9
PEG_CRX_GTX_N[0..15] PEG_RXN_2 PEG_TXN_2
<27> PEG_CRX_GTX_N[0..15] PEG_CRX_GTX_P12 PEG_CTX_GRX_P12 PEG_CTX_C_GRX_P12
E22 B22 @ CH11 1 2 0.22U_0201_6.3V6M
PEG_CRX_GTX_N12 F22 PEG_RXP_3 PEG_TXP_3 C22 PEG_CTX_GRX_N12 @ CH12 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N12
PEG_RXN_3 PEG_TXN_3
D PEG_CRX_GTX_N11 D21 PEG_RXP_4 PEG_TXP_4 A21 PEG_CTX_GRX_N11 @ CH14 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N11 D
PEG_RXN_4 PEG_TXN_4
PEG_RXN_5 PEG_TXN_5
PEG_RXN_6 PEG_TXN_6
PEG_RXN_7 PEG_TXN_7
PEG_CRX_GTX_P7 D17 A17 PEG_CTX_GRX_P7 DIS@ CH21 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_P7
PEG_CRX_GTX_N7 E17 PEG_RXP_8 PEG_TXP_8 B17 PEG_CTX_GRX_N7 DIS@ CH22 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_N7
PEG_RXN_8 PEG_TXN_8
PEG_CRX_GTX_P6 F16 C16 PEG_CTX_GRX_P6 DIS@ CH23 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_P6
PEG_RXN_9 PEG_TXN_9
PEG_RXN_10 PEG_TXN_10
+VCCIO PEG_CRX_GTX_P0 F10 C10 PEG_CTX_GRX_P0 DIS@ CH35 1 2 0.22U_0201_6.3V6M PEG_CTX_C_GRX_P0
RH24 1 2 24.9_0201_1% PEG_RCOMP G2

PEG_RCOMP
C C
Trace Width/Space: 15 mil/ 15 mil
Max Trace Length: 600 mil
D8 B8
<16> DMI_CRX_PTX_P0 DMI_RXP_0 DMI_TXP_0 DMI_CTX_PRX_P0 <16>
<16> DMI_CRX_PTX_N0 E8 A8 DMI_CTX_PRX_N0 <16>
DMI_RXN_0 DMI_TXN_0
<16> DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1 <16>

F6 DMI_RXP_1 DMI_TXP_1 B6
<16> DMI_CRX_PTX_N1 DMI_RXN_1 DMI_TXN_1 DMI_CTX_PRX_N1 <16>
<16> DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2 <16>

E5 DMI_RXP_2 DMI_TXP_2 A5
J8 D4
<16> DMI_CRX_PTX_P3 DMI_RXP_3 3 OF 13 DMI_TXP_3 DMI_CTX_PRX_P3 <16>
J9 B4
CFL-H_BGA1440
@
CFL-H
UH1D
K36 D29
<42> CPU_DP1_P0 DDI1_TXP_0 EDP_TXP_0 EDP_TXP0 <38>
<42> CPU_DP1_N0 K37 E29 EDP_TXN0 <38>
B
J35 DDI1_TXN_0 EDP_TXN_0 F28 B
<42> CPU_DP1_P1 DDI1_TXP_1 EDP_TXP_1 EDP_TXP1 <38>
J34 E28
<42> CPU_DP1_N1 DDI1_TXN_1 EDP_TXN_1 EDP_TXN1 <38>
<42> CPU_DP1_P2 H37 A29 EDP_TXP2 <38>
H36 DDI1_TXP_2 EDP_TXP_2 B29
<42> CPU_DP1_P3 J37 C28 EDP_TXP3 <38>
J38 DDI1_TXP_3 EDP_TXP_3 B28
<42> CPU_DP1_AUXP D27 C26 EDP_AUXP <38>

E27 DDI1_AUXP EDP_AUXP B26
<42> CPU_DP1_AUXN DDI1_AUXN EDP_AUXN EDP_AUXN <38>
H34
<42> CPU_DP2_P0 DDI2_TXP_0 +VCCIO
H33
<42> CPU_DP2_N0 DDI2_TXN_0 EDP_DISP_UTIL
To Titan Ridge Port1 <42> CPU_DP2_P1 F37
G38 DDI2_TXP_1 EDP_DISP_UTIL
A33 RH456 1 @ 2 0_0201_5% BIA_PWM_PCH <13,38>
<42> CPU_DP2_N1 DDI2_TXN_1
<42> CPU_DP2_P2 F34
F35 DDI2_TXP_2 D37 EDP_COMP RH30 1 2 24.9_0402_1%
<42> CPU_DP2_N2 DDI2_TXN_2 DISP_RCOMP
E37
<42> CPU_DP2_P3 DDI2_TXP_3
<42> CPU_DP2_N3 E36 EDP_COMP
DDI2_TXN_3 CAD Note:Trace width=20 mils ,Spacing=25mil,
Max length=100 mils.
F26
<42> CPU_DP2_AUXP DDI2_AUXP
E26
<42> CPU_DP2_AUXN DDI2_AUXN
C34
<47> CPU_DP3_N0 D34
B36 DDI3_TXN_0
B34
<47> CPU_DP3_N1 DDI3_TXN_1
DP/USB3 Re-driver PS8802 <47> CPU_DP3_P2 F33
E33 DDI3_TXP_2
<47> CPU_DP3_N2
C33 DDI3_TXN_2 Close to CPU
B33
<47> CPU_DP3_N3 DDI3_TXN_3 G27
PROC_AUDIO_CLK AUD_AZA_CPU_SCLK <15>
<47> CPU_DP3_AUXP A27 G25 AUD_AZA_CPU_SDO <15>
B27 DDI3_AUXP PROC_AUDIO_SDI G29 AUD_AZA_CPU_SDI RH145 1 2 20_0402_5%
<47> CPU_DP3_AUXN DDI3_AUXN 4 ofPROC_AUDIO_SDO
13
AUD_AZA_CPU_SDI_R <15>
CFL-H_BGA1440
A @ A

P006-CPU(1/7) DMI,PEG,DDI,EDP
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C 0.4(X03)
5 4 3 2 1
5 4 3 2 1
Interleave
CFL-H
UH1A CFL-H
UH1B
DDR CHANNEL A DDR CHANNEL B
DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4 DDR4(IL)/LP3-DDR4(NIL) LP3/DDR4
DDR_A_D0 BR6 AG1 DDR_B_D0 BT11 AM9
DDR_A_D1 DDR0_DQ_0/DDR0_DQ_0 DDR0_CKP_0/DDR0_CKP_0 M_CLK_DDR0 <23> DDR_B_D1 DDR1_DQ_0/DDR0_DQ_16 DDR1_CKP_0/DDR1_CKP_0 M_CLK_DDR2 <24>
BT6 AG2 BR11 AN9
DDR_A_D2 DDR0_DQ_1/DDR0_DQ_1 DDR0_CKN_0/DDR0_CKN_0 M_CLK_DDR#0 <23> DDR_B_D6 DDR1_DQ_1/DDR0_DQ_17 DDR1_CKN_0/DDR1_CKN_0 M_CLK_DDR#2 <24>
<23> DDR_A_D[0..63] BP3 AK2 M_CLK_DDR1 <23> BT9 AM7 M_CLK_DDR3 <24>
DDR_A_D7 BR3 DDR0_DQ_2/DDR0_DQ_2 DDR0_CKP_1/DDR0_CKP_1 AK1 DDR_B_D2 BR8 DDR1_DQ_2/DDR0_DQ_18 DDR1_CKP_1/DDR1_CKP_1 AM8
<23> DDR_A_MA[0..13] DDR_A_D4 DDR0_DQ_3/DDR0_DQ_3 DDR0_CKN_1/DDR0_CKN_1 M_CLK_DDR#1 <23> DDR_B_D4 DDR1_DQ_3/DDR0_DQ_19 DDR1_CKN_1/DDR1_CKN_1 M_CLK_DDR#3 <24>
<23> DDR_A_DQS#[0..7] BN5 AL3 BP11 AM11
DDR_A_D5 BP6 DDR0_DQ_4/DDR0_DQ_4 NC/DDR0_CKP_2 AK3 DDR_B_D5 BN11 DDR1_DQ_4/DDR0_DQ_20 NC/DDR1_CKP_2 AM10
<23> DDR_A_DQS[0..7] DDR_A_D6 DDR0_DQ_5/DDR0_DQ_5 NC/DDR0_CKN_2 DDR_B_D3 DDR1_DQ_5/DDR0_DQ_21 NC/DDR1_CKN_2
BP2 AL2 BP8 AJ10
<23> DDR_A_CB[0..7] DDR_A_D3 DDR0_DQ_6/DDR0_DQ_6 NC/DDR0_CKP_3 DDR_B_D7 DDR1_DQ_6/DDR0_DQ_22 NC/DDR1_CKP_3
BN3 AL1 BN8 AJ11
DDR_A_D9 BL4 DDR0_DQ_7/DDR0_DQ_7 NC/DDR0_CKN_3 DDR_B_D12 BL12 DDR1_DQ_7/DDR0_DQ_23 NC/DDR1_CKN_3
DDR_A_D13 BL5 DDR0_DQ_8/DDR0_DQ_8 AT1 DDR_B_D8 BL11 DDR1_DQ_8/DDR0_DQ_24 AT8
D DDR_A_D10 DDR0_DQ_9/DDR0_DQ_9 DDR0_CKE_0/DDR0_CKE_0 DDR_CKE0_DIMMA <23> DDR_B_D9 DDR1_DQ_9/DDR0_DQ_25 DDR1_CKE_0/DDR1_CKE_0 DDR_CKE2_DIMMB <24> D
BL2 AT2 BL8 AT10
DDR_A_D11 DDR0_DQ_10/DDR0_DQ_10 DDR0_CKE_1/DDR0_CKE_1 DDR_CKE1_DIMMA <23> DDR_B_D10 DDR1_DQ_10/DDR0_DQ_26 DDR1_CKE_1/DDR1_CKE_1 DDR_CKE3_DIMMB <24>
BM1 AT3 BJ8 AT7
<24> DDR_B_D[0..63] DDR_A_D12 DDR0_DQ_11/DDR0_DQ_11 DDR0_CKE_2/DDR0_CKE_2 DDR_B_D14 DDR1_DQ_11/DDR0_DQ_27 DDR1_CKE_2/DDR1_CKE_2
<24> DDR_B_MA[0..13] BK4 AT5 BJ11 AT11
DDR_A_D8 BK5 DDR0_DQ_12/DDR0_DQ_12 DDR0_CKE_3/DDR0_CKE_3 DDR_B_D11 BJ10 DDR1_DQ_12/DDR0_DQ_28 DDR1_CKE_3/DDR1_CKE_3
<24> DDR_B_DQS#[0..7] DDR_A_D14 DDR0_DQ_13/DDR0_DQ_13 DDR_B_D13 DDR1_DQ_13/DDR0_DQ_29
<24> DDR_B_DQS[0..7] BK1 AD5 DDR_CS0_DIMMA# <23> BL7 AF11 DDR_CS2_DIMMB# <24>
DDR_A_D15 BK2 DDR0_DQ_14/DDR0_DQ_14 DDR0_CS#_0/DDR0_CS#_0 AE2 DDR_B_D15 BJ7 DDR1_DQ_14/DDR0_DQ_30 DDR1_CS#_0/DDR1_CS#_0 AE7
<24> DDR_B_CB[0..7] DDR_A_D20 DDR0_DQ_15/DDR0_DQ_15 DDR0_CS#_1/DDR0_CS#_1 DDR_CS1_DIMMA# <23> DDR_B_D16 DDR1_DQ_15/DDR0_DQ_31 DDR1_CS#_1/DDR1_CS#_1 DDR_CS3_DIMMB# <24>
BG4 AD2 BG11 AF10
DDR_A_D16 BG5 DDR0_DQ_16/DDR0_DQ_32 NC/DDR0_CS#_2 AE5 DDR_B_D17 BG10 DDR1_DQ_16/DDR0_DQ_48 NC/DDR1_CS#_2 AE10
DDR_A_D23 BF4 DDR0_DQ_17/DDR0_DQ_33 NC/DDR0_CS#_3 DDR_B_D21 BG8 DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_CS#_3
DDR_A_D19 BF5 DDR0_DQ_18/DDR0_DQ_34 AD3 DDR_B_D19 BF8 DDR1_DQ_18/DDR0_DQ_50 AF7
DDR_A_D21 DDR0_DQ_19/DDR0_DQ_35 DDR0_ODT_0/DDR0_ODT_0 M_ODT0 <23> DDR_B_D18 DDR1_DQ_19/DDR0_DQ_51 DDR1_ODT_0/DDR1_ODT_0 M_ODT2 <24>
BG2 AE4 BF11 AE8
DDR_A_D17 DDR0_DQ_20/DDR0_DQ_36 NC/DDR0_ODT_1 M_ODT1 <23> DDR_B_D22 DDR1_DQ_20/DDR0_DQ_52 NC/DDR1_ODT_1 M_ODT3 <24>
BG1 AE1 BF10 AE9
DDR_A_D22 BF1 DDR0_DQ_21/DDR0_DQ_37 NC/DDR0_ODT_2 AD4 DDR_B_D20 BG7 DDR1_DQ_21/DDR0_DQ_53 NC/DDR1_ODT_2 AE11
DDR_A_D18 BF2 DDR0_DQ_22/DDR0_DQ_38 NC/DDR0_ODT_3 DDR_B_D23 BF7 DDR1_DQ_22/DDR0_DQ_54 NC/DDR1_ODT_3
DDR_A_D24 BD2 DDR0_DQ_23/DDR0_DQ_39 AH5 DDR_B_D26 BB11 DDR1_DQ_23/DDR0_DQ_55 AH10
DDR_A_D25 DDR0_DQ_24/DDR0_DQ_40 DDR0_CAB_4/DDR0_BA_0 DDR_A_BS0 <23> DDR_B_D24 DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_3/DDR1_MA_16 DDR_B_RAS# <24>
BD1 AH1 BC11 AH11
DDR_A_D26 DDR0_DQ_25/DDR0_DQ_41 DDR0_CAB_6/DDR0_BA_1 DDR_A_BS1 <23> DDR_B_D31 DDR1_DQ_25/DDR0_DQ_57 DDR1_CAB_2/DDR1_MA_14 DDR_B_WE# <24>
BC4 AU1 BB8 AF8
DDR_A_D27 DDR0_DQ_26/DDR0_DQ_42 DDR0_CAA_5/DDR0_BG_0 DDR_A_BG0 <23> DDR_B_D25 DDR1_DQ_26/DDR0_DQ_58 DDR1_CAB_1/DDR1_MA_15 DDR_B_CAS# <24>
BC5 BC8
DDR_A_D28 BD5 DDR0_DQ_27/DDR0_DQ_43 AH4 DDR_B_D28 BC10 DDR1_DQ_27/DDR0_DQ_59 AH8
DDR_A_D29 DDR0_DQ_28/DDR0_DQ_44 DDR0_CAB_3/DDR0_MA_16 DDR_A_RAS# <23> DDR_B_D30 DDR1_DQ_28/DDR0_DQ_60 DDR1_CAB_4/DDR1_BA_0 DDR_B_BS0 <24>
BD4 AG4 DDR_A_WE# <23> BB10 AH9 DDR_B_BS1 <24>
DDR_A_D30 BC1 DDR0_DQ_29/DDR0_DQ_45 DDR0_CAB_2/DDR0_MA_14 AD1 DDR_B_D29 BC7 DDR1_DQ_29/DDR0_DQ_61 DDR1_CAB_6/DDR1_BA_1 AR9
DDR_A_D31 DDR0_DQ_30/DDR0_DQ_46 DDR0_CAB_1/DDR0_MA_15 DDR_A_CAS# <23> DDR_B_D27 DDR1_DQ_30/DDR0_DQ_62 DDR1_CAA_5/DDR1_BG_0 DDR_B_BG0 <24>
BC2 BB7
DDR_A_D32 AB1 DDR0_DQ_31/DDR0_DQ_47 AH3 DDR_A_MA0 DDR_B_D34 AA11 DDR1_DQ_31/DDR0_DQ_63 AJ9 DDR_B_MA0
DDR_A_D33 AB2 DDR0_DQ_32/DDR1_DQ_0 DDR0_CAB_9/DDR0_MA_0 AP4 DDR_A_MA1 DDR_B_D38 AA10 DDR1_DQ_32/DDR1_DQ_16 DDR1_CAB_9/DDR1_MA_0 AK6 DDR_B_MA1
DDR_A_D34 AA4 DDR0_DQ_33/DDR1_DQ_1 DDR0_CAB_8/DDR0_MA_1 AN4 DDR_A_MA2 DDR_B_D32 AC11 DDR1_DQ_33/DDR1_DQ_17 DDR1_CAB_8/DDR1_MA_1 AK5 DDR_B_MA2
DDR_A_D35 AA5 DDR0_DQ_34/DDR1_DQ_2 DDR0_CAB_5/DDR0_MA_2 AP5 DDR_A_MA3 DDR_B_D36 AC10 DDR1_DQ_34/DDR1_DQ_18 DDR1_CAB_5/DDR1_MA_2 AL5 DDR_B_MA3
DDR_A_D36 AB5 DDR0_DQ_35/DDR1_DQ_3 NC/DDR0_MA_3 AP2 DDR_A_MA4 DDR_B_D35 AA7 DDR1_DQ_35/DDR1_DQ_19 NC/DDR1_MA_3 AL6 DDR_B_MA4
DDR_A_D37 AB4 DDR0_DQ_36/DDR1_DQ_4 NC/DDR0_MA_4 AP1 DDR_A_MA5 DDR_B_D39 AA8 DDR1_DQ_36/DDR1_DQ_20 NC/DDR1_MA_4 AM6 DDR_B_MA5
DDR_A_D38 AA2 DDR0_DQ_37/DDR1_DQ_5 DDR0_CAA_0/DDR0_MA_5 AP3 DDR_A_MA6 DDR_B_D37 AC8 DDR1_DQ_37/DDR1_DQ_21 DDR1_CAA_0/DDR1_MA_5 AN7 DDR_B_MA6
DDR_A_D39 AA1 DDR0_DQ_38/DDR1_DQ_6 DDR0_CAA_2/DDR0_MA_6 AN1 DDR_A_MA7 DDR_B_D33 AC7 DDR1_DQ_38/DDR1_DQ_22 DDR1_CAA_2/DDR1_MA_6 AN10 DDR_B_MA7
DDR_A_D44 V5 DDR0_DQ_39/DDR1_DQ_7 DDR0_CAA_4/DDR0_MA_7 AN3 DDR_A_MA8 DDR1_DQ_39/DDR1_DQ_23 DDR1_CAA_4/DDR1_MA_7
DDR_A_D45 V2 DDR0_DQ_40/DDR1_DQ_8 DDR0_CAA_3/DDR0_MA_8 AT4 DDR_A_MA9 DDR_B_D40 W8 DDR4(IL)/LP3-DDR4(NIL) AN8 DDR_B_MA8
DDR_A_D43 U1 DDR0_DQ_41/DDR1_DQ_9 DDR0_CAA_1/DDR0_MA_9 AH2 DDR_A_MA10 DDR_B_D41 W7 DDR1_DQ_40/DDR1_DQ_24 DDR1_CAA_3/DDR1_MA_8 AR11 DDR_B_MA9
DDR_A_D47 U2 DDR0_DQ_42/DDR1_DQ_10 DDR0_CAB_7/DDR0_MA_10 AN2 DDR_A_MA11 DDR_B_D42 V10 DDR1_DQ_41/DDR1_DQ_25 DDR1_CAA_1/DDR1_MA_9 AH7 DDR_B_MA10
DDR_A_D41 V1 DDR0_DQ_43/DDR1_DQ_11 DDR0_CAA_7/DDR0_MA_11 AU4 DDR_A_MA12 DDR_B_D43 V11 DDR1_DQ_42/DDR1_DQ_26 DDR1_CAB_7/DDR1_MA_10 AN11 DDR_B_MA11
DDR_A_D40 V4 DDR0_DQ_44/DDR1_DQ_12 DDR0_CAA_6/DDR0_MA_12 AE3 DDR_A_MA13 DDR_B_D44 W11 DDR1_DQ_43/DDR1_DQ_27 DDR1_CAA_7/DDR1_MA_11 AR10 DDR_B_MA12
DDR_A_D42 U5 DDR0_DQ_45/DDR1_DQ_13 DDR0_CAB_0/DDR0_MA_13 AU2 DDR_B_D45 W10 DDR1_DQ_44/DDR1_DQ_28 DDR1_CAA_6/DDR1_MA_12 AF9 DDR_B_MA13
DDR_A_D46 DDR0_DQ_46/DDR1_DQ_14 DDR0_CAA_9/DDR0_BG_1 DDR_A_BG1 <23> DDR_B_D47 DDR1_DQ_45/DDR1_DQ_29 DDR1_CAB_0/DDR1_MA_13
C U4 AU3 DDR_A_ACT# <23> V7 AR7 DDR_B_BG1 <24> C
DDR_A_D53 R2 DDR0_DQ_47/DDR1_DQ_15 DDR0_CAA_8/DDR0_ACT# DDR_B_D46 V8 DDR1_DQ_46/DDR1_DQ_30 DDR1_CAA_9/DDR1_BG_1 AT9
DDR_A_D51 DDR0_DQ_48/DDR1_DQ_32 DDR_B_D48 DDR1_DQ_47/DDR1_DQ_31 DDR1_CAA_8/DDR1_ACT# DDR_B_ACT# <24>
P5 AG3 DDR_A_PAR <23> R11
DDR_A_D49 R4 DDR0_DQ_49/DDR1_DQ_33 NC/DDR0_PAR AU5 DDR_B_D51 P11 DDR1_DQ_48/DDR1_DQ_48 AJ7
DDR_A_D55 DDR0_DQ_50/DDR1_DQ_34 NC/DDR0_ALERT# DDR_A_ALERT# <23> DDR_B_D50 DDR1_DQ_49/DDR1_DQ_49 NC/DDR1_PAR DDR_B_PAR <24>
P4 P7 AR8
DDR_A_D52 DDR0_DQ_51/DDR1_DQ_35 DDR_B_D52 DDR1_DQ_50/DDR1_DQ_50 NC/DDR1_ALERT# DDR_B_ALERT# <24>
R5 DDR4(IL)/LP3-DDR4(NIL) R8
DDR_A_D54 P2 DDR0_DQ_52/DDR1_DQ_36 BR5 DDR_A_DQS#0 DDR_B_D53 R10 DDR1_DQ_51/DDR1_DQ_51 DDR4(IL)/LP3-DDR4(NIL)
DDR_A_D48 R1 DDR0_DQ_53/DDR1_DQ_37DDR0_DQSN_0/DDR0_DQSN_0 BL3 DDR_A_DQS#1 DDR_B_D55 P10 DDR1_DQ_52/DDR1_DQ_52 BN9 DDR_B_DQS#0
DDR_A_D50 P1 DDR0_DQ_54/DDR1_DQ_38DDR0_DQSN_1/DDR0_DQSN_1 BG3 DDR_A_DQS#2 DDR_B_D49 R7 DDR1_DQ_53/DDR1_DQ_53DDR1_DQSN_0/DDR0_DQSN_2 BL9 DDR_B_DQS#1
DDR_A_D56 M4 DDR0_DQ_55/DDR1_DQ_39DDR0_DQSN_2/DDR0_DQSN_4 BD3 DDR_A_DQS#3 DDR_B_D54 P8 DDR1_DQ_54/DDR1_DQ_54DDR1_DQSN_1/DDR0_DQSN_3 BG9 DDR_B_DQS#2
DDR_A_D57 M1 DDR0_DQ_56/DDR1_DQ_40DDR0_DQSN_3/DDR0_DQSN_5 AA3 DDR_A_DQS#4 DDR_B_D58 L11 DDR1_DQ_55/DDR1_DQ_55DDR1_DQSN_2/DDR0_DQSN_6 BC9 DDR_B_DQS#3
DDR_A_D58 L4 DDR0_DQ_57/DDR1_DQ_41DDR0_DQSN_4/DDR1_DQSN_0 U3 DDR_A_DQS#5 DDR_B_D57 M11 DDR1_DQ_56/DDR1_DQ_56DDR1_DQSN_3/DDR0_DQSN_7 AC9 DDR_B_DQS#4
DDR_A_D63 L2 DDR0_DQ_58/DDR1_DQ_42DDR0_DQSN_5/DDR1_DQSN_1 P3 DDR_A_DQS#6 DDR_B_D59 L7 DDR1_DQ_57/DDR1_DQ_57DDR1_DQSN_4/DDR1_DQSN_2 W9 DDR_B_DQS#5
DDR_A_D60 M5 DDR0_DQ_59/DDR1_DQ_43DDR0_DQSN_6/DDR1_DQSN_4 L3 DDR_A_DQS#7 DDR_B_D61 M8 DDR1_DQ_58/DDR1_DQ_58DDR1_DQSN_5/DDR1_DQSN_3 R9 DDR_B_DQS#6
DDR_A_D61 M2 DDR0_DQ_60/DDR1_DQ_44DDR0_DQSN_7/DDR1_DQSN_5 DDR_B_D62 L10 DDR1_DQ_59/DDR1_DQ_59DDR1_DQSN_6/DDR1_DQSN_6 M9 DDR_B_DQS#7
DDR_A_D62 L5 DDR0_DQ_61/DDR1_DQ_45 BP5 DDR_A_DQS0 DDR_B_D60 M10 DDR1_DQ_60/DDR1_DQ_60DDR1_DQSN_7/DDR1_DQSN_7
DDR_A_D59 L1 DDR0_DQ_62/DDR1_DQ_46 DDR0_DQSP_0/DDR0_DQSP_0 BK3 DDR_A_DQS1 DDR_B_D56 M7 DDR1_DQ_61/DDR1_DQ_61 BP9 DDR_B_DQS0
DDR0_DQ_63/DDR1_DQ_47 DDR0_DQSP_1/DDR0_DQSP_1 BF3 DDR_A_DQS2 DDR_B_D63 L8 DDR1_DQ_62/DDR1_DQ_62 DDR1_DQSP_0/DDR0_DQSP_2 BJ9 DDR_B_DQS1
LP3/DDR4 DDR0_DQSP_2/DDR0_DQSP_4 BC3 DDR_A_DQS3 DDR1_DQ_63/DDR1_DQ_63 DDR1_DQSP_1/DDR0_DQSP_3 BF9 DDR_B_DQS2
DDR_A_CB0 BA2 DDR0_DQSP_3/DDR0_DQSP_5 AB3 DDR_A_DQS4 DDR_B_CB0 AW11 LP3/DDR4 DDR1_DQSP_2/DDR0_DQSP_6 BB9 DDR_B_DQS3
DDR_A_CB1 BA1 NC/DDR0_ECC_0 DDR0_DQSP_4/DDR1_DQSP_0 V3 DDR_A_DQS5 DDR_B_CB1 AY11 NC/DDR1_ECC_0 DDR1_DQSP_3/DDR0_DQSP_7 AA9 DDR_B_DQS4
DDR_A_CB2 AY4 NC/DDR0_ECC_1 DDR0_DQSP_5/DDR1_DQSP_1 R3 DDR_A_DQS6 DDR_B_CB2 AY8 NC/DDR1_ECC_1 DDR1_DQSP_4/DDR1_DQSP_2 V9 DDR_B_DQS5
DDR_A_CB3 AY5 NC/DDR0_ECC_2 DDR0_DQSP_6/DDR1_DQSP_4 M3 DDR_A_DQS7 DDR_B_CB3 AW8 NC/DDR1_ECC_2 DDR1_DQSP_5/DDR1_DQSP_3 P9 DDR_B_DQS6
DDR_A_CB4 BA5 NC/DDR0_ECC_3 DDR0_DQSP_7/DDR1_DQSP_5 DDR_B_CB4 AY10 NC/DDR1_ECC_3 DDR1_DQSP_6/DDR1_DQSP_6 L9 DDR_B_DQS7
DDR_A_CB5 BA4 NC/DDR0_ECC_4 AY3 DDR_A_DQS8 DDR_B_CB5 AW10 NC/DDR1_ECC_4 DDR1_DQSP_7/DDR1_DQSP_7
DDR_A_CB6 NC/DDR0_ECC_5 DDR0_DQSP_8/DDR0_DQSP_8 DDR_A_DQS#8 DDR_A_DQS8 <23> DDR_B_CB6 NC/DDR1_ECC_5 DDR_B_DQS8
AY1 BA3 AY7 AW9 For ECC DIMM
DDR_A_CB7 AY2 NC/DDR0_ECC_6 1 OFDDR0_DQSN_8/DDR0_DQSN_8
13 DDR_A_DQS#8 <23> DDR_B_CB7 AW7 NC/DDR1_ECC_6 DDR1_DQSP_8/DDR1_DQSP_8 AY9 DDR_B_DQS#8 DDR_B_DQS8 <24>
For ECC DIMM NC/DDR0_ECC_7 For ECC DIMM NC/DDR1_ECC_7 DDR1_DQSN_8/DDR1_DQSN_8 DDR_B_DQS#8 <24>
For ECC DIMM
CFL-H_BGA1440
@
ECC Byte swapping (with othe Bytes) is not allowed.

ECC bits swap is allowed RH148 1 2 121_0201_1% DDR_RCOMP0 G1 BN13 +V_DDR_REFA_R
RH149 1 2 75_0201_1% DDR_RCOMP1 H1 DDR_RCOMP_0 DDR_VREF_CA BP13
DDR_RCOMP_1 DDR0_VREF_DQ +0.6V_A_VREFDQ
RH150 1 2 100_0201_1% DDR_RCOMP2 J2 2 OF 13 BR13
DDR_RCOMP_2 DDR1_VREF_DQ +V_DDR_REFB_R
Trace Width/Space: 15 mil/ 25 mil CFL-H_BGA1440
Max Trace Length: 500 mil
B
@ B
A A
Security Classification Compal Secret Data

P007-CPU(2/7) DDR4
5 4 3 2 1
5 4 3 2 1
CFG Straps for Processor

+VCCST
CFL-H
Stall reset sequence after PCU PLL lock until de-asserted 1 2 H_THERMTRIP#_R UH1E
RH163 1K_0201_5%
XDP_PREQ#
1 = (Default) Normal Operation; No stall. 1 2 B31 BN25
*
@ <14> PCH_CPU_BCLK_P CFG0 CFG0 <79>
BCLKP CFG_0
CFG0 RH156 51_0201_5% <14> PCH_CPU_BCLK_N A32
BCLKN CFG_1
BN27 CFG1 CFG1 <79>
BN26 CFG2
H_VCCST_PWRGD CFG_2 CFG2 <79>
1 2 <14> PCH_CPU_PCIBCLK_P D35 BN28 CFG3 CFG3 <79>
D PCI_BCLKP CFG_3 D
0 = Stall. RH164 1K_0201_5% <14> PCH_CPU_PCIBCLK_N
C36
PCI_BCLKN CFG_4
BR20 CFG4 CFG4 <79>
BM20 CFG5
SVID_DAT_PWR_CPU CFG_5 CFG5 <79>
1 2 <14> CPU_24MHZ_P E31 BT20 CFG6 CFG6 <79>
RH151 100_0402_5% D31 CLK24P CFG_6 BP20 CFG7
<14> CPU_24MHZ_N CLK24N CFG_7 CFG7 <79>
CFG0 1 @ 2 BR23 CFG8 CFG8 <79>
RH183 1K_0201_5% 1 2 SVID_ALERT#_PWR_CPU CFG_8 BR22 CFG9
CFG_9 CFG9 <79>
RH152 56.2_0402_1% BT23 CFG10
CFG_10 CFG10 <79>
BT22 CFG11 CFG11 <79>
1 @ 2 H_CATERR# CFG_11 BM19 CFG12
CFG_12 CFG12 <79>
RH570 49.9_0201_1% BR19 CFG13 CFG13 <79>
CFG_13 BP19 CFG14
SVID_ALERT#_PWR_CPU CFG_14 CFG14 <79>
RH153 1 2 220_0402_5% VR_SVID_ALERT#_R BH31 BT19 CFG15
<88> SVID_ALERT#_PWR_CPU VIDALERT# CFG_15 CFG15 <79>
<88> SVID_CLK_PWR_CPU BH32
SVID_DAT_PWR_CPU BH29 VIDSCK BN23 CFG17
<88> SVID_DAT_PWR_CPU H_PROCHOT# VIDSOUT CFG_17 CFG17 <79>
<58,82,85,88> H_PROCHOT# RH158 1 2 499_0201_1% H_PROCHOT#_R BR30 BP23 CFG16 CFG16 <79>
+VCCSTG PROCHOT# CFG_16 BP22
Display Port Presence Strap DDR_VTT_PG_CTRL CFG_19
CFG19 CFG19 <79>
BT13 BN22 CFG18
DDR_VTT_CNTL CFG_18 CFG18 <79>
1 : Disabled; No Physical Display Port

CFG4 attached to Embedded Display Port H_PROCHOT# BPM#_0
BR27 XDP_BPM#0 <79>
1 2 BT27
BPM#_1 CPU_BPM#2 XDP_BPM#1 <79>
RH165 1K_0201_5% BM31 T4971 PAD~D TP@
H_VCCST_PWRGD VCCST_PWRGD_CPU BPM#_2 CPU_BPM#3
0 : Enabled; An external Display Port device is
* <78,79> H_VCCST_PWRGD 1 2 H13 BT30 T4972 PAD~D TP@
RH154 60.4_0402_1% VCCST_PWRGD BPM#_3
connected to the Embedded Display Port BT31
<15> H_CPUPWRGD PLTRST_CPU# PROCPWRGD CPU_XDP_TDO
BP35 BT28
<13,79> PLTRST_CPU# H_PM_SYNC_R RESET# PROC_TDO CPU_XDP_TDI CPU_XDP_TDO <79>
BM34 BL32
<13> H_PM_SYNC_R H_PM_DOWN H_PM_DOWN_R PM_SYNC PROC_TDI CPU_XDP_TMS CPU_XDP_TDI <79>
<13> H_PM_DOWN RH155 1 2 20_0402_5% BP31 BP28 CPU_XDP_TMS <79>
CFG4 1 2 RH190 1 2 0_0201_5% H_PECI_R BT34 PM_DOWN PROC_TMS BR28 CPU_XDP_TCK
<13,58> H_PECI H_THERMTRIP#_R PECI PROC_TCK CPU_XDP_TCK <79>
RH185 1K_0201_5% <13,58> H_THERMTRIP#_R J31
THERMTRIP# BP30 CPU_XDP_TRST#
PROC_DETECT#_R PROC_TRST# XDP_PREQ# CPU_XDP_TRST# <19,79>
RH519 1 @ 2 0_0201_5% BR33 BL30
<13> PROC_DETECT# SKTOCC# PROC_PREQ# XDP_PRDY# XDP_PREQ# <19,79>
BN1 BP27 XDP_PRDY# <19,79>
RH1958 1 2 0_0201_5% PROC_SELECT# PROC_PRDY#
H_CATERR# BM30
CATERR# BT25 CFG_RCOMP
TP@PAD~D T4969 CEZVM# AT13 CFG_RCOMP
TP@PAD~D T4970 CEMSM# AW13 ZVM#
C C
MSM#
1
PCIE Port Bifurcation Straps
TP@PAD~D T4967 CERSVD1 AU13 RH59
TP@PAD~D T4968 CERSVD2 AY13 RSVD1 49.9_0201_1%
RSVD2
11: (Default) x16 - Device 1 functions 1 and 2 disabled
*10:
5 OF 13
2
CFG[6:5] x8, x8 - Device 1 function 1 enabled ; function 2
CFL-H_BGA1440
disabled
@
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled H_PECI_R
RH230 1 2 0_0201_5% DDR_VTT_PG_CTRL
<85> SM_PG_CTRL
1
CFG2 1 2
RH184 1K_0201_5%
CFG2 PEG LANE REVERSAL 1
@
RH200
300_0201_1%
NORMAL:1 @ CH230
0.1U_0402_10V7K
LANE REVERSER :0
2
2
CFG5 1 2
RH186 1K_0201_5%
CFL-H
CFG6 1 @ 2 UH1M
RH187 1K_0201_5%
— 00 = 1 x8, 2 x4 PCI Express*
— 01 = reserved Impedance Spectrum Tool Trigger TP@PAD~D T39 CMRSVD_TP5
IST_TRIG_T
E2
RSVD_TP5
TP@PAD~D T40 E3
— 10 = 2 x8 PCI Express* TP@PAD~D T41 CMRSVD_TP4 E1 IST_TRIG
CMRSVD_TP3 RSVD_TP4
— 11 = 1 x16 PCI Express* TP@PAD~D T42 D1
RSVD_TP3
TP@PAD~D T43 CMRSVD_TP1 BR1 BK28 CMRSVD11 T66 PAD~D TP@
CMRSVD_TP2 BT2 RSVD_TP1 RSVD11 BJ28
PEG DEFER TRAINING TP@PAD~D T44
RSVD_TP2 RSVD10
CMRSVD10 T67 PAD~D TP@
TP@PAD~D T45 CMRSVD15 BN35

RSVD15
1: (Default) PEG Train immediately following xxRESETB
B
CFG7 * de assertion TP@PAD~D
TP@PAD~D
T46
T47
CMRSVD28
CMRSVD27
J24
H24 RSVD28
RSVD27
B
TP@PAD~D T48 CMRSVD14 BN33

RSVD14
0: PEG Wait for BIOS for training TP@PAD~D T49 CMRSVD13 BL34
RSVD13
TP@PAD~D T50 CMRSVD30 N29
TP@PAD~D T51 CMRSVD31 R14 RSVD30
CFG7 1 @ 2 TP@PAD~D T52 CMRSVD2 AE29 RSVD31
RH188 1K_0201_5% TP@PAD~D T53 CMRSVD1 AA14 RSVD2
TP@PAD~D T4966 CMRSVD5 AP29 RSVD1
TP@PAD~D T4965 CMRSVD4 AP14 RSVD5
A36 RSVD4
VSS_A36
A37
VSS_A37
PCH_TRIGGER RH167 1 2 30_0402_5% PCH_TRIGGER_R H23
<19> PCH_TRIGGER CPU_TRIGGER CPU_TRIGGER_R PROC_TRIGIN
<19> CPU_TRIGGER RH192 1 2 30_0402_5% J23
PROC_TRIGOUT
TP@PAD~D T57 CMRSVD24 F30
RSVD24
TP@PAD~D T58 CMRSVD23 E30

RSVD23
TP@PAD~D T59 CMRSVD7 B30 BL31 CMRSVD12 T82 PAD~D TP@

TP@PAD~D T60 CMRSVD21 C30 RSVD7 RSVD12 AJ8 CMRSVD3 T83 PAD~D TP@
RSVD21 RSVD3 G13 CMRSVD25 T84 PAD~D TP@
RSVD25
TP@PAD~D T61 CMRSVD26 G3
TP@PAD~D T62 CMRSVD29 J3 RSVD26 C38 CMRSVD22 T85 PAD~D TP@
RSVD29 RSVD22 C1 CMRSVD20 T86 PAD~D TP@
RSVD20 BR2 CMRSVD17 T87 PAD~D TP@
TP@PAD~D T63 CMRSVD19 BR35 RSVD17 BP1 CMRSVD16 T88 PAD~D TP@
TP@PAD~D T64 CMRSVD18 BR31 RSVD19 RSVD16 B38 CMRSVD8 T89 PAD~D TP@
TP@PAD~D T65 CMRSVD9 BH30 RSVD18 RSVD8 B2 CMRSVD6 T90 PAD~D TP@
RSVD9 RSVD6
13 OF 13
A A
CFL-H_BGA1440
@

P008-CPU(3/7) RSVD,CFG,XDP
5 4 3 2 1
5 4 3 2 1
+VCC_CORE +VCC_CORE +VCC_CORE +VCC_CORE
96000mA(Hexa Core GT2)

D D
CFL-H
CFL-H UH1J
UH1I
AA13 AH13 K14 W35
AA31 VCC1 VCC64 AH14 L13 VCC1 VCC64 W36
AA32 VCC2 VCC65 AH29 L14 VCC2 VCC65 W37
AA33 VCC3 VCC66 AH30 N13 VCC3 VCC66 W38
AA34 VCC4 VCC67 AH31 N14 VCC4 VCC67 Y29
AA35 VCC5 VCC68 AH32 N30 VCC5 VCC68 Y30
AA36 VCC6 VCC69 AJ14 N31 VCC6 VCC69 Y31
AB29 VCC9 VCC72 AJ31 N36 VCC9 VCC72 Y34
AB32 VCC12 VCC75 AJ34 P13 VCC12 VCC75
AB35 VCC13 VCC76 AJ35 P14 VCC13
AB36 VCC14 VCC77 AJ36 P29 VCC14
AB37 VCC15 VCC78 AK31 P30 VCC15
AB38 VCC16 VCC79 AK32 P31 VCC16
AC13 VCC17 VCC80 AK33 P32 VCC17
AC32 VCC22 VCC85 AK38 R13 VCC22
AC33 VCC23 VCC86 AL13 R31 VCC23
C
AD13 VCC27 VCC90 AL32 R35 VCC27 C
AD14 VCC28 VCC91 AL35 R36 VCC28
AD33 VCC31 VCC94 AL38 T29 VCC31
AD34 VCC32 VCC95 AM13 T30 VCC32
AE13 VCC37 VCC100 AM32 T37 VCC37
AE14 VCC38 VCC101 AM33 T38 VCC38
AE30 VCC39 VCC102 AM34 U29 VCC39
AE35 VCC42 VCC105 AN13 U32 VCC42
AF29 VCC46 VCC109 AN33 U36 VCC46
AF30 VCC47 VCC110 AN34 V13 VCC47
AF35 VCC52 VCC115 AP13 V34 VCC52
AG14 VCC56 VCC119 AP35 +VCC_CORE V38 VCC56
AG31 VCC57 VCC120 AP36 W13 VCC57
VCC60 VCC123 VCC60
1
AG34 K13 W30

AG35 VCC61 VCC124 RH197 W31 VCC61
B B
AG36 VCC62 W32 VCC62 10 OF 13
VCC63 100_0402_1% VCC63
CFL-H_BGA1440
2
AG37 VCC_SENSE_R RH198 1 2 0_0402_5% @

VCC_SENSE VSS_SENSE_R VCC_SENSE_IA <88>
9 OF 13 AG38 RH465 1 2 0_0402_5% VSS_SENSE_IA <88>
VSS_SENSE
CFL-H_BGA1440
1
@ RH466
100_0402_1%
2
1. Vcc_SENSE/ Vss_SENSE Trace Length Match < 25 mils

2. Maintain 25-mil separation distance away from any other dynamic signals.
3. RC10, RC11 should be placed within 2 inches (50.8 mm) of CPU
A A

P009-CPU(4/7) PWR,VCore,RSVD
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.4(X03)
5 4 3 2 1
5 4 3 2 1
570805_CFL_EDS_Vol1_Rev0.7
+1.2V_VDDQ_CPU
Max: 3300mA
570805_CFL_EDS_Vol1_Rev0.7
+VCC_SA +1.2V_DDR
Max: 11100mA +VDDQ_DDR 571483_CFL_H_RVP_CRB_TDK_Rev0p5
D D
+1.05VS_VCCSTG: 1uF * 1
PJP1604
+VCC_SA 1 2
Board Edge cap
PAD-OPEN 3x3m
JUMP@ +VCCSTG +VCCST
CFL-H +VCC_SA
UH1L
J30 AA6
K29 VCCSA1 VDDQ1 AE12
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
K30 VCCSA2 VDDQ2 AF5
22U_0603_6.3V6M
22U_0603_6.3V6M
VCCSA3 VDDQ3 1 1 1 1 1 1
K31 AF6
CH105
CH106
CH107
CH108
CH109
CH110
VCCSA4 VDDQ4 1 1
K32 AG5
CH134
CH135
K33 VCCSA5 VDDQ5 AG9
K34 VCCSA6 VDDQ6 AJ12 2 2 2 2 2 2
K35 VCCSA7 VDDQ7 AL11 2 2
L31 VCCSA8 VDDQ8 AP6
L32 VCCSA9 VDDQ9 AP7
L35 VCCSA10 VDDQ10 AR12
L36 VCCSA11 VDDQ11 AR6
L37 VCCSA12 VDDQ12 AT12
L38 VCCSA13 VDDQ13 AW6
M29 VCCSA14 VDDQ14 AY6
M30 VCCSA15 VDDQ15 J5
M31 VCCSA16 VDDQ16 J6 +VCC_SA +VCC_SA
M32 VCCSA17 VDDQ17 K12
570805_CFL_EDS_Vol1_Rev0.7 M33 VCCSA18 VDDQ18 K6
+VCC_IO M34 VCCSA19 VDDQ19 L12 570805_CFL_EDS_Vol1_Rev0.7 +1.2V_VCCPLL_OC +VCCST +VCCST
Max: 6400mA
M35 VCCSA20 VDDQ20 L6 +1.2V_VCCPLL_OC
M36 VCCSA21 VDDQ21 R6 Max: 130mA
C +VCCIO VCCSA22 VDDQ22 T6 C
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1U_0201_6.3V6M
VDDQ23 W6 +1.2V_VCCPLL_OC
1U_0201_6.3V6M
1U_0201_6.3V6M
VDDQ24 1 1 1 1 1 1 1 1
Y12
1U_0402_10V6K
CH3334
47U_0603-H1_2_6.3V6M
CH111
CH112
CH113
CH114
CH115
CH116
CH117
CH133
VDDQ25 1 1 1
1
AG12
CH3335
G15 VCCIO1 @
CH3332
CH3333
G17 VCCIO2 2 2 2 2 2 2 2 2
VCCIO3 2 2 2
2
G19 BH13
G21 VCCIO4 VCCPLL_OC1 BJ13
H15 VCCIO5 VCCPLL_OC2 G11 +VCCST
H16 VCCIO6 VCCPLL_OC3
H17 VCCIO7 H30 Max: 60mA
H19 VCCIO8 VCCST +VCCSTG
H20 VCCIO9 H29 Max: 20mA
H21 VCCIO10 VCCSTG2
H26 VCCIO11 G30
close CPU ball close CPU ball
H27 VCCIO12
VCCIO13
VCCSTG1 +VCCST H28,J28
J15 H28 Max: 150mA
J16 VCCIO14 VCCPLL1 J28
J17 VCCIO15 VCCPLL2
J19 VCCIO16 RH201 1 2 100_0402_1%
VCCIO17 VCCSA_SENSE_R +VCC_SA
J20 M38 RH202 1 2 0_0402_5% VCC_SENSE_SA <88>
J21 VCCIO18 VCCSA_SENSE M37 VSSSA_SENSE_R RH470 1 2 0_0402_5%
VCCIO19 VSSSA_SENSE VSS_SENSE_SA <88>
J26 RH469 1 2 100_0402_1%
J27 VCCIO20 H14
VCCIO21 VCCIO_SENSE J14
12 OF 13 VSSIO_SENSE
1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils
CFL-H_BGA1440 3. RC15, RC16 should be placed within 2 inches (50.8 mm) of CPU
@
B
VCCIO_SENSE <87> B
VSSIO_SENSE <87>
Backside cap Backside cap
+VCCIO
+VDDQ_DDR +VDDQ_DDR
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1 1 1
CH102
CH103
CH104
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1 1 1 1
2 2 2 1 1 1 1 1 1 1 1 1 1 1
CH129
CH130
CH131
CH132
CH118
CH121
CH124
CH120
CH119
CH122
CH123
CH125
CH126
CH127
CH128
2 2 2 2
2 2 2 2 2 2 2 2 2 2 2
A A

P010-CPU(5/7) PWR,VDDR,VSA,VIO
5 4 3 2 1
Vinafix.com
5 4 3 2 1
+VCC_GT
GT +VCC_GT
55000mA(Hexa Core GT2)
CFL-H
UH1K
AT14 BD35
AT31 VCCGT1 VCCGT80 BD36
AT32 VCCGT2 VCCGT81 BE31
D AT35 VCCGT5 VCCGT84 BE34 D
AU14 VCCGT9 VCCGT88 BE38
AU29 VCCGT10 VCCGT89 BF13
AV29 VCCGT18 VCCGT97 BF37
AV30 VCCGT19 VCCGT98 BF38
AV31 VCCGT20 VCCGT99 BG29
AW14 VCCGT26 VCCGT105 BG35
AW31 VCCGT27 VCCGT106 BG36
AW32 VCCGT28 VCCGT107 BH33
AW38 VCCGT34 VCCGT113 BJ16
AY29 VCCGT35 VCCGT114 BJ17
C AY31 VCCGT37 VCCGT116 BJ20 C
BA13 VCCGT43 VCCGT122 BJ37
BA14 VCCGT44 VCCGT123 BJ38
BA29 VCCGT45 VCCGT124 BK16
BB13 VCCGT53 VCCGT132 BK27
BB14 VCCGT54 VCCGT133 BL15
BC29 VCCGT63 VCCGT142 BL36
BC30 VCCGT64 VCCGT143 BL37
BC31 VCCGT65 VCCGT144 BM15
B BC37 VCCGT69 VCCGT148 BM37 B
BC38 VCCGT70 VCCGT149 BN15
BD13 VCCGT71 VCCGT150 BN16
BD30 VCCGT74 VCCGT153 BN37 +VCC_GT
BD32 VCCGT76 VCCGT155 BP15
BP37 VCCGT79 VCCGT158 BR37
BP38 VCCGT159 VCCGT164 BT15
1
BR15 VCCGT160 VCCGT165 BT16
VCCGT161 VCCGT166 RH203
BR16 BT17
BR17 VCCGT162 VCCGT167 BT37 100_0402_1%
VCCGT163 VCCGT168
2
AH37 VSSGT_SENSE_R RH204 1 2 0_0402_5%
11 OF VSSGT_SENSE VCCGT_SENSE_R VSS_SENSE_GT <88>
13 AH38 RH471 1 2 0_0402_5% VCC_SENSE_GT <88>
VCCGT_SENSE
CFL-H_BGA1440
@
1
RH472
100_0402_1%
1. VccGT_SENSE / VssGT_SENSE Trace Length Match < 25 mils

2
3. RC12, RC13 should be placed within 2 inches (50.8 mm) of CPU
A A
Security Classification Compal Secret Data Compal Electronics,TitleInc.

Issued Date 2019/11/30 Deciphered Date 2027/06/21
P011-CPU(6/7) PWR,VGT
5 4 3 2 1
Vinafix.com
5 4 3 2 1
CFL-H CFL-H CFL-H

UH1F UH1G UH1H
A10 AK4 AW5 BJ15 BN4 F15
A12 VSS_1 VSS_82 AL10 AY12 VSS_163 VSS_244 BJ18 BN7 VSS_325 VSS_409 F17
A16 VSS_2 VSS_83 AL12 AY33 VSS_164 VSS_245 BJ22 BP12 VSS_326 VSS_410 F19
D A18 VSS_3 VSS_84 AL14 AY34 VSS_165 VSS_246 BJ25 BP14 VSS_327 VSS_411 F2 D
A20 VSS_4 VSS_85 AL33 B9 VSS_166 VSS_247 BJ29 BP18 VSS_328 VSS_412 F21
A22 VSS_5 VSS_86 AL34 BA10 VSS_167 VSS_248 BJ30 BP21 VSS_329 VSS_413 F23
A6 VSS_10 VSS_91 AM1 BA6 VSS_172 VSS_253 BJ35 BP33 VSS_334 VSS_418 F31
A9 VSS_11 VSS_92 AM12 BA7 VSS_173 VSS_254 BJ36 BP34 VSS_335 VSS_419 F36
AA12 VSS_12 VSS_93 AM2 BA8 VSS_174 VSS_255 BK13 BP7 VSS_336 VSS_420 F4
AA29 VSS_13 VSS_94 AM3 BA9 VSS_175 VSS_256 BK14 BR12 VSS_337 VSS_421 F5
AA30 VSS_14 VSS_95 AM37 BB1 VSS_176 VSS_257 BK15 BR14 VSS_338 VSS_422 F8
AB33 VSS_15 VSS_96 AM38 BB12 VSS_177 VSS_258 BK18 BR18 VSS_339 VSS_423 F9
AB34 VSS_16 VSS_97 AM4 BB2 VSS_178 VSS_259 BK22 BR21 VSS_340 VSS_424 G10
AB6 VSS_17 VSS_98 AM5 BB29 VSS_179 VSS_260 BK25 BR24 VSS_341 VSS_425 G12
AC1 VSS_18 VSS_99 AN12 BB3 VSS_180 VSS_261 BK29 BR25 VSS_342 VSS_426 G14
AC12 VSS_19 VSS_100 AN29 BB30 VSS_181 VSS_262 BK6 BR26 VSS_343 VSS_427 G16
AC2 VSS_20 VSS_101 AN30 BB4 VSS_182 VSS_263 BL13 BR29 VSS_344 VSS_428 G18
AC38 VSS_23 VSS_104 AP10 BC12 VSS_185 VSS_266 BL19 BR7 VSS_347 VSS_431 G23
AC4 VSS_24 VSS_105 AP11 BC13 VSS_186 VSS_267 BL20 BT12 VSS_348 VSS_432 G24
AD10 VSS_27 VSS_108 AP34 BC34 VSS_189 VSS_270 BL29 BT21 VSS_351 VSS_435 G4
AD11 VSS_28 VSS_109 AP8 BC6 VSS_190 VSS_271 BL33 BT24 VSS_352 VSS_436 G5
AD12 VSS_29 VSS_110 AP9 BD10 VSS_191 VSS_272 BL35 BT26 VSS_353 VSS_437 G6
AD29 VSS_30 VSS_111 AR1 BD11 VSS_192 VSS_273 BL38 BT29 VSS_354 VSS_438 G8
AD30 VSS_31 VSS_112 AR13 BD12 VSS_193 VSS_274 BL6 BT32 VSS_355 VSS_439 G9
AD6 VSS_32 VSS_113 AR14 BD37 VSS_194 VSS_275 BM11 BT5 VSS_356 VSS_440 H11
AD8 VSS_33 VSS_114 AR2 BD6 VSS_195 VSS_276 BM12 C11 VSS_357 VSS_441 H12
AD9 VSS_34 VSS_115 AR29 BD7 VSS_196 VSS_277 BM13 C13 VSS_358 VSS_442 H18
C AE33 VSS_35 VSS_116 AR3 BD8 VSS_197 VSS_278 BM14 C15 VSS_359 VSS_443 H22 C
AE34 VSS_36 VSS_117 AR30 BD9 VSS_198 VSS_279 BM18 C17 VSS_360 VSS_444 H25
AE6 VSS_37 VSS_118 AR31 BE1 VSS_199 VSS_280 BM2 C19 VSS_361 VSS_445 H32
AF1 VSS_38 VSS_119 AR32 BE2 VSS_200 VSS_281 BM21 C21 VSS_362 VSS_446 H35
AF12 VSS_39 VSS_120 AR33 BE29 VSS_201 VSS_282 BM22 C23 VSS_363 VSS_447 J10
AG10 VSS_45 VSS_126 AR4 BF12 VSS_207 VSS_288 BM28 C5 VSS_369 VSS_453 J36
AG11 VSS_46 VSS_127 AR5 BF33 VSS_208 VSS_289 BM29 C8 VSS_370 VSS_454 J4
AG13 VSS_47 VSS_128 AT29 BF34 VSS_209 VSS_290 BM3 C9 VSS_371 VSS_455 J7
AG29 VSS_48 VSS_129 AT30 BF6 VSS_210 VSS_291 BM33 D10 VSS_372 VSS_456 K1
AG30 VSS_49 VSS_130 AT6 BG12 VSS_211 VSS_292 BM35 D12 VSS_373 VSS_457 K10
AG6 VSS_50 VSS_131 AU10 BG13 VSS_212 VSS_293 BM38 D14 VSS_374 VSS_458 K11
AH12 VSS_53 VSS_134 AU33 BG38 VSS_215 VSS_296 BM7 D20 VSS_377 VSS_461 K38
AH33 VSS_54 VSS_135 AU34 BG6 VSS_216 VSS_297 BM8 D22 VSS_378 VSS_462 K4
AH34 VSS_55 VSS_136 AU6 BH1 VSS_217 VSS_298 BM9 D24 VSS_379 VSS_463 K5
AH35 VSS_56 VSS_137 AU7 BH10 VSS_218 VSS_299 BN12 D26 VSS_380 VSS_464 K7
AJ1 VSS_59 VSS_140 AV37 BH14 VSS_221 VSS_302 BN19 D30 VSS_383 VSS_467 L29
AJ13 VSS_60 VSS_141 AV38 BH2 VSS_222 VSS_303 BN2 D33 VSS_384 VSS_468 L30
AJ2 VSS_61 VSS_142 AW1 BH3 VSS_223 VSS_304 BN20 D6 VSS_385 VSS_469 L33
AJ3 VSS_62 VSS_143 AW12 BH4 VSS_224 VSS_305 BN21 D9 VSS_386 VSS_470 L34
AJ37 VSS_63 VSS_144 AW2 BH5 VSS_225 VSS_306 BN24 E34 VSS_387 VSS_471 M12
AJ38 VSS_64 VSS_145 AW29 BH6 VSS_226 VSS_307 BN29 E35 VSS_388 VSS_472 M13
AJ4 VSS_65 VSS_146 AW3 BH7 VSS_227 VSS_308 BN30 E38 VSS_389 VSS_473 N10
AJ5 VSS_66 VSS_147 AW30 BH8 VSS_228 VSS_309 BN31 E4 VSS_390 VSS_474 N11
B AJ6 VSS_67 VSS_148 AW4 BH9 VSS_229 VSS_310 BN34 E9 VSS_391 VSS_475 N12 B
W4 VSS_68 VSS_149 U6 T2 VSS_230 VSS_311 P38 N3 VSS_392 VSS_476 N2
W5 VSS_69 VSS_150 V12 T3 VSS_231 VSS_312 P6 N33 VSS_393 VSS_477 BT8
Y10 VSS_70 VSS_151 V29 T33 VSS_232 VSS_313 R12 N34 VSS_394 VSS_478 BR9
Y11 VSS_71 VSS_152 V30 T34 VSS_233 VSS_314 R29 N4 VSS_395 VSS_479
Y13 VSS_72 VSS_153 A14 T4 VSS_234 VSS_315 AY14 N5 VSS_396 A3
Y14 VSS_73 VSS_154 AD7 T5 VSS_235 VSS_316 BD38 N6 VSS_397 VSS_A3 A34
Y37 VSS_74 VSS_155 V6 T7 VSS_236 VSS_317 R30 N7 VSS_398 VSS_A34 A4
Y38 VSS_75 VSS_156 W1 T8 VSS_237 VSS_318 T1 N8 VSS_399 VSS_A4 B3
Y7 VSS_76 VSS_157 W12 T9 VSS_238 VSS_319 T10 N9 VSS_400 VSS_B3 B37
Y8 VSS_77 VSS_158 W2 U37 VSS_239 VSS_320 T11 P12 VSS_401 VSS_B37 BR38
Y9 VSS_78 VSS_159 W3 U38 VSS_240 VSS_321 T12 P37 VSS_402 VSS_BR38 BT3
AK29 VSS_79 VSS_160 W33 BJ12 VSS_241 VSS_322 T13 M14 VSS_403 VSS_BT3 BT35
AK30 VSS_80
6 OF VSS_161
13 W34 BJ14 VSS_2427 OF VSS_323
13 T14 M6 VSS_404 VSS_BT35 BT36
VSS_81 VSS_162 VSS_243 VSS_324 N1 VSS_405 VSS_BT36 BT4
F11 VSS_406 VSS_BT4 C2
CFL-H_BGA1440 CFL-H_BGA1440 VSS_4078 OF 13
VSS_C2
F13 D38
@ @ VSS_408 VSS_D38
CFL-H_BGA1440
@
A A

Vinafix.com THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
P012-CPU(7/7) VSS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
5 4 3 2 1
5 4 3 2 1
+3V_PCH
CNP-H
UH2C
AR2 G36 TBT_CIO_PLUG_EVENT# 1 @ 2
<52> CLINK_CLK CL_CLK PCIE9_RXN PCIE_PRX_DTX_N09 <68>
AT5 F36 RH5889 10K_0201_5%
<52> CLINK_DATA CL_DATA PCIE9_RXP PCIE_PRX_DTX_P09 <68>
<52> CLINK_RST# AU4 C34 PCIE_PTX_DRX_N09 <68>
CL_RST# PCIE9_TXN D34 M2280_PCIE_SATA#1 1 2
PCH_GPP_K8_BALL PCIE9_TXP PCIE_PTX_DRX_P09 <68>
TP@PAD~D T91 P48 RH508 10K_0201_5%
TP@PAD~D T92 PCH_GPP_K9_BALL V47 GPP_K8
GPP_K9 SSD Port1 M2280_PCIE_SATA#2
V48 K37 1 2
GPP_K10 PCIE10_RXN PCIE_PRX_DTX_N10 <68>
W47 J37 PCIE_PRX_DTX_P10 <68> RH5901 10K_0201_5%
GPP_K11 PCIE10_RXP C35
PCIE10_TXN PCIE_PTX_DRX_N10 <68> PCH_PLTRST#_EC_AR
L47 B35 PCIE_PTX_DRX_P10 <68> 1 2
D
TP@PAD~D T94 PCH_GPP_K2_BALL L46 GPP_K0 PCIE10_TXP RH6902 100K_0201_5%
D
U48 GPP_K1 F44
U47 GPP_K2 PCIE15_RXN/SATA2_RXN E45
N48 GPP_K3 PCIE15_RXP/SATA2_RXP B40
N47 GPP_K4 PCIE_15_SATA_2_TXN C40
P47 GPP_K5 PCIE15_TXP/SATA2_TXP
R46 GPP_K6 L41 SATAGP0 RH5844 1 2 10K_0201_5%
GPP_K7 PCIE16_RXN/SATA3_RXN M40
C36 PCIE16_RXP/SATA3_RXP B41 SATAGP2 RH5845 1 2 10K_0201_5%
<68> PCIE_PTX_DRX_P11
B36 PCIE11_TXP/SATA0A_TXP PCIE16_TXN/SATA3_TXN C41
<68> PCIE_PTX_DRX_N11 PCIE11_TXN/SATA0A_TXN PCIE16_TXP/SATA3_TXP
SSD Port1 <68> PCIE_PRX_DTX_P11 F39 SATAGP3 RH5846 1 2 10K_0201_5%
G38 PCIE11_RXP/SATA0A_RXP K43
<68> PCIE_PRX_DTX_N11 PCIE11_RXN/SATA0A_RXN PCIE17_RXN/SATA4_RXN SATA_PRX_DTX_N4A <69>
K44 SATA_PRX_DTX_P4A <69> SATAGP5 RH5847 1 2 10K_0201_5%
BIOS_REC AR42 PCIE17_RXP/SATA4_RXP A42
GPP_F10/SATA_SCLOCK PCIE17_TXN/SATA4_TXN SATA_PTX_DRX_N4A <69> SSD Port2 SATA4
AR48 B42 SATA_PTX_DRX_P4A <69>
AU47 GPP_F11/SATA_SLOAD PCIE17_TXP/SATA4_TXP
PANEL_BKEN_PCH AU46 GPP_F13/SATA_SDATAOUT0 P41 TS_DETECT# RH5849 1 @ 2 10K_0201_5%
GPP_F12/SATA_SDATAOUT1 PCIE18_RXN/SATA5_RXN PCIE_PRX_DTX_N18 <69>
R40 PCIE_PRX_DTX_P18 <69> SSD Port2
C39 PCIE18_RXP/SATA5_RXP C42
PCIE14_TXN/SATA1B_TXN PCIE18_TXN/SATA5_TXN PCIE_PTX_DRX_N18 <69>
D39 D42 PCIE_PTX_DRX_P18 <69>
D46 PCIE14_TXP/SATA1B_TXP PCIE18_TXP/SATA5_TXP
C47 PCIE14_RXN/SATA1B_RXN AK48 SATALED#
PCIE14_RXP/SATA1B_RXP GPP_E8/SATA_LED# +3VS
B38 AH41 SATAGP0
C38 PCIE13_TXN/SATA0B_TXN GPP_E0/SATAXPCIE0/SATAGP0 AJ43 M2280_PCIE_SATA#1
PCIE13_TXP/SATA0B_TXP GPP_E1/SATAXPCIE1/SATAGP1 M2280_PCIE_SATA#1 <68> BIOS_REC
C45 AK47 SATAGP2 1 2
C46 PCIE13_RXN/SATA0B_RXN GPP_E2/SATAXPCIE2/SATAGP2 AN47 SATAGP3 RH5840 10K_0201_5%
PCIE13_RXP/SATA0B_RXP GPP_F0/SATAXPCIE3/SATAGP_3 AM46 M2280_PCIE_SATA#2
GPP_F1/SATAXPCIE4/SATAGP4 M2280_PCIE_SATA#2 <69> CAM_CBL_DET#
E37 AM43 SATAGP5 1 2
<68> SATA_PTX_DRX_P1A PCIE12_TXP/SATA1A_TXP GPP_F2/SATAXPCIE5/SATAGP5 TS_DETECT#
SSD Port1 SATA1A <68> SATA_PTX_DRX_N1A D38 AM47 TS_DETECT# <38> RH511 10K_0201_5%
J41 PCIE12_TXN/SATA1A_TXN GPP_F3/SATAXPCIE6/SATAGP6 AM48 PCH_PLTRST#_EC_AR
<68> SATA_PRX_DTX_P1A PCIE12_RXP/SATA_1A_RXP GPP_F4/SATAXPCIE7/SATAGP7 PCH_PLTRST#_EC_AR <42>
H42 SATALED# 1 2
<68> SATA_PRX_DTX_N1A PCIE12_RXN/SATA1A_RXN AU48 BIA_PWM_PCH <6,38> RH512 10K_0201_5%
B44 GPP_F21/EDP_BKLTCTL AV46
<69> PCIE_PTX_DRX_P20 PCIE20_TXP/SATA7_TXP GPP_F20/EDP_BKLTEN PANEL_BKEN_PCH <38>
<69> PCIE_PTX_DRX_N20 A44 AV44 ENVDD_PCH <77>
R37 PCIE20_TXN/SATA7_TXN GPP_F19/EDP_VDDEN
<69> PCIE_PRX_DTX_P20 R35 PCIE20_RXP/SATA7_RXP AD3 H_THERMTRIP# RH191 1 2 620_0402_5%
H_THERMTRIP#_R <8,58>
<69> PCIE_PRX_DTX_N20 PCIE20_RXN/SATA7_RXN THRMTRIP# PCH_PECI
C D43 AF2 RH539 1 2 13_0402_5% H_PECI <8,58> C
<69> PCIE_PTX_DRX_P19 C44 PCIE19_TXP/SATA6_TXP PECI AF3 H_PM_SYNC RH189 1 2 30_0402_5% PCH_PECI
SSD Port2 <69> PCIE_PTX_DRX_N19 H_PM_SYNC_R <8> RH5836 1 @ 2 10K_0201_5%
N42 PCIE19_TXN/SATA6_TXN PM_SYNC AG5
<69> PCIE_PRX_DTX_P19 PCIE19_RXP/SATA6_RXP 3 OF 13 PLTRST_CPU# PLTRST_CPU# <8,79>
M44 AE2
<69> PCIE_PRX_DTX_N19 PCIE19_RXN/SATA6_RXN PM_DOWN H_PM_DOWN <8>
CNP-H_BGA874 Rev1.0
+3VS
CNP-H
UH2E AUD_PWR_EN RH569 1 2 100K_0201_5%
AL13 DDI1_DDPB_CTRLCLK
GPP_I5/DDPB_CTRLCLK AR8 Strap PinDDI1_DDPB_CTRLDAT @
AT6 GPP_I6/DDPB_CTRLDATA AN13 DDI2_DDPC_CTRLCLK
DP1/DP2 from Titan Ridge <42> PCH_DP1_HPD GPP_I0/DDPB_HPD0/DISP_MISC0 GPP_I7/DDPC_CTRLCLK
AN10 AL10 Strap PinDDI2_DDPC_CTRLDAT
<42> PCH_DP2_HPD GPP_I1/DDPC_HPD1/DISP_MISC1 GPP_I8/DDPC_CTRLDATA DDI3_DDPD_CTRLCLK
DP3 Re-driver PS8802 <47,48> PCH_DP3_HPD AP9 AL9
AL15 GPP_I2/DDPD_HPD2/DISP_MISC2 GPP_I9/DDPD_CTRLCLK AR3 Strap PinDDI3_DDPD_CTRLDAT
GPP_I3/DDPF_HPD3/DISP_MISC3 GPP_I10/DDPD_CTRLDATA AN40 PCH_GPP_F23_BALL
GPP_F23/DDPF_CTRLDATA AT49 T2 PAD~D TP@ EDP_HPD RV114 1 2 100K_0201_5%
GPP_F22/DDPF_CTRLCLK
AP41 PROC_DETECT# <8>
EDP_HPD AN6 GPP_F14/PS_ON#
<38,58> EDP_HPD GPP_I4/EDP_HPD/DISP_MISC4
M45 PCH_GPP_K23_BALL T4 PAD~D TP@
Strap Definitions(GPP_I6 / DDPB_CTRLDATA)
GPP_K23/IMGCLKOUT1
GPP_K22/IMGCLKOUT0
L48 Strap Definitions(GPP_I8 / DDPC_CTRLDATA)
GPP_K21
T45
T46
Strap Definitions(GPP_I10 /DDPD_CTRLDATA)
GPP_K20 AJ47 PCH_GPP_H23_BALL
GPP_J9 Strap Definitions 5 OF 13
GPP_H23/TIME_SYNC0
T8 PAD~D TP@
+3VS
+1.8VALW CNP-H_BGA874 Rev1.0
@ RP1
B DDI2_DDPC_CTRLCLK 1 8 B
DDI2_DDPC_CTRLDAT 2 7
100K_0201_5%
1
DDI1_DDPB_CTRLCLK 3 6
@ DDI1_DDPB_CTRLDAT 4 5
RH5855
2.2K_0804_8P4R_5%
2
CNV_COEX1 CNP-H DDI3_DDPD_CTRLCLK 2.2K_0201_5% 1 2 RH1145

UH2M DDI3_DDPD_CTRLDAT 2.2K_0201_5% 1 2 RH1146
100K_0201_5%
CAM_CBL_DET#
1
GPP_J9 AW13 BD4

<38> CAM_CBL_DET# GPP_G0/SD_CMD CNV_WR_CLKN CLK_CNV_PRX_DTX_N <52>
VCCSPI hard strap BE9 BE3
<27> GC6_EVENT# TBT_CIO_PLUG_EVENT# BF8 GPP_G1/SD_DATA0 CNV_WR_CLKP CLK_CNV_PRX_DTX_P <52> This signal has a weak internal pull-down.
<42> TBT_CIO_PLUG_EVENT#
0 = Port X is not detected. (Default)
RH5890
BF9 GPP_G2/SD_DATA1 BB3

HIGH 1.8V <27> GPU_GC6_FB_EN GPP_G3/SD_DATA2 CNV_WR_D0N CNV_PRX_DTX_N0 <52>
<38> S_BIO
BG8
GPP_G4/SD_DATA3 CNV_WR_D0P
BB4 CNV_PRX_DTX_P0 <52> 1 = Port X is detected.
2
HOST_SD_WP# BE8 BA3

<55> HOST_SD_WP# AUD_PWR_EN GPP_G5/SD_CD# CNV_WR_D1N CNV_PRX_DTX_N1 <52> +3VS
* LOW 3.3V
BD8
AV13 GPP_G6/SD_CLK
GPP_G7/SD_WP
CNV_WR_D1P
BA2
CNV_PRX_DTX_P1 <52>
BC5
AP3 CNV_WT_CLKN BB6 CLK_CNV_PTX_DRX_N <52> HOST_SD_WP# 10K_0201_5% 2 1 RH563
AP2 GPP_I11/M2_SKT2_CFG0 CNV_WT_CLKP CLK_CNV_PTX_DRX_P <52>
AN4 GPP_I12/M2_SKT2_CFG1 BE6
GPP_I13/M2_SKT2_CFG2 CNV_WT_D0N CNV_PTX_DRX_N0 <52>
PAD~D TP@
AM7
GPP_I14/M2_SKT2_CFG3 CNV_WT_D0P
BD7
BG6 CNV_PTX_DRX_P0 <52> PCH Strap PIN
T4949 CNV_WT_D1N CNV_PTX_DRX_N1 <52>
AV6 BF6
CPU_C10_GATE# RH5835 1 2 0_0402_5% CPU_VCCIO_PWR_GATE# AY3 GPP_J0/CNV_PA_BLANKING CNV_WT_D1P BA1 CNV_WT_RCOMP RH588 1 2 150_0201_1% CNV_PTX_DRX_P1 <52>
<78,87> CPU_C10_GATE#
AR13 GPP_J1/CPU_C10_GATE# CNV_WT_RCOMP
AV7 GPP_J11/A4WP_PRESENT B12 PCIE_RCOMPN RH108 1 2 100_0201_1%
Strap Pin option on P52 AW3 GPP_J10 PCIE_RCOMPN A13 PCIE_RCOMPP
GPP_J4/GPP_J6 AT10 GPP_J_2 PCIE_RCOMPP BE5 SD_1P8_RCOMP RH5832 1 2 200_0201_1%
RW123 1 @ 2 33_0201_1% CNV_BRI_PTX_DRX Strap Pin AV4 GPP_J_3 SD_1P8_RCOMP BE4 SD_3P3_RCOMP RH5833 1 2 200_0201_1%
<52> CNV_BRI_PTX_R_DRX CNV_BRI_PRX_DTX AY2 GPP_J4/CNV_BRI_DT/UART0B_RTS# SD_3P3_RCOMP BD1
<52> CNV_BRI_PRX_DTX RW124 1 @ 2 33_0201_1% CNV_RGI_PTX_DRX Strap Pin BA4 GPP_J5/CNV_BRI_RSP/UART0B_RXD GPPJ_RCOMP_1P81 BE1 GPPJ_RCOMP RH5834 1 2 200_0201_1%
<52> CNV_RGI_PTX_R_DRX CNV_RGI_PRX_DTX AV3 GPP_J6/CNV_RGI_DT/UART0B_TXD GPPJ_RCOMP_1P82 BE2
<52> CNV_RGI_PRX_DTX CNV_COEX1_R GPP_J7/CNV_RGI_RSP/UART0B_CTS# GPPJ_RCOMP_1P83
0_0201_5% 2 @ 1 RH666 AW2
CNV_COEX1 Strap Pin AU9 GPP_J8/CNV_MFUART2_RXD Y35 PMRSVD2 T4963 PAD~D TP@
GPP_J9/CNV_MFUART2_TXD RSVD2 Y36 PMRSVD3 T4962 PAD~D TP@
RSVD3
A A
BC1 PMRSVD1 T4961 PAD~D TP@
13 OF 13 RSVD1 AL35 PCH_TP_BALL T4947 PAD~D TP@
TP
+1.8VALW CNP-H_BGA874 Rev1.0
@
DVT2.1_16:PDG already internal pull up ,now BIOS set is native mode ,so this change keep monitor
20K_0201_5% 2 @ 1 RH5853 CNV_BRI_PRX_DTX

20K_0201_5% 2 @ 1 RH5854 CNV_RGI_PRX_DTX

P013-PCH (1/7)SATA,DDC,PCIE,CNV

5 4 3 2 1
5 4 3 2 1
+3VS
CLKREQ_PCIE#3
RTC CRYSTAL
RH1203 1 2 10K_0201_5%
RH1202 1 2 10K_0201_5% CLKREQ_PCIE#4 CNP-H
RH1201 1 2 10K_0201_5% CLKREQ_PCIE#5 UH2G
RH1200 1 2 10K_0201_5% CLKREQ_PCIE#6 BE33 PCH_RTCX1
GPP_A16/CLKOUT_48
D7 Y3 RH70 1 2 10M_0402_5% PCH_RTCX2
<8> CPU_24MHZ_P CLKOUT_CPUNSSC_P CLKOUT_ITPXDP# PCH_XDP_CLK_N <79>
<8> CPU_24MHZ_N C6 Y4 PCH_XDP_CLK_P <79> YH1
CLKOUT_CPUNSSC# CLKOUT_ITPXDP_P 32.768KHZ_X1A000141000300
+3VS B8 B6
<8> PCH_CPU_BCLK_P CLKOUT_CPUBCLK_P CLKOUT_CPUPCIBCLK# PCH_CPU_PCIBCLK_N <8>
<8> PCH_CPU_BCLK_N C8 A6 PCH_CPU_PCIBCLK_P <8> 1 2
CLKOUT_CPUBCLK# CLKOUT_CPUPCIBCLK_P
RH548 1 @ 2 10K_0201_5% CLKREQ_PCIE#0 XTAL24_OUT U9 AJ6
RH549 1 2 10K_0201_5% CLKREQ_PCIE#1 XTAL24_IN U10 XTAL_OUT CLKOUT_PCIE_N0 AJ7
RH550 1 @ 2 10K_0201_5% SRCCLKREQ2# XTAL_IN CLKOUT_PCIE_P0 Max Crystal
RH551 1 2 10K_0201_5% CLKREQ_PCIE#7 RH71 1 2 60.4_0402_1% XCLK_BIASREF T3 AH9 1
ESR = 50k Ohm. 1
XCLK_BIASREF CLKOUT_PCIE_N1 CLK_PCIE_N1 <69>
AH10 CLK_PCIE_P1 <69> NGFF - SSD2
PCH_RTCX1 BA49 CLKOUT_PCIE_P1 CH45 CH46
XCLK_BIASREF PCH_RTCX2 RTCX1 7.5P_0201_50V8B
BA48 AE14 8.2P_0201_25V8D
+3VS Trace Width/Space: 15mil /15 mil RTCX2 CLKOUT_PCIE_N2 AE15 2 2
D D
@ Max Trace Length: 1000 mil CLKREQ_PCIE#0 BF31 CLKOUT_PCIE_P2
RP22 CLKREQ_PCIE#1 BE31 GPP_B5/SRCCLKREQ0# AE6
NGFF - SSD2 <69> CLKREQ_PCIE#1 GPP_B6/SRCCLKREQ1# CLKOUT_PCIE_N3 CLK_PCIE_N3 <68>
4 5 SRCCLKREQ9# SRCCLKREQ2# AR32 AE7 CLK_PCIE_P3 <68> NGFF - SSD
3 6 CLKREQ_PCIE#3 BB30 GPP_B7/SRCCLKREQ2# CLKOUT_PCIE_P3
SRCCLKREQ15# NGFF - SSD1 <68> CLKREQ_PCIE#3 CLKREQ_PCIE#4 GPP_B8/SRCCLKREQ3#
2 7 SRCCLKREQ8# Card Reader <55> CLKREQ_PCIE#4 BA30 AC2 CLK_PCIE_N4 <55>
1 8 CLKREQ_PCIE#5 AN29 GPP_B9/SRCCLKREQ4# CLKOUT_PCIE_N4 AC3
SRCCLKREQ10# Thunderbolt1 <42> CLKREQ_PCIE#5 CLKREQ_PCIE#6 GPP_B10/SRCCLKREQ5# CLKOUT_PCIE_P4 CLK_PCIE_P4 <55> Card Reader XTAL24_IN_R XTAL24_IN
NGFF - WLAN.CNVi <52> CLKREQ_PCIE#6 AE47 RA96 1 2 33_0201_5%
10K_0804_8P4R_5% CLKREQ_PCIE#7 AC48 GPP_H0/SRCCLKREQ6# AB2
GPU - ( N18P-GX ; N19P-QX )<27> CLKREQ_PCIE#7 GPP_H1/SRCCLKREQ7# CLKOUT_PCIE_N5 CLK_PCIE_N5 <42>
SRCCLKREQ8# AE41 AB3 CLK_PCIE_P5 <42> Thunderbolt
SRCCLKREQ9# AF48 GPP_H2/SRCCLKREQ8# CLKOUT_PCIE_P5 RH72 1 2 1M_0201_5% XTAL24_OUT_R RA97 1 2 33_0201_5% XTAL24_OUT
SRCCLKREQ10# AC41 GPP_H3/SRCCLKREQ9# W4
+3VS GPP_H4/SRCCLKREQ10# CLKOUT_PCIE_N6 CLK_PCIE_N6 <52>
SRCCLKREQ11# AC39 W3 CLK_PCIE_P6 <52> NGFF - WLAN.CNVi
@ SRCCLKREQ12# AE39 GPP_H5/SRCCLKREQ11# CLKOUT_PCIE_P6 YH2
RP23 SRCCLKREQ13# AB48 GPP_H6/SRCCLKREQ12# W7 1 3
GPP_H7/SRCCLKREQ13# CLKOUT_PCIE_N7 CLK_PEG_N7 <27>
4 5 SRCCLKREQ11# SRCCLKREQ14# AC44 W6 CLK_PEG_P7 <27> GPU - ( N18P-GX ; N19P-QX ) 2 4
3 6 SRCCLKREQ13# SRCCLKREQ15# AC43 GPP_H8/SRCCLKREQ14# CLKOUT_PCIE_P7
2 7 SRCCLKREQ14# GPP_H9/SRCCLKREQ15# AC14 24MHZ_12PF_8Y24000034
1 8 SRCCLKREQ12# V2 CLKOUT_PCIE_N8 AC15
CLKOUT_PCIE_N15 CLKOUT_PCIE_P8 1 1
V3
10K_0804_8P4R_5% CLKOUT_PCIE_P15 U2 CH47 CH48
T2 CLKOUT_PCIE_N9 U3 15P_0201_50V8J 15P_0201_50V8J
T1 CLKOUT_PCIE_N14 CLKOUT_PCIE_P9 2 2
CLKOUT_PCIE_P14 AC9
AA1 CLKOUT_PCIE_N10 AC11
Strap Definitions(SPI0_MOSI) Y2 CLKOUT_PCIE_N13 CLKOUT_PCIE_P10
CLKOUT_PCIE_P13 AE9
AC7 CLKOUT_PCIE_N11 AE11 +3V_PCH
AC6 CLKOUT_PCIE_N12 CLKOUT_PCIE_P11
CLKOUT_PCIE_P12 7 OF 13 R6 CLKIN_XTAL
CLKIN_XTAL CLKIN_XTAL <52> SIO_EXT_SMI#_R RH110 1 2 10K_0201_5%
1
CNP-H_BGA874 Rev1.0
@
RH5850 +3VS
10K_0201_5%
2
TOUCH_SCREEN_PD# RH510 1 2 10K_0201_5%
TOUCHPAD_INTR# RH547 1 2 10K_0201_5%
G3 set EC_SLP_S0IX# RH535 1 2 10K_0201_5%
DGPU_PWR_EN RH537 1 2 10K_0201_5%
+3V_PCH
Reserve For EC Auto Load Code
C C
CNP-H
RH74 1 2 4.7K_0201_5% CPU_SPI_0_CS#0 UH2A +RTCVCC
TP@PAD~D T17 PCH_GPP_A11_BALL BE36 AV29 PCH_PLTRST#
GPP_A11/PME#/SD_VDD2_PWR_EN# GPP_B13/PLTRST#
INTRUDER# RH531 1 2 1M_0201_5%
TP@PAD~D T4950 PARSVD2 R15 Y47
RH55 1 @G3@ 2 100K_0201_5% CPU_SPI_0_D1 TP@PAD~D T4951 PARSVD1 R13 RSVD2 GPP_K16/GSXCLK Y46 PCH_PLTRST#
RSVD1 GPP_K12/GSXDOUT Y48
GPP_K13/GSXSLOAD 1
W46 @
AL37 GPP_K14/GSXDIN AA45 CH3327
AN35 VSS GPP_K15/GSXSRESET#
TP 10P_0201_50V8J
2
CPU_SPI_0_D0 Strap Pin AU41 AL47 BID_DIS
CPU_SPI_0_D1 SPI0_MOSI GPP_E3/CPU_GP0 TOUCH_SCREEN_PD# BID_DIS <17,58>
BA45 AM45 TOUCH_SCREEN_PD# <38>
CPU_SPI_0_CS#0 AY47 SPI0_MISO GPP_E7/CPU_GP1 BF32 TOUCHPAD_INTR# +3V_PCH
<79> CPU_SPI_0_CS#0 CPU_SPI_0_CLK SPI0_CS0# GPP_B3/CPU_GP2 EC_SLP_S0IX#
AW47 BC33
RH423 2 @ 1 100K_0201_5% 3.3V_mSATA_EN AW48 SPI0_CLK GPP_B4/CPU_GP3
To SPI ROM <79> CPU_SPI_0_CS#1 SPI0_CS1# AE44
CPU_SPI_0_D2 Strap Pin AY48 GPP_H18/SML4ALERT# AJ46
RH5892 2 1 100K_0201_5% CPU_SPI_0_CLK CPU_SPI_0_D3 Strap Pin BA46 SPI0_IO2 GPP_H17/SML4DATA AE43
SPI0_IO3 GPP_H16/SML4CLK GPP_H15 RTD3_CIO_PWR_EN <42>
5
<66> CPU_SPI_0_CS#2 AT40 AC47 Strap Pin UH7
SPI0_CS2# GPP_H15/SML3ALERT# AD48 DGPU_PWR_EN 1 PCH_PLTRST#
DGPU_PWR_EN <37>
P
BE19 GPP_H14/SML3DATA AF47 4 B
GPP_D1/SPI1_CLK/SBK1_BK1 GPP_H13/SML3CLK GPP_H12 <27,42,52,55,66,68,69,79> PCH_PLTRST#_EC Y
BF19 AB47 Strap Pin 2
SIO_EXT_SMI#_R GPP_D0/SPI1_CS#/SBK0_BK0 GPP_H12/SML2ALERT# A
G
BF18 AD47
3.3V_mSATA_EN GPP_D3/SPI1_MOSI/SBK3_BK3 GPP_H11/SML2DATA
1
BE18 AE48 TC7SH08FU_SSOP5
GPP_D2/SPI1_MISO/SBK2_BK2 GPP_H10/SML2CLK
3
BC17
BD17 GPP_D22/SPI1_IO3 1 OF 13 BB44 INTRUDER# RH77
GPP_D21/SPI1_IO2 INTRUDER# 100K_0402_5%
CNP-H_BGA874 Rev1.0
2
CPU_SPI_CLK CPU_SPI_0_CLK @
<66,79> CPU_SPI_CLK RH577 1 2 0_0201_5%
CPU_SPI_D0 RH578 1 2 0_0201_5% CPU_SPI_0_D0
<66,79> CPU_SPI_D0 CPU_SPI_D1 RH579 1 2 0_0201_5% CPU_SPI_0_D1 Form PCH Close PR313
TPM <66,79> CPU_SPI_D1 CPU_SPI_D2 RH5899 1 2 0_0201_5% CPU_SPI_0_D2
<79> CPU_SPI_D2 CPU_SPI_D3 CPU_SPI_0_D3
<79> CPU_SPI_D3 RH5900 1 2 0_0201_5%
DH1
RH630 1 2 0_0201_5% SPI_CLK_ROM TOUCHPAD_INTR# 2 1
SPI_D0_ROM PTP_INT# <58,59>
RH631 1 2 0_0201_5%
RT881 1 @ 2 CPU_SPI_D2 RH632 1 2 0_0201_5% SPI_D1_ROM To SPI ROM RB751S-40_SOD523-2
<79> CPU_SPI_D2_XDP SPI_D2_ROM
0_0201_5% RH633 1 2 22_0201_1%
<79> CPU_SPI_D0_XDP RT880 1 @ 2 CPU_SPI_D0 RH634 1 2 22_0201_1% SPI_D3_ROM
0_0201_5%
RH635 1 2 0_0402_5% SHD_CLK <58>
B
RH636 1 2 0_0402_5% SHD_IO0 <58> B
RH637 1 2 0_0402_5%
RH638 1 2 75_0402_1%
SHD_IO1 <58> To EC
SHD_IO2 <58>
RH639 1 2 75_0402_1% SHD_IO3 <58>
CPU_SPI_0_CS#0 RT640 1 2 0_0201_5% SHD_CS0# <58>
+3V_PCH MEC5107 G3 Sharing Topology

+3V_ROM
DH2 1 2 RB751S-40_SOD523-2 25-ohm 15-ohm
SPI ROM FOR ME ( 32MByte ) RH585 1 @ 2 0_0603_5%

PCH SPI
UH8 15-ohm 1K-ohm
CPU_SPI_0_CS#0
SPI_D1_ROM
SPI_D2_ROM
1
2 CS#
DO
VCC
IO3
8
7 SPI_D3_ROM
SPI_CLK_ROM
EC XDP
3 6
4 IO2 CLK 5 SPI_D0_ROM
GND DI 9
ThemalPad
GD25B256DYIG_WSON8_8X6-X
TPM 15-ohm
JSPI
DVT1.1_17:change CPN from Winband to Gigidevice SA0000BGM00 S IC FL 256M GD25B256DYIG WSON 8P SPI
GPP_H15/SML3ALERT# GPP_H12/SML2ALERT# SPI0_MOSI/CPU_SPI_0_D0 SPI0_IO2/CPU_SPI_0_D2 SPI0_IO3/CPU_SPI_0_D3

External pull-up is required. Recommend 100K This signal has a weak internal pull-down.
if pulled up to 3.3V External pull-up is required. Recommend 100 kohm External pull-up is required. Recommend 100 kohm External pull-up is required. Recommend 100 kohm
0 = Master Attached Flash Sharing (MAFS) enabled if pulled up to 3.3V if pulled up to 3.3V if pulled up to 3.3V
CRB pop (Default)
CRB Unpop CRB pop CRB pop
A
+3V_PCH 1 = Slave Attached Flash Sharing (SAFS) enabled A
+3V_PCH
+3V_PCH +3V_PCH
+3V_PCH
RH42 1 2 100K_0201_5% GPP_H15

RH78 1 2 100K_0201_5% CPU_SPI_0_D3
RH5881 1 @ 2 4.7K_0201_5% GPP_H12 RH5860 1 2 100K_0402_5% CPU_SPI_0_D0 RH75 1 2 100K_0201_5% CPU_SPI_0_D2
Compal Secret Data Compal Electronics, Inc.

Vinafix.com
Security Classification
P014-PCH (2/7) CLK,SPI,PLTRST
0.4(X03)
5 4 3 2 1
5 4 3 2 1
HDA_SDO / I2S0_TXD
ME_FWP PCH has internal 20K PD.
FLASH DESCRIPTOR SECURITY OVERRIDE
+3V_PCH
1=Disable ME Protect (ME can be updated)
0=Enable ME Protect (ME cannot be updated) PM_LANPHY_ENABLE RH5842 1 @ 2 10K_0201_5%
PCH_PCIE_WAKE# RH453 1 2 1K_0201_5%
PCH_BATLOW# RH515 1 2 8.2K_0201_1%
AC_PRESENT RH533 1 2 8.2K_0201_1%
RP14~RP15 close to PCH
LAN_WAKE# RH545 1 2 10K_0201_5%
RH266 1 2 33_0201_1% HDA_SYNC
D <56> HDA_SYNC_AUDIO HDA_SDOUT D
<56> HDA_SDOUT_AUDIO RH267 1 2 33_0201_1% VRALERT# RH5837 2 @ 1 4.7K_0201_5%
RH268 1 2 33_0201_1% HDA_BITCLK
<56> HDA_BITCLK_AUDIO
+3V_PCH
RH1205 1 DAR@ 2 33_0201_1% PCM_CLK_CPU ME_SUS_PWR_ACK_R RH506 1 @ 2 1M_0201_5%

<52> PCM_CLK PCM_OUT_CPU
RH1206 1 DAR@ 2 33_0201_1%
<52> PCM_OUT PCM_IN_CPU SYS_RESET#
<52> PCM_IN RH1207 1 DAR@ 2 33_0201_1% RH571 1 2 8.2K_0201_1%
RH1208 1 DAR@ 2 33_0201_1% PCM_SYNC_CPU
+RTCVCC <52> PCM_SYNC
RH83 1 2 20K_0201_5% PCH_SRTCRST# CNP-H

UH2D
HDA_BITCLK BD11 BF36 +3VS
1 HDA_SDIN0_AUDIO HDA_BCLK/I2S0_SCLK GPP_A12/BM_BUSY#/ISH_GP6/SX_EXIT_HOLDOFF#
CH52 BE11 AV32 CLKRUN#
<56> HDA_SDIN0_AUDIO HDA_SDOUT HDA_SDI0/I2S0_RXD GPP_A8/CLKRUN#
1U_0201_6.3V6M <79> HDA_SDOUT Strap PinBF12
HDA_SYNC BG13 HDA_SDO/I2S0_TXD BF41 PM_LANPHY_ENABLE CLKRUN# RH85 1 @ 2 8.2K_0201_1%
2 HDA_SYNC/I2S0_SFRM GPD11/LANPHYPC
PCM_CLK_CPU BE10 BD42 SIO_SLP_WLAN#
PCM_OUT_CPU BF10 HDA_RST#/I2S1_SCLK GPD9/SLP_WLAN# SIO_SLP_WLAN# <77> Strap Definitions(GPP_B14 / SPKR)
PCM_IN_CPU BE12 HDA_SDI1/I2S1_RXD BB46
+RTCVCC PCM_SYNC_CPU I2S1_TXD/SNDW2_DATA DRAM_RESET# H_DRAMRST# <23> +3V_PCH
BD12 BE32 VRALERT#
I2S1_SFRM/SNDW2_CLK GPP_B2/VRALERT# BF33
RH84 1 2 20K_0201_5% PCH_RTCRST# Close to PCH GPP_B1/GSPI1_CS1#/TIME_SYNC1 BE29
AUD_AZA_CPU_SDO_R GPP_B0/GSPI0_CS1# TS_I2C_RST# <38>
RH146 1 2 30_0201_1% AM2 R47 SPKR 4.7K_0201_5% 2 @ 1 RH82
<6> AUD_AZA_CPU_SDO AUD_AZA_CPU_SDI_R HDACPU_SDO GPP_K17/ADR_COMPLETE I2C2_IRQ_TS
1 close to BOT AN3 AP29 I2C2_IRQ_TS <38>
<6> AUD_AZA_CPU_SDI_R AUD_AZA_CPU_SCLK_R HDACPU_SDI GPP_B11/I2S_MCLK SYS_PWROK
1
CH53 RH147 1 2 30_0201_1% AM3 AU3

<6> AUD_AZA_CPU_SCLK HDACPU_SCLK SYS_PWROK SYS_PWROK <58,79>
1U_0201_6.3V6M CLRP1
AV18 BB47 PCH_PCIE_WAKE#
SHORT PADS
PCH_GPP_D7_BALL GPP_D8/I2S2_SCLK WAKE# SIO_SLP_A# PCH_PCIE_WAKE# <58> Top Swap Override (internal PD)
2
2 TP@PAD~D T121 AW18 BE40

CLKREQ_CNV# GPP_D7/I2S2_RXD GPD6/SLP_A# PCH_SLP_LAN# SIO_SLP_A# <79>
BA17 BF40 HIGH ENABLE
<52> CLKREQ_CNV# CNV_RF_RESET# BE16 GPP_D6/I2S2_TXD/MODEM_CLKREQ SLP_LAN# BC28 T20 PAD~D TP@
+3V_PCH <52> CNV_RF_RESET# PCH_DMIC_DAT_R RA102 1 2 0_0402_5% PCH_DMIC_DAT BF15 GPP_D5/I2S2_SFRM/CNV_RF_RESET# GPP_B12/SLP_S0# BF42
SIO_SLP_S0# <66,78,79,88> LOW(DEFAULT) DISABLE
<38> PCH_DMIC_DAT_R PCH_DMIC_CLK_R PCH_DMIC_CLK GPP_D20/DMIC_DATA0/SNDW4_DATA GPD4/SLP_S3# SIO_SLP_S4# SIO_SLP_S3# <42,78,79>
<38> PCH_DMIC_CLK_R RA103 1 2 0_0402_5% BD16 BE42
SIO_SLP_S4# <78,79>
DGPU_PWROK AV16 GPP_D19/DMIC_CLK0/SNDW4_CLK GPD5/SLP_S4# BC42
<27,37,58,96> DGPU_PWROK KB_DET# GPP_D18/DMIC_DATA1/SNDW3_DATA GPD10/SLP_S5# SIO_SLP_S5# <79>
C AW15 C
1 2 MEM_SMBCLK <59> KB_DET# GPP_D17/DMIC_CLK1/SNDW3_CLK BE45
RH458
RH459 1 2
1K_0201_5%
1K_0201_5% MEM_SMBDATA DVT1.1_41 :RA102,RA103 change from 33 ohm to 0 ohm for solve mic noise GPD8/SUSCLK BF44 PCH_BATLOW# SUSCLK <52> Strap Definitions(GPP_C2 /SMBALERT#)
RH460 1 2 1K_0201_5% SML1_SMBCLK GPD0/BATLOW# BE35 SUSACK#_R 0_0201_5% 2 1 RH5872
1 2 SML1_SMBDAT PCH_RTCRST# BE47 GPP_A15/SUSACK# BC37 ME_SUS_PWR_ACK_R T6020 PAD~D TP@ +3V_PCH
RH461 1K_0201_5%
RH501 1 2 1K_0201_1% SML0_SMBCLK <64,79> PCH_RTCRST# PCH_SRTCRST# BD46 RTCRST# GPP_A13/SUSWARN#/SUSPWRDNACK
RH502 1 2 1K_0201_1% SML0_SMBDATA SRTCRST#
RH557 2 1 10K_0201_5% KB_DET# PCH_PWROK AY42 BG44 LAN_WAKE#
PCH_RSMRST#_AND PCH_PWROK GPD2/LAN_WAKE# AC_PRESENT LAN_WAKE# <58> PCH_SMB_ALERT#
BA47 BG42 4.7K_0201_5% 2 @ 1 RH505
RSMRST# GPD1/ACPRESENT AC_PRESENT <58>
+3VS BD39 SIO_SLP_SUS#_L 0_0201_5% 2 1 RH587 SIO_SLP_SUS#
SLP_SUS# BE46
PCH_DPWROK_R GPD3/PWRBTN# SYS_RESET# SIO_PWRBTN# <58,79>
<58> PCH_DPWROK_EC RH309 1 DS3@ 2 0_0402_5% AW41 AU2
SYS_RESET# <79> TLS CONFIDENTIALITY
RH463 1 2 1K_0201_5% PCH_SMBCLK PCH_SMB_ALERT# Strap Pin BE25 DSW_PWROK SYS_RESET# AW29 Strap Pin SPKR
PCH_SMBDATA MEM_SMBCLK GPP_C2/SMBALERT# GPP_B14/SPKR SPKR <56,58>
1 2 BE26 AE3
RH462
RH516 1 DIS@ 2
1K_0201_5%
10K_0201_5% DGPU_PWROK MEM_SMBDATA BF26 GPP_C0/SMBCLK CPUPWRGD H_CPUPWRGD <8> HIGH vPRO
RH599 1 2 10K_0201_5% IMVP_VR_PG SML0_ALERT#_TR Strap Pin BF24 GPP_C1/SMBDATA AL3 PCH_ITP_PMODE LOW(DEFAULT) non-vPRO
<42> SML0_ALERT#_TR SML0_SMBCLK GPP_C5/SML0ALERT# ITP_PMODE PCH_JTAGX PCH_ITP_PMODE <79>
BF25 AH4
<42> SML0_SMBCLK SML0_SMBDATA GPP_C3/SML0CLK PCH_JTAGX PCH_JTAG_TMS PCH_JTAGX <79>
<42> SML0_SMBDATA BE24 AJ4 PCH_JTAG_TMS <79>
RH91 1 @ 2 100K_0201_5% SYS_PWROK GPP_B23 Strap Pin BD33 GPP_C4/SML0DATA PCH_JTAG_TMS AH3 PCH_JTAG_TDO
SML1_SMBCLK GPP_B23/SML1ALERT#/PCHHOT# PCH_JTAG_TDO PCH_JTAG_TDI PCH_JTAG_TDO <79>
BF27 AH2
<58> SML1_SMBCLK SML1_SMBDAT GPP_C6/SML1CLK 4 OF 13 PCH_JTAG_TDI PCH_JTAG_TCK PCH_JTAG_TDI <79>
<58> SML1_SMBDAT BE27 AJ3 PCH_JTAG_TCK <79> Strap Definitions(GPP_C5 /SML0ALERT#)
GPP_C7/SML1DATA PCH_JTAG_TCK
CNP-H_BGA874 Rev1.0
RH6907 1 UMA@ 2 10K_0201_5% DGPU_PWROK Strap Definitions(ITP_PMODE) +3V_PCH
@
DVT2.1_08:EC read DGPU always high that thermal PL4 error,so it's should control by BOM optoin
RH5841 1 2 100K_0201_5% PCH_RSMRST#_AND
Add RH6907(UMA@) ,change RH516 to DIS@
SML0_ALERT#_TR 4.7K_0201_5% 2 1 RH503
RH401 1 DS3@ 2 100K_0201_5% PCH_DPWROK_R
+3VS
RH899 1 2 1M_0201_5% SIO_SLP_SUS# PCH to DDR, XDP, FFS +3VS
EC interface
1 @ 2 0.1U_0201_10V6K SIO_SLP_SUS#
CH899 HIGH ESPI
5
UH14
IMVP_VR_PG 1 LOW(DEFAULT) LPC
P
<88,99> IMVP_VR_PG B PCH_PWROK
4
2 Y
SIO_SLP_A# <58> RUNPWROK A
G
RH1152 1 2 100K_0201_5%
B B
2
QH4A TC7SH08FU_SSOP5 Strap Definitions(GPP_B23 /SML1ALERT# /PCHHOT#)
1
G1
RH529
RZ1150 1 2 100K_0201_5% SIO_SLP_S3# MEM_SMBCLK 6 1 PCH_SMBCLK 100K_0201_5% +3V_PCH
PCH_SMBCLK <23,24,79>
D1
S1
2
G2
PMDXB600UNE_DFN1010B-6
RZ1151 1 2 100K_0201_5% SIO_SLP_S4# GPP_B23 150K_0201_5% 2 1 RH504
MEM_SMBDATA 3 4 PCH_SMBDATA
PCH_SMBDATA <23,24,79>
D2
S2
75K_0201_1% 2 1 RH114 CNV_RF_RESET# PCHHOT# ( IntelR DCI-OOB )

2 1 CLKREQ_CNV# QH4B
75K_0201_1% RH728
PMDXB600UNE_DFN1010B-6 DVT2.1_11:Power sequence fix & Aligne schematic to Olympic
HIGH Enable
DVT2_12 :change RH728 from SD000016T00 to SD000010380 follow intel design guide Add Net name "EN_1.8_PRIM","EN_1.0VA" LOW(DEFAULT) Disable
Add CH54(SE00000QL10),RH702(SD043470180)
Add RH701(SD043000080),CH55(SE00000QL10) but un-pop
0_0201_5% 2 @DS3@ 1 RH699 SIO_SLP_SUS#
Reserve for EMI

RSMRST circuit
@ RH701
+3VALW 0_0201_5% PCH_PRIM_EN <77,78>
1 2
<17> VCCDSW_EN_GPIO EMC@ CH50 1 2 8.2P_0201_25V8D HDA_BITCLK
RH700 1 2 0_0201_5%
EN_1.8V_PRIM <95>
HDA_SDOUT
1
UZ123 <58> VCCDSW_EN RH6905 1 2 0_0201_5% CH55 RF@ CH51 1 2 2P_0201_25V8B
5
@ 1U_0402_10V6K
<15,58> PCH_RSMRST#_EC_R 1
P
2
4 PCH_RSMRST#_AND EMC@ CD3325 1 2 2P_0201_25V8B HDA_SYNC
ALW_PWRGD_3V_5V 2 O RH6906 1 2 0_0201_5%
<15,50,83> ALW_PWRGD_3V_5V A <15,50,83> ALW_PWRGD_3V_5V
G
RH702 1 2 4.7K_0201_5% EMC@ CD3324 1 2 2P_0201_25V8B HDA_SDIN0_AUDIO

EN_1.0VA <84>
3
TC7SH08FU_SSOP5~D RH215 1 2 0_0201_5% PCH_DPWROK_R

D
1
1
QT14 CH54
R5873 1 @ 2 200K _0201_1% PCH_RSMRST#_G 2 1U_0402_10V6K
<15,58> PCH_RSMRST#_EC_R
A G A
2
1 S 2N7002KW_SOT323-3
3
CA252
470P_0201_25V7K
RH215 2 DVT2_11 : Change CA252 from 330P to 470P to fix WDT sequence
PCH_PRIM_EN is low intervel time = 40 ms
POP NO Support Deep sleep
DE-POP Support Deep sleep EC WDT reset circuit R5873 change to unpop,EC can internal pull down
DVT2_10 : Change QT14 from SB00000ST00 to SB000009Q80 follow Olympic schematic

P015-PCH (3/7) PM,HDA,SMB,JTAG


5 4 3 2 1
5 4 3 2 1
GPD7 Strap Definitions

+3VALW
CNP-H
UH2B
2
K34 J3
<6> DMI_CTX_PRX_N0 DMI0_RXN USB2N_1
<6> DMI_CTX_PRX_P0 J35 J2 RZ38 100K_0201_5%
C33 DMI0_RXP USB2P_1 N13
<6> DMI_CRX_PTX_N0 DMI0_TXN USB2N_2
<6> DMI_CRX_PTX_P0 B33 N15
D
G33 DMI0_TXP USB2P_2 K4 D
<6> DMI_CTX_PRX_N1 DMI1_RXN USB2N_3 USB20_N3 <48,51> 3.3V_CAM_EN#
1
F34 K3 Type-C Port C(CG5_L Port)
<6> DMI_CTX_PRX_P1 DMI1_RXP USB2P_3 USB20_P3 <48,51>
<6> DMI_CRX_PTX_N1 C32 M10 USB20_N4 <44>
B32 DMI1_TXN USB2N_4 L9 Rising edge of DSW_PWROK
<6> DMI_CRX_PTX_P1
K32 DMI1_TXP USB2P_4 M1
USB20_P4 <44> Type-C Port A (CCG5_R_Port1) External pull-up is required
<6> DMI_CTX_PRX_N2 DMI2_RXN USB2N_5 USB20_N5 <44>
J32 L2 Type-C Port B (CCG5_R_Port2)
<6> DMI_CTX_PRX_P2 DMI2_RXP USB2P_5 USB20_P5 <44>
C31 K7
<6> DMI_CRX_PTX_P2 B31 K6
G30 DMI2_TXP USB2P_6 L4
<6> DMI_CTX_PRX_N3 DMI3_RXN USB2N_7
<6> DMI_CTX_PRX_P3 F30 L3
C29 DMI3_RXP USB2P_7 G4
B29 G5
<6> DMI_CRX_PTX_P3 DMI3_TXP USB2P_8
A25 M6
B25 RSVD USB2N_9 N8
P24 RSVD USB2P_9 H3
RSVD USB2N_10 USB20_N10 <66>
R24 H2 Finger Print model
RSVD USB2P_10 USB20_P10 <66> +3V_PCH
C26 R10
RSVD USB2N_11 USB20_N11 <38>
B26 P9 USB20_P11 <38> RGB Camera
F26 RSVD USB2P_11 G1
G26 RSVD USB2N_12 G2
B27 RSVD USB2P_12 N3
C27 RSVD USB2N_13 N2
L26 RSVD USB2P_13 E5 TBT_WAKE# RH5898 1 2 10K_0201_5%
RSVD USB2N_14 USB20_N14 <52> USB_OC3#
M26 F6 RH555 1 2 10K_0201_5%
RSVD USB2P_14 USB20_P14 <52>WLAN.CNVi USB_OC4#
D29 RH554 1 2 10K_0201_5%
E28 RSVD AH36 USB_OC0# USB_OC5# RH553 1 2 10K_0201_5%
K29 RSVD GPP_E9/USB2_OC0# AL40 USB_OC1# USB_OC6# RH552 1 2 10K_0201_5%
M29 RSVD GPP_E10/USB2_OC1# AJ44 USB_OC2#
RSVD GPP_E11/USB2_OC2# AL41 USB_OC3#
GPP_E12/USB2_OC3# USB_OC4# USB_OC3# <48>
G17 AV47 USB_OC4# <44>
<42> PCIE_PRX_TTX_N1 PCIE1_RXN/USB31_7_RXN GPP_F15/USB2_OC4# USB_OC5#
F16 AR35
<42> PCIE_PRX_TTX_P1 PCIE1_RXP/USB31_7_RXP GPP_F16/USB2_OC5# USB_OC6# USB_OC5# <44>
A17 AR37
<42> PCIE_PTX_TRX_N1 B17 PCIE1_TXN/USB31_7_TXN GPP_F17/USB2_OC6# AV43 USB_OC7# +3V_PCH
<42> PCIE_PTX_TRX_P1 R21 PCIE1_TXP/USB31_7_TXP GPP_F18/USB2_OC7# RP8
<42> PCIE_PRX_TTX_N2 PCIE2_RXN/USB31_8_RXN USB2_COMP USB_OC0#
P21 F4 RH109 1 2 113_0201_1% 4 5
<42> PCIE_PRX_TTX_P2 PCIE2_RXP/USB31_8_RXP USB2_COMP USB2_VBUSSENSE RH580 1 USB_OC1#
B18 F3 2 0_0201_5% 3 6
<42> PCIE_PTX_TRX_N2 C18 PCIE2_TXN/USB31_8_TXN USB2_VBUSSENSE U13 PBRSVD1 T4964 PAD~D TP@ USB_OC2# 2 7
<42> PCIE_PTX_TRX_P2 K18 PCIE2_TXP/USB31_8_TXP RSVD1 G3 RH581 1 2 0_0201_5% USB_OC7# 1 8
C TR TBT Port1 <42> PCIE_PRX_TTX_N3 PCIE3_RXN/USB31_9_RXN USB2_ID
C
J18
<42> PCIE_PRX_TTX_P3 PCIE3_RXP/USB31_9_RXP 3.3V_CAM_EN#
B19 BE41 Strap Pin 10K_0804_8P4R_5%
<42> PCIE_PTX_TRX_N3 C19 PCIE3_TXN/USB31_9_TXN GPD7
<42> PCIE_PTX_TRX_P3 N18 PCIE3_TXP/USB31_9_TXP G45
<42> PCIE_PRX_TTX_N4 PCIE4_RXN/USB31_10_RXN PCIE24_TXP
R18 G46
<42> PCIE_PRX_TTX_P4 D20 PCIE4_RXP/USB31_10_RXP PCIE24_TXN Y41
<42> PCIE_PTX_TRX_N4 C20 PCIE4_TXN/USB31_10_TXN PCIE24_RXP Y40
<42> PCIE_PTX_TRX_P4 F20 PCIE4_TXP/USB31_10_TXP PCIE24_RXN G48
G20 PCIE5_RXN PCIE23_TXP G49
B21 PCIE5_RXP PCIE23_TXN W44 Xtal input
A22 PCIE5_TXN PCIE23_RXP W43
K21 PCIE5_TXP PCIE23_RXN H48
<52>
<52>
PCIE_PRX_DTX_N7
PCIE_PRX_DTX_P7
J21 PCIE6_RXN PCIE22_TXP H47 HIGH(DEFAULT) dif f er ent ial
M.2 1216 Wlan <52> PCIE_PTX_DRX_N7
D21
C21
PCIE6_RXP
PCIE6_TXN
PCIE22_TXN
PCIE22_RXP
U41
U40
LOW single-end
<52> PCIE_PTX_DRX_P7 PCIE6_TXP PCIE22_RXN
B23 F46
<70> PCIE_PTX_DRX_P6 PCIE7_TXP PCIE21_TXP
<70> PCIE_PTX_DRX_N6 C23 G47 0628
J24 PCIE7_TXN PCIE21_TXN R44 CFL CRB rev0.5
CARD_READER <70> PCIE_PRX_DTX_P6 PCIE7_RXP PCIE21_RXP Xtal input
L24 T43
<70> PCIE_PRX_DTX_N6 PCIE7_RXN PCIE21_RXN High : differential
F24 Low : single-end
G24 PCIE8_RXN CNL- PCH EDS rev0.5
B24 PCIE8_RXP External pull-up is required. Recommend 100K if pulled
C24 PCIE8_TXN 2 OF 13 up to 3.3V
PCIE8_TXP
CNP-H_BGA874 Rev1.0
@
+3.3V_1.8V_ESPI
SIO_RCIN# RH518 1 2 10K_0201_5%
CNP-H
UH2F DVT1.1_ : DVT1.1_ : change net name +3.3V_1.8V_ESPI
F9 BB39 ESPI_IO0_R RC5831 1 2 15_0201_1% ESPI_CLK to ESPI_CLK_1P8
<47> USB3_CTX_DRX_N1 USB31_1_TXN GPP_A1/LAD0/ESPI_IO0 ESPI_IO1_R ESPI_IO0_1P8 <58,79> ESPI_CS# to ESPI_CS#_1P8
F7 AW37 RC5832 1 2 15_0201_1% ESPI_IO0 to ESPI_IO0_1P8
<47> USB3_CTX_DRX_P1 USB31_1_TXP GPP_A2/LAD1/ESPI_IO1 ESPI_IO2_R ESPI_IO1_1P8 <58,79> ESPI_ALERT#
USB3.0 DP MX (PS8802) <47> USB3_CRX_DTX_N1 D11 AV37 RC5833 1 2 15_0201_1% ESPI_IO2_1P8 <58,79> ESPI_IO1 to ESPI_IO1_1P8 RH1943 1 2 8.2K_0201_1%
B
C11 USB31_1_RXN GPP_A3/LAD2/ESPI_IO2 BA38 ESPI_IO3_R RC5834 1 2 15_0201_1% ESPI_IO2 to ESPI_IO2_1P8 B
<47> USB3_CRX_DTX_P1 USB31_1_RXP GPP_A4/LAD3/ESPI_IO3 ESPI_IO3_1P8 <58,79> ESPI_IO3 to ESPI_IO3_1P8
USB3_PTX_DRX_N2 C3
USB3_PTX_DRX_P2 D4 USB31_2_TXN BE38 ESPI_CS#_1P8 ESPI_RESET# RH5838 1 @ 2 10K_0201_5%
USB3_PRX_DTX_N2 USB31_2_TXP GPP_A5/LFRAME#/ESPI_CS0# IRQ_SERIRQ ESPI_CS#_1P8 <58,79>
B9 AW35 RH5882 1 @ 2 0_0201_5% ESPI_ALERT# <58>
USB3_PRX_DTX_P2 C9 USB31_2_RXN GPP_A6/SERIRQ/ESPI_CS1# BA36 ESPI_ALERT#_R RH5883 1 2 0_0201_5%
USB31_2_RXP GPP_A7/PIRQA#/ESPI_ALERT0# BE39 SIO_RCIN#
C17 GPP_A0/RCIN#/ESPI_ALERT1# BF38 ESPI_RESET#_R RH5839 1 2 0_0201_5% ESPI_RESET#
USB31_6_TXN GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RESET# <58>
C16
G14 USB31_6_TXP BB36 ESPI_CLK RH168 1 2 15_0201_1%
USB31_6_RXN GPP_A9/CLKOUT_LPC0/ESPI_CLK PCI_CLK_LPC1 ESPI_CLK_1P8
PCI_CLK_LPC1_R <58,79>
F14 BB34 RH428 1 @ 2 22_0201_1%
C15 USB31_6_RXP GPP_A10/CLKOUT_LPC1 T4945 PAD~D TP@
B15 USB31_5_TXN T48 TBT_PWR_EN T5990 PAD~D TP@
+5VALW J13 USB31_5_TXP GPP_K19/SMI# T47 TBT_WAKE# Follow Intel RVP for TBT RTD3 ESPI_CLK_1P8
USB31_5_RXN GPP_K18/NMI# TBT_WAKE# <42>
JWIND K13
1 USB31_5_RXP
1 1
2 G12 AH40
2 3 F11 USB31_3_TXP GPP_E6/SATA_DEVSLP2 AH35 @ CH198
3 USB31_3_TXN GPP_E5/SATA_DEVSLP1 M2280A_DEVSLP <68>
4 C10 AL48 15P_0201_25V8J
4 5 B10 USB31_3_RXP GPP_E4/SATA_DEVSLP0 AP47 2
5 USB3_PTX_C_DRX_P2 CT565 1 USB3_PTX_DRX_P2 USB31_3_RXN GPP_F9/SATA_DEVSLP7 SSD Port1 SATA1A
6 2 0.22U_0201_6.3V6K AN37
6 7 USB3_PTX_C_DRX_N2 CT567 1 2 0.22U_0201_6.3V6K USB3_PTX_DRX_N2 C14 GPP_F8/SATA_DEVSLP6 AN46
7 8 B14 USB31_4_TXP GPP_F7/SATA_DEVSLP5 AR47
SSD Port2 SATA4
M2280B_DEVSLP <69>
RF Reserved.
8 9 USB3_PRX_DTX_P2 J15 USB31_4_TXN GPP_F6/SATA_DEVSLP4 AP48 LCD_DBC +3VS
9 USB3_PRX_DTX_N2 USB31_4_RXP 6 OF 13 GPP_F5/SATA_DEVSLP3
LCD_DBC <38>
10 K16
10 USB31_4_RXN
CNP-H_BGA874 Rev1.0
11 LCD_DBC RH527 1 @ 2 10K_0201_5%
GND1 @
12
GND2
RH528 1 2 10K_0201_5%
ACES_50521-01041-P01
CONN@
A A

P016-PCH (4/7) DMI,PCIE,USB,LPC


5 4 3 2 1
5 4 3 2 1
CNP-H
UH2K GPIO_D11=DCI_CLK
BBS_BIT6 Strap Pin BA26 BA20 GPIO_D12=DCI_DAT +3VS
+3VS BD30 GPP_B22/GSPI1_MOSI GPP_D9/ISH_SPI_CS#/GSPI2_CS0# BB20
<77> PCH_3.3V_TS_EN SIO_EXT_SCI# GPP_B21/GSPI1_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK DGPU_HOLD_RST# <27>
AU26 BB16
SIO_EXT_SCI# PCH_BT_RADIO_DIS# GPP_B20/GSPI1_CLK GPP_D11/ISH_SPI_MISO/GP_BSSB_CLK/GSPI2_MISO DCI_CLK <47> P_SENSOR_PWR_SAVE# RH102 1
RH383 1 2 10K_0201_5% <52> PCH_BT_RADIO_DIS# AW26 AN18 2 10K_0201_5%
1 2 49.9K_0201_1% UART2_TXD GPP_B19/GSPI1_CS0# GPP_D12/ISH_SPI_MOSI/GP_BSSB_DI/GSPI2_MOSI DCI_DATA <47>
RH561
RH562 1 2 49.9K_0201_1% UART2_RXD NRB_BIT Strap Pin BE30 BF14 BID_GPU +3VS_Hinge
BD29 GPP_B18/GSPI0_MOSI GPP_D16/ISH_UART0_CTS#/CNV_WCEN AR18 BID_BC
<66> TPM_PIRQ# GPP_B17/GSPI0_MISO GPP_D15/ISH_UART0_RTS#/GSPI2_CS1#/CNV_WFEN P_DET# P_DET#
BF29 BF17 RH688 1 2 10K_0201_5%
MEDIACARD_IRQ# GPP_B16/GSPI0_CLK GPP_D14/ISH_UART0_TXD/I2C2_SCL P_SENSOR_PWR_SAVE# P_DET# <38>
BB26 BE17
<55> MEDIACARD_IRQ# GPP_B15/GSPI0_CS0# GPP_D13/ISH_UART0_RXD/I2C2_SDA P_SENSOR_PWR_SAVE# <38>
BB24
D <79> SBIOS_TX PCH_GPP_C8 GPP_C9/UART0A_TXD D
BE23
TP@ PAD~D T6014 PCH_GPP_C11 AP24 GPP_C8/UART0A_RXD +3VS
TP@ PAD~D T4988 PCH_GPP_C10 GPP_C11/UART0A_CTS#
BA24 GPP_H Group 3.3V
TP@ PAD~D T4989 GPP_C10/UART0A_RTS# AG45
CORE_ID BD21 GPP_H20/ISH_I2C0_SCL AH46 ISH_I2C1_SCL RH19 1 2 1K_0201_5%
CPU_ID AW24 GPP_C15/UART1_CTS#/ISH_UART1_CTS# GPP_H19/ISH_I2C0_SDA ISH_I2C1_SDA RH20 1 2 1K_0201_5%
PCH_GPP_C13 AP21 GPP_C14/UART1_RTS#/ISH_UART1_RTS# AH47 ISH_I2C1_SCL
TP@ PAD~D T6013 SIO_EXT_WAKE# GPP_C13/UART1_TXD/ISH_UART1_TXD GPP_H22/ISH_I2C1_SCL ISH_I2C1_SDA ISH_I2C1_SCL <38,59>
AU24 AH48 ALS Accelerometer
GPP_C12/UART1_RXD/ISH_UART1_RXD GPP_H21/ISH_I2C1_SDA ISH_I2C1_SDA <38,59> +1.8VS_AUDIO
<52> WAKE_BT AV21
AW21 GPP_C23/UART2_CTS#
<52> UART_WAKE_HOST UART2_TXD GPP_C22/UART2_RTS# ISH_ALS_INT#_R
BE20 GPP_A Group 1.8V AV34
<44> UART2_TXD UART2_RXD GPP_C21/UART2_TXD GPP_A23/ISH_GP5 ISH_P_SENSOR_INT#_R ISH_ALS_INT#_R
<44> UART2_RXD BD20 AW32 RH99 1 2 10K_0201_5%
+3V_PCH GPP_C20/UART2_RXD GPP_A22/ISH_GP4 BA33 ISH_ACC_INT#_R ISH_P_SENSOR_INT#_RRH101 1 2 10K_0201_5%
BE21 GPP_A21/ISH_GP3 BE34 ISH_ACC_INT#_R RH355 1 2 10K_0201_5%
PCH_BT_RADIO_DIS# <59> I2C1_SCK_TP GPP_C19/I2C1_SCL GPP_A20/ISH_GP2
RH6904 1 2 10K_0201_5%
<59> I2C1_SDA_TP
BF21 BD34
BC22 GPP_C18/I2C1_SDA GPP_A19/ISH_GP1 BF35 PCH_GPP_A18
<38> I2C0_SCK_TS GPP_C17/I2C0_SCL GPP_A18/ISH_GP0 T124 PAD~D TP@
<38> I2C0_SDA_TS BF23 BD38
GPP_C16/I2C0_SDA GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
RH523 1 2 10K_0201_5% SIO_EXT_WAKE# <42> TBT_FORCE_PWR BE15

BE14 GPP_D4/ISH_I2C2_SDA/I2C3_SDA/SBK4_BK4
11 OF 13 X00:add ISH_I2C signal
GPP_D23/ISH_I2C2_SCL/I2C3_SCL +3V_PCH
CNP-H_BGA874 Rev1.0
MEDIACARD_IRQ# RH546 1 2 10K_0201_5%

Strap Definitions(GPP_B22 /GSPI1_MOSI)
+3V_PCH
DVT2.1_03 : Change QH1,QRTC from SB00000T900 to SB00000SS00 for ESD improve RH130 1 @ 2 4.7K_0201_5% BBS_BIT6
+3V_PCH_DSW +3V_PCH +3VALW
DE225 1 2 ISH_ALS_INT#_R
<38> ISH_ALS_INT#
RB520SM-30T2R_EMD2-2
C
0_0201_5% 2 @ 1 RH5864 DE226 1 2 ISH_P_SENSOR_INT#_R Boot BIOS Strap Bit (internal PD) C
<38> ISH_P_SENSOR_INT#
@ RB520SM-30T2R_EMD2-2 HIGH LPC
QH1 DE227 1 2 ISH_ACC_INT#_R LOW(DEFAULT) SPI
NTK3139PT1G_SOT723-3 <59> ISH_ACC_INT#
0_0201_5% 2 @ 1 RH5865 +3V_PCH_DSW_RR1 3

D
Strap Definitions(GPP_B18 /GSPI0_MOSI)

G
2
R5832 +3V_PCH
@ 499K_0201_1% RH5867
@ RH524 1 @ 2 4.7K_0201_5% NRB_BIT
100K_0201_5%
2
DVT2_10 : Del RH5867 pull high follow Olympic schematic

NO REBOOT mode (internal PD)
1
RH5868 HIGH ENABLE

@ 49.9K_0201_1%
LOW(DEFAULT) DISABLE
2
QE20
D
1
@ 2N7002KW_SOT323-3
2
G VCCDSW_EN_GPIO <15>
S
3
B B
+3V_PCH +3V_PCH
+3V_PCH +3V_PCH +3V_PCH

1
RH5875 RH5896
100K_0201_5% 100K_0201_5%
1
@ @
RH564 RH566 RH5857
2
@ 100K_0201_5% @ 100K_0201_5% @ 100K_0201_5%

CPU_ID CORE_ID
2
BID_DIS BID_BC BID_GPU

1
BID_DIS <14,58>
RH5876 RH5897
100K_0201_5% 100K_0201_5%
1
@ @
RH565 RH567 RH5858
2
DIS@ 100K_0201_5% @ 100K_0201_5% @ 100K_0201_5%

2
SYSTEM ID 3 (VR) SYSTEM ID 4 (VR)

HIGH =4PHASE HIGH =8+2 core
LOW =3PHASE LOW = 6+2 core & other
A A
CPU_ID CORE_ID SYSTEM SKU

L L 3PHASE-I5
L H NA
H L 4PHASE-6+2
H H 4PHASE-8+2 Security Classification Compal Secret Data Compal Electronics, Inc.
P017-PCH (5/7) I2C,GPIO


5 4 3 2 1
5 4 3 2 1
CNP-H
+1VALW +1V_PCH_CLK5 +1VALW UH2H +3V_PCH
5.95A AA22 AW9 0.182A
AA23 VCCPRIM_1P051 VCCPRIM_3P32
AB20 VCCPRIM_1P052 BF47
VCCPRIM_1P053 DCPRTC1 +DCPRTC
LH4 1 2 CPI160809UF_2P AB22 BG47
VCCPRIM_1P054 DCPRTC2
0.1U_0201_6.3V6K
AB23 +3V_PCH +3V_USB2
DVT1.1_12 : change footprint from AB27 VCCPRIM_1P055 V23 0.095A
VCCPRIM_1P056 VCCPRIM_3P35 1
MURAT_BLM18EG221TN1D_2P to AB28
CH3331
+3V_PCH +3V_PCH_SPI
CHILI_PBY160808T-300Y-N_2P. VCCPRIM_1P057
AB30 AN44 0.042A
AD20 VCCPRIM_1P058 VCCSPI
AD23 VCCPRIM_1P059 BC49 2
VCCPRIM_1P0510 VCCRTC1 +RTCVCC
AD27 BD49
+1VALW +1V_MPHY_MPHYPLL AD28 VCCPRIM_1P0511 VCCRTC2 +3V_PCH +3V_PCH_PRIM
AD30 VCCPRIM_1P0512 AN21 0.195A +3V_PCH +3V_PHVLDO
AF23 VCCPRIM_1P0513 VCCPGPPG_3P3 AY8 0.97A
AF27 VCCPRIM_1P0516 VCCPRIM_3P33 BB7
D
LH3 1 2 0_0603_5% +1V_MPHY +1VALW AF30 VCCPRIM_1P0517 VCCPRIM_3P34 +3V_PCH +3V_1.8V_PGPPHK D
VCCPRIM_1P0518 AC35 0.262A
6.66A U26 VCCPGPPHK1 AC36 +3V_PCH +3V_1.8V_PGPPEF
U29 VCCPRIM_1P0523 VCCPGPPHK2 AE35 0.174A
V25 VCCPRIM_1P0524 VCCPGPPEF1 AE36
V27 VCCPRIM_1P0525 VCCPGPPEF2 +3V_PCH +3V_1.8V_PGPPD
V28 VCCPRIM_1P0526 AN24 0.14A
+1VALW +1V_PCH_AZPLL V30 VCCPRIM_1P0527 VCCPGPPD AN26
+VCCPRIM_FUSE_1P05 +1VALW V31 VCCPRIM_1P0528 VCCPGPPBC1 AP26 0.334A
+1VALW VCCPRIM_1P0529 VCCPGPPBC2 +3.3V_1.8V_ESPI
0.0012A AD31 AN32 0.101A
LH2 1 2 0_0402_5% VCCPRIM_1P0514 VCCPGPPA +3V_PCH +3V_PCH_PRIM
RH5856 1 2 0_0402_5% +1V_PCH_CNVI 0.2A AE17 AT44 0.106A +3V_PCH +3V_PCH_PRIM
+1V_PCH_USBPLL VCCPRIM_1P0515 VCCPRIM_3P31 BE48 0.113A
+1VALW 0.42A W22 VCCDSW_3P31 BE49
1 1 VCCDUSB_1P051 VCCDSW_3P32
EMC@ EMC@ W23 +1.8V_PCH_AZIO
CH3323 CH3322 +1V_VCCDSW VCCDUSB_1P052 BB14 0.00767A +1.8VALW +1.8V_PRIM
2P_0201_25V8B 2P_0201_25V8B BG45 VCCHDA AG19 0.766A
2 2 +VCCCLPLLEBB_1P05 +1VALW BG46 VCCDSW_1P051 VCCPRIM_1P83 AG20
0.109A W31 VCCDSW_1P052 VCCPRIM_1P84 AN15
+1V_PCH_AZPLL VCCPRIM_MPHY_1P05 VCCPRIM_1P85 AR15
0.015A D1 VCCPRIM_1P86 BB11
E1 VCCPRIM_1P0521 VCCPRIM_1P87 +1.8VALW +1.8V_PCH_LDO
+1V_MPHY_MPHYPLL +1V_MPHY_MPHYPLL 0.213A C49 VCCPRIM_1P0522 AF19 0.882A +1.8V_PCH_LDO RH5880 1 @ 2 0_0402_5%
D49 VCCAMPHYPLL_1P051 VCCPRIM_1P81 AF20
E49 VCCAMPHYPLL_1P052 VCCPRIM_1P82 +1VALW +1V_PCH
+1V_PCH_CLK5 +1V_PCH_CLK5 VCCAMPHYPLL_1P053 AG31 0.193A +1VALW +1V_PCH
0.00428A P2 VCCPRIM_1P0520 AF31 0.0859A +1.25V_LDOSRAM
+VCCA_SRC_1P05 +1VALW P3 VCCA_XTAL_1P051 VCCPRIM_1P0519 AK22 T5003 PAD~D TP@
0.169A W19 VCCA_XTAL_1P052 VCCPRIM_1P241 AK23
W20 VCCA_SRC_1P051 VCCPRIM_1P242 +1.25V_DPHY_MAR
+VCCA_BCLKPLL2_1P05 +1VALW VCCA_SRC_1P052 AJ22 T5004 PAD~D TP@
0.0198A C1 VCCDPHY_1P241 AJ23
+VCCA_OC_1P05 +1VALW C2 VCCAPLL_1P054 VCCDPHY_1P242 BG5
0.0085A V19 VCCAPLL_1P055 VCCDPHY_1P243
VCCA_BCLK_1P05 +3V_PCH_AZIO change to +1.8V_PCH_AZIO
+VCCA_BCLKPLL2_1P05 +1VALW K47 VCCMPHY_SENSE T4943 PAD~D TP@
0.021A B1 VCCMPHY_SENSE K46 VSSMPHY_SENSE T4944 PAD~D TP@ AMP_TAS2770 GPIO level is 1.8V
B2 VCCAPLL_1P051 VSSMPHY_SENSE Need change the PCH power level(3.3V to 1.8V)
C C
B3 VCCAPLL_1P052 8 OF 13
VCCAPLL_1P053
CNP-H_BGA874 Rev1.0
@ +1.8V_PCH_AZIO +1.8VALW
Close to ball name

+1V_PCH_AZPLL LH5 1 2 0_0402_5%
D1, E1
+1.25V_DPHY_MAR
+1.25V_LDOSRAM +1.25V_DPHY_MAR 1 1
4.7U_0402_6.3V6M
EMC@ EMC@
22U_0402_6.3V6M
22U_0402_6.3V6M
1 1 1 RH5879 1 2 0_0402_5% CH3320 CH3326
4.7U_0402_6.3V6M
2P_0201_25V8B 2P_0201_25V8B
CH203
1
2 2
CH330
CH331
+1.8VALW +3.3V_1.8V_ESPI
CA131
2 2 2
2
RH597 1 2 0_0402_5%
4.7uF close to BG5
+RTCVCC +1VALW
+3V_1.8V_PGPPEF
+1VALW +1.8V_PCH_AZIO 20170614 +1V_PCH_CLK5
+1V_VCCDSW Close to ball name
+3V_PHVLDO +1V_PCH_CLK5 AE35 , AE36
0613 0613 intel review 0613 Intel review Close ball name P2 , P3
Close to ball name +VCCA_BCLKPLL2_1P05 Close to net name Close to ball name 1x 0.1uF 0402 3mm
To add 1x 1uF 0603, 3mm
0.1U_0201_10V6K
Close to ball name BC49, BD49 Intel review +1V_PCH_PRIM BB14 (placeholder)
BG45, BG46 Close to ball name AY8, BB7
1U_0402_10V6K
1x 0.1uF 0402, 3mm Close to ball name 1uF 0402 capacitor 1uF 0402 capacitor
1U_0201_6.3V6M
CH200
1 1
1x 1uF 0402
1
1x 1uF 0402, 5mm

1U_0201_6.3V6M
0.1U_0201_10V6K
+3V_PCH
1 B1, B2, B3, C1, C2 +3V_PCH
CH176
1U_0201_6.3V6M
1U_0201_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
CH207
1 1 1 1 1
B 1uF 0402 capacitor B
CH3329
CH70
CH177
CH178
@
2
2 2
CH80
CH179
2
2 2 2 2 2
0.1U_0201_10V6K
1
1U_0201_6.3V6M
1
CH192
@
CH187
2
2
+1.8VALW +1V_MPHY_MPHYPLL
+1VALW +1VALW
+1V_MPHY 20170613
20170614 Intel review Close to ball name +1V_MPHY_MPHYPLL
To add 1x 1uF, 0402 U26,U29,V25, Intel review Close to ball name
on +1.8V_PCH. AF31, AG31, AD31, AA22, 20170614 +3V_1.8V_PGPPD
V27,V28,V30,V31 To change close ball name. +3V_PCH_DSW Close to ball name
AA23, AB20, AB22, AB23,
1U_0201_6.3V6M
1 1x 1uF 0402, 3mm Close to ball name

1U_0402_10V6K
AB27, AB28, AB30, AD20, Intel review AN24

1x 22uF 0805, 5mm C49,D49,E49
1
To add 1x 0.1uF 0402, 3mm 1x 0.1uF 0402 3mm

1U_0201_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
CH205
1 1 1
1x 1uF 0402, 3mm AD23, AD27, AD28, AD30,
CH206
22U_0402_6.3V6M
1U_0201_6.3V6M
CH181
CH182
2 1 1
AF23, AF27, AF30, AE17, 3mm Close to ball name BE48, BE49 (placeholder)
CH180
2
CH184
CH183
2 2 2 +3V_PCH +3V_PCH +3VS +3V_PCH

2 2
0.1U_0201_10V6K
0.1U_0201_10V6K
1U_0201_6.3V6M
0.1U_0201_10V6K
1 1 1 1
CH82
CH204
CH188
CH191
@
2 2 2 2
+1.8VALW +3V_PCH +3V_PCH +1VALW

+1.8V_PRIM +3V_1.8V_PGPPEF
A
Close to ball name Close to ball name +3V_1.8V_PGPPHK 0619 A
AG19, AG20, AR15, AN15, BB11 AE35, AE36 Close to ball name +1V_PCH_USBPLL
1x 4.7uF 0603, 3mm 1x 0.1uF 0402, 3mm AC35, AC36 EMI require 100nF
1x 0.1uF 0402 3mm Close to W22,W23 for EMI require
0.1U_0201_10V6K
4.7U_0402_6.3V6M
CH92
1 Option 1: Internal LDO 1 (placeholder)

4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
1x 1uF 0402, 3mm (placeholder)

0.1U_0201_10V6K
0.1U_0201_10V6K
CH190
1 1 1 1
Option 2: External VRM
CH201
CH202
2 2
CH189
CH3324
2 2 2 2
P018-PCH (6/7) PWR


5 4 3 2 1
5 4 3 2 1
CNP-H CNP-H
UH2I UH2L
A2 AL12
A28 VSS VSS AL17 BG3 M24
A3 VSS VSS AL21 BG33 VSS VSS M32
D A45 VSS VSS AL33 C12 VSS VSS N12 D
A46 VSS VSS AL38 C25 VSS VSS N16
A47 VSS VSS AM1 C30 VSS VSS N34
AA19 VSS VSS AN12 D12 VSS VSS P26
AA28 VSS VSS AP4 D33 VSS VSS R12
AA30 VSS VSS AP46 D8 VSS VSS R16
AA31 VSS VSS AR12 E10 VSS VSS R26
AB19 VSS VSS AR38 E17 VSS VSS R34
AB25 VSS VSS AT1 E19 VSS VSS R38 CNP-H
AB31 VSS VSS AT16 E22 VSS VSS R4 UH2J
AC12 VSS VSS AT18 E24 VSS VSS T17 Y14 PJRSVD7 T4953 PAD~D TP@
AC17 VSS VSS AT21 E26 VSS VSS T18 RSVD7 Y15 PJRSVD8 T4954 PAD~D TP@
AC33 VSS VSS AT24 E31 VSS VSS T32 RSVD8 U37 PJRSVD6 T4955 PAD~D TP@
AC38 VSS VSS AT26 E33 VSS VSS T4 RSVD6 U35 PJRSVD5 T4956 PAD~D TP@
AC4 VSS VSS AT29 E35 VSS VSS T49 RSVD5
AC46 VSS VSS AT32 E40 VSS VSS T5 N32 PJRSVD3 T4957 PAD~D TP@
AD1 VSS VSS AT34 E42 VSS VSS T7 RSVD3 R32 PJRSVD4 T4958 PAD~D TP@
AD19 VSS VSS AT45 E8 VSS VSS U12 RSVD4
AD2 VSS VSS AV11 F41 VSS VSS U15 AH15 PJRSVD2 T4959 PAD~D TP@
AD22 VSS VSS AV39 F43 VSS VSS U17 RSVD2 AH14 PJRSVD1 T4960 PAD~D TP@
AD25 VSS VSS AW10 F47 VSS VSS U21 RSVD1
AD49 VSS VSS AW4 G44 VSS VSS U24
AE12 VSS VSS AW40 G6 VSS VSS U33
AE33 VSS VSS AW46 H8 VSS VSS U38 AL2
C VSS VSS VSS VSS PREQ# XDP_PREQ# <8,79> C
AE38 B47 J10 V20 AM5
VSS VSS VSS VSS PRDY# XDP_PRDY# <8,79>
AE4 B48 J26 V22 AM4
VSS VSS VSS VSS CPU_TRST# CPU_XDP_TRST# <8,79>
AE46 B49 J29 V4 AK3
VSS VSS VSS VSS TRIGGER_OUT PCH_TRIGGER <8>
AF22 BA12 J4 V46 AK2
VSS VSS VSS VSS TRIGGER_IN CPU_TRIGGER <8>
AF25 BA14 J40 W25
AF28 VSS VSS BA44 J46 VSS VSS W27 10 OF 13
AG1 VSS VSS BA5 J47 VSS VSS W28 CNP-H_BGA874 Rev1.0
AG22 VSS VSS BA6 J48 VSS VSS W30
VSS VSS VSS VSS @
AG23 BB41 J9 Y10
AG25 VSS VSS BB43 K11 VSS VSS Y12
AG27 VSS VSS BB9 K39 VSS VSS Y17
AG28 VSS VSS BC10 M16 VSS VSS Y33
AG30 VSS VSS BC13 M18 VSS VSS Y38
AG49 VSS VSS BC15 M21 VSS 12 OF 13 VSS Y9
AH12 VSS VSS BC19 VSS VSS
AH17 VSS VSS BC24 Rev1.0
VSS VSS CNP-H_BGA874
AH33 BC26
AH38 VSS VSS BC31 @
AJ19 VSS VSS BC35
AJ20 VSS VSS BC40
AJ25 VSS VSS BC45
AJ27 VSS VSS BC8
AJ28 VSS VSS BD43
AJ30 VSS VSS BE44
AJ31 VSS VSS BF1
AK19 VSS VSS BF2
AK20 VSS VSS BF3
AK25 VSS VSS BF48
AK27 VSS VSS BF49
AK28 VSS VSS BG17
AK30 VSS VSS BG2
AK31 VSS VSS BG22
B AK4 VSS VSS BG25 B
AK46 VSS 9 OF 13 VSS BG28
VSS VSS
Rev1.0
CNP-H_BGA874
@
A A

P019-PCH (7/7) VSS

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
DELL CONFIDENTIAL/PROPRIETARY
P020-Reserve
0.4(X03)
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P021-Reserve
0.4(X03)
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P022-Reserve
0.4(X03)
5 4 3 2 1
5 4 3 2 1
<7> DDR_A_D[0..63]
<7> DDR_A_MA[0..13] JDIMM1
+1.2V_DDR JP?
<7> DDR_A_DQS#[0..7] +1.2V_DDR
<7> DDR_A_DQS[0..7]
1 2
<7> DDR_A_CB[0..7] DDR_A_D5 VSS1 VSS2 DDR_A_D4
Layout Note: Layout Note: 3 4
5 DQ5 DQ4 6
Place near JDIMM1.257,259 Place near JDIMM1.258 DDR_A_D1 7 VSS3 VSS4 8 DDR_A_D0
9 DQ1 DQ0 10
DDR_A_DQS#0 11 VSS5 VSS6 12
DDR_A_DQS0 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_A_D6
DDR_A_D7 17 VSS8 DQ6 18
+2.5V_MEM +0.6VS 19 DQ7 VSS9 20 DDR_A_D2
DDR_A_D3 21 VSS10 DQ2 22
Layout Note: DQ3 VSS11 DDR_A_D12
23 24
Place near JDIMM1.255 DDR_A_D13 25 VSS12 DQ12 26
D 27 DQ13 VSS13 28 DDR_A_D8
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
D
DDR_A_D9 VSS14 DQ8
1U_0201_6.3V6M
29 30
10U_0402_6.3V6M
10U_0402_6.3V6M
100P_0201_50V8J
1U_0201_6.3V6M DQ9 VSS15 DDR_A_DQS#1
1U_0201_6.3V6M
31 32
100P_0201_50V8J
RF@ CD111
1 1 1 1 1 VSS16 DQS1_c DDR_A_DQS1
33 34
RF@ CD113
CD12
CD13
CD14
CD15
1 1 1 1 1 DM1_n/DBI_n DQS1_t
35 36
CD9
CD10
CD3
CD4
DDR_A_D15 37 VSS17 VSS18 38 DDR_A_D14
2 2 2 2 2 +3VS 39 DQ15 DQ14 40
2 2 2 2 2 DDR_A_D10 41 VSS19 VSS20 42 DDR_A_D11
43 DQ10 DQ11 44
47 DQ21 DQ20 48
.1U_0402_16V7K
100P_0201_50V8J
51 DQ17 DQ16 52
2.2U_0402_6.3V6M
RF@ CD112
1 1 1 DDR_A_DQS#2 VSS25 VSS26
53 54
CD16
CD17
CD113 RF request CD111 RF request DDR_A_DQS2 55 DQS2_c DM2_n/DBI2_n 56
DVT1.1_31 : change location CD70,CD71,CD72,CD73, 57 DQS2_t VSS27 58 DDR_A_D22
CD5,CD6,CD7,CD8,CD15,CD14,CD13 from SE000005T80 to SE00000UD00 2 2 2 DDR_A_D23 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_A_D18
DDR_A_D19 63 VSS30 DQ18 64
65 DQ19 VSS31 66 DDR_A_D28
DDR_A_D29 67 VSS32 DQ28 68
Layout Note: DQ29 VSS33 DDR_A_D24
69 70
Place near JDIMM1 DDR_A_D25 71 VSS34 DQ24 72
CD112 RF request DQ25 VSS35
73 74 DDR_A_DQS#3
75 VSS36 DQS3_c 76 DDR_A_DQS3
+1.2V_DDR 77 DM3_n/DBI3_n DQS3_t 78
81 DQ30 DQ31 82
DQ26 DQ27
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
85 86
DDR_A_CB0 87 VSS41 VSS42 88 DDR_A_CB1
1 1 1 1 1 1 1 1 100P_0201_50V8J 89 CB5/NC CB4/NC 90
CD1
CD2
CD75
CD74
CD77
CD76
CD79
CD78
1 RF@ CD114 DDR_A_CB5 91 VSS43 VSS44 92 DDR_A_CB4

93 CB1/NC CB0/NC 94
2 2 2 2 2 2 2 2 DDR_A_DQS#8 95 VSS45 VSS46 96
2 <7> DDR_A_DQS#8 DDR_A_DQS8 DQS8_c DM8_n/DBI_n/NC
97 98
<7> DDR_A_DQS8 DQS8_t VSS47 DDR_A_CB7
99 100
DDR_A_CB2 101 VSS48 CB6/NC 102
C 103 CB2/NC VSS49 104 DDR_A_CB6 C
CD114 RF request DDR_A_CB3 105 VSS50 CB7/NC 106
107 CB3/NC VSS51 108
DDR_CKE0_DIMMA VSS52 RESET_n DDR_CKE1_DIMMA DDR4_DRAMRST# <23,24>
109 110
<7> DDR_CKE0_DIMMA CKE0 CKE1 DDR_CKE1_DIMMA <7>
111 112
+1.2V_DDR DDR_A_BG1 113 VDD1 VDD2 114
.1U_0402_16V7K
<7> DDR_A_BG1 DDR_A_BG0 BG1 ACT_n DDR_A_ALERT# DDR_A_ACT# <7>
115 116 1 @
<7> DDR_A_BG0 BG0 ALERT_n DDR_A_ALERT# <7>
117 118
CD3326
DDR_A_MA12 119 VDD3 VDD4 120 DDR_A_MA11
DDR_A_MA9 121 A12 A11 122 DDR_A_MA7
123 A9 A7 124 2
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
DDR_A_MA8 125 VDD5 VDD6 126 DDR_A_MA5

1 DDR_A_MA6 A8 A5 DDR_A_MA4
1 1 1 1 1 1 1 1 127 128
+ CD11 129 A6 A4 130
220U_D7_2VM_R6M DDR_A_MA3 131 VDD7 VDD8 132 DDR_A_MA2
CD5
CD6
CD7
CD8
CD70
CD71
CD72
CD73
DDR_A_MA1 133 A3 A2 134 All VREF traces should

2 2 2 2 2 2 2 2 2 135 A1 EVENT_n/NF 136
M_CLK_DDR0 VDD9 VDD10 M_CLK_DDR1
have 10 mil trace width
137 138
<7> M_CLK_DDR0 M_CLK_DDR#0 CK0_t CK1_t/NF M_CLK_DDR#1 M_CLK_DDR1 <7>
139 140
<7> M_CLK_DDR#0 CK0_c CK1_c/NF M_CLK_DDR#1 <7>
141 142
DDR_A_PAR 143 VDD11 VDD12 144 DDR_A_MA0
<7> DDR_A_PAR DDR_A_BS1 PARITY A0 DDR_A_MA10
DVT1.1_31 : change location CD70,CD71,CD72,CD73, 145 146
CD5,CD6,CD7,CD8,CD15,CD14,CD13 from SE000005T80 to SE00000UD00 <7> DDR_A_BS1 BA1 A10/AP
147 148
DDR_CS0_DIMMA# 149 VDD13 VDD14 150 DDR_A_BS0
<7> DDR_CS0_DIMMA# DDR_A_WE# CS0_n BA0 DDR_A_RAS# DDR_A_BS0 <7>
151 152
<7> DDR_A_WE# WE_n/A14 RAS_n/A16 DDR_A_RAS# <7>
153 154
M_ODT0 155 VDD15 VDD16 156 DDR_A_CAS#
+3VS +3VS +3VS <7> M_ODT0 DDR_CS1_DIMMA# ODT0 CAS_n/A15 DDR_A_MA13 DDR_A_CAS# <7>
157 158
<7> DDR_CS1_DIMMA# CS1_n A13
159 160
M_ODT1 161 VDD17 VDD18 162 +V_DDR_REFA
<7> M_ODT1 ODT1 C0/CS2_n/NC +V_DDR_REFA
163 164
165 VDD19 VREFCA 166 DIMM_CHA_SA2 20mil
C1, CS3_n,NC SA2
1
167 168
.1U_0402_16V7K
RD1 RD2 RD3
@ @ @ 171 DQ37 DQ36 172
0_0201_5% 0_0201_5% 0_0201_5% DDR_A_D33 VSS55 VSS56 DDR_A_D32 1
173 174
CD18
175 DQ33 DQ32 176
DDR_A_DQS#4 VSS57 VSS58
2
177 178
DIMM_CHA_SA0 DIMM_CHA_SA1 DIMM_CHA_SA2 DDR_A_DQS4 179 DQS4_c DM4_n/DBI4_n 180 +1.2V_DDR 2
B DDR_A_D38 183 VSS60 DQ39 184 B
DQ38 VSS61 DDR_A_D35
1
185 186
RD28 RD29 RD30 DDR_A_D34 187 VSS62 DQ35 188
+1.2V_DDR 189 DQ34 VSS63 190 DDR_A_D45
0_0201_5% 0_0201_5% 0_0201_5% DDR_A_D44 VSS64 DQ45
191 192
193 DQ44 VSS65 194 DDR_A_D41
DDR_A_D40 VSS66 DQ41
2
195 196
197 DQ40 VSS67 198 DDR_A_DQS#5
199 VSS68 DQS5_c 200 DDR_A_DQS5
DDR_A_D46 VSS69 VSS70 DDR_A_D47
1
203 204
RD35 205 DQ46 DQ47 206
470_0402_1% DDR_A_D42 207 VSS71 VSS72 208 DDR_A_D43
209 DQ42 DQ43 210
DQ52 DQ53
2
213 214
RD31 1 2 0_0201_5% 217 DQ49 DQ48 218
<23,24> DDR4_DRAMRST# H_DRAMRST# <15> DDR_A_DQS#6 VSS77 VSS78
219 220
DDR_A_DQS6 221 DQS6_c DM6_n/DBI6_n 222 +1.2V_DDR
.1U_0402_16V7K
@ DDR_A_D55 225 VSS80 DQ54 226

1 DQ55 VSS81 DDR_A_D50
227 228
CD69
DDR_A_D51 229 VSS82 DQ50 230

231 DQ51 VSS83 232 DDR_A_D60
2 DDR_A_D61 233 VSS84 DQ60 234
DQ61 VSS85 DDR_A_D57
VREF traces should be at least 20 mils DDR_A_D56
235
237 VSS86 DQ57
236
238
wide with 20 mils spacing to other 239 DQ56
VSS88
VSS87
DQS7_c
240 DDR_A_DQS#7
DDR_A_DQS7
241 242
signals +1.2V_DDR 243 DM7_n/DBI7_n DQS7_t 244
247 DQ62 DQ63 248
CPU Side +V_DDR_REFA_R +VDDQ_DDR
DDR_A_D58
PCH_SMBCLK
249
251
VSS91
DQ58
VSS93
VSS92
DQ59
VSS94
250
252
DDR_A_D59
PCH_SMBDATA
253 254
<15,24,79> PCH_SMBCLK SCL SDA DIMM_CHA_SA0 PCH_SMBDATA <15,24,79>
255 256
+3VS VDDSPD SA0
257 258
DIMM Side +2.5V_MEM VPP1 VTT DIMM_CHA_SA1 +0.6VS
1
259 260
20mil RH206 261 VPP2 SA1 262
A 1K_0201_1% GND1 GND2 A
+V_DDR_REFA
2
1 2 2_0402_1% +V_DDR_REFA
RH484
20mil LOTES_ADDR0206-P001A02~D CONN@
1
1
CH101 RH209
0.022U_0201_10V6K 1K_0201_1%
2
1

2
RH211
24.9_0201_1%
P023-DDR4 DIMMA
2

5 4 3 2 1
5 4 3 2 1
JDIMM2
+1.2V_DDR JP?
<7> DDR_B_D[0..63] +1.2V_DDR
<7> DDR_B_MA[0..13]
1 2
<7> DDR_B_DQS#[0..7] DDR_B_D5 VSS1 VSS2 DDR_B_D4
3 4
<7> DDR_B_DQS[0..7] DQ5 DQ4
Layout Note: Layout Note: 5 6
<7> DDR_B_CB[0..7] DDR_B_D1 VSS3 VSS4 DDR_B_D0
7 8
Place near JDIMM1.258 Place near JDIMM2.257,259 9 DQ1 DQ0 10
DDR_B_DQS#0 11 VSS5 VSS6 12
DDR_B_DQS0 13 DQS0_c DM0_n/DBI0_n 14
15 DQS0_t VSS7 16 DDR_B_D6
DDR_B_D7 17 VSS8 DQ6 18
19 DQ7 VSS9 20 DDR_B_D2
+0.6VS +2.5V_MEM 23 DQ3 VSS11 24 DDR_B_D12
DDR_B_D13 25 VSS12 DQ12 26
D 27 DQ13 VSS13 28 DDR_B_D8 D
31 DQ9 VSS15 32 DDR_B_DQS#1
VSS16 DQS1_c DDR_B_DQS1
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
33 34
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
100P_0201_50V8J
100P_0201_50V8J
10U_0402_6.3V6M
10U_0402_6.3V6M
Layout Note: DM1_n/DBI_n DQS1_t
35 36
RF@CD115
RF@CD109
1 1 1 1 1 1 1 1 1 1 Place near JDIMM2.255 DDR_B_D15 VSS17 VSS18 DDR_B_D14
37 38
CD32
CD30
CD31
CD27
CD28
39 DQ15 DQ14 40
CD90
CD89
CD88
DDR_B_D10 41 VSS19 VSS20 42 DDR_B_D11

2 2 2 2 2 2 2 2 2 2 43 DQ10 DQ11 44
47 DQ21 DQ20 48
+3VS 51 DQ17 DQ16 52
DDR_B_DQS2 55 DQS2_c DM2_n/DBI2_n 56
CD115 RF request CD109 RF request DDR_B_D23 59 VSS28 DQ22 60
61 DQ23 VSS29 62 DDR_B_D18
100P_0201_50V8J
0.1U_0201_10V6K
DDR_B_D19 63 VSS30 DQ18 64
RF@CD116
2.2U_0201_6.3V6M
X00:0403 0603 change 0402 (CD27 CD28) for layout
1 1 1 DQ19 VSS31 DDR_B_D28
65 66
CD34
CD35
DDR_B_D29 67 VSS32 DQ28 68
69 DQ29 VSS33 70 DDR_B_D24
2 2 2 DDR_B_D25 71 VSS34 DQ24 72
DQ25 VSS35
Layout Note: DDR_B_DQS#3
73 74
Place near JDIMMB 75 VSS36 DQS3_c 76 DDR_B_DQS3
77 DM3_n/DBI3_n DQS3_t 78
81 DQ30 DQ31 82
CD109 RF request DDR_B_D26 83 VSS39 VSS40 84 DDR_B_D27
85 DQ26 DQ27 86
DDR_B_CB4 87 VSS41 VSS42 88 DDR_B_CB1
89 CB5/NC CB4/NC 90
DDR_B_CB2 91 VSS43 VSS44 92 DDR_B_CB3
+1.2V_DDR 93 CB1/NC CB0/NC 94
<7> DDR_B_DQS#8 DDR_B_DQS8 97 DQS8_c DM8_n/DBI_n/NC 98
<7> DDR_B_DQS8 99 DQS8_t VSS47 100 DDR_B_CB6
VSS48 CB6/NC
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
DDR_B_CB7 101 102

100P_0201_50V8J
C 103 CB2/NC VSS49 104 DDR_B_CB0 C

RF@CD110
1 1 1 1 1 1 1 1 1 DDR_B_CB5 VSS50 CB7/NC

105 106
CD19
CD20
CD21
CD22
CD83
CD81
CD80
CD82
107 CB3/NC VSS51 108

DDR_CKE2_DIMMB VSS52 RESET_n DDR_CKE3_DIMMB DDR4_DRAMRST# <23>
109 110
2 2 2 2 2 2 2 2 2 <7> DDR_CKE2_DIMMB CKE0 CKE1 DDR_CKE3_DIMMB <7>
111 112
DDR_B_BG1 113 VDD1 VDD2 114
.1U_0402_16V7K
<7> DDR_B_BG1 DDR_B_BG0 BG1 ACT_n DDR_B_ALERT# DDR_B_ACT# <7>
115 116 1 @
<7> DDR_B_BG0 BG0 ALERT_n DDR_B_ALERT# <7>
117 118
CD3327
DDR_B_MA12 119 VDD3 VDD4 120 DDR_B_MA11
CD109 RF request DDR_B_MA9 121 A12 A11 122 DDR_B_MA7
123 A9 A7 124 2
+1.2V_DDR DDR_B_MA6 127 A8 A5 128 DDR_B_MA4
129 A6 A4 130
DDR_B_MA1 133 A3 A2 134 All VREF traces should
135 A1 EVENT_n/NF 136
M_CLK_DDR2 VDD9 VDD10 M_CLK_DDR3
have 10 mil trace width
137 138
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
<7> M_CLK_DDR2 M_CLK_DDR#2 CK0_t CK1_t/NF M_CLK_DDR#3 M_CLK_DDR3 <7>

1 139 140
<7> M_CLK_DDR#2 CK0_c CK1_c/NF M_CLK_DDR#3 <7>
1 1 1 1 1 1 1 1 141 142
+ DDR_B_PAR 143 VDD11 VDD12 144 DDR_B_MA0
CD23
CD24
CD26
CD87
CD85
CD33 <7> DDR_B_PAR

220U_D7_2VM_R6M DDR_B_BS1 145 PARITY A0 146 DDR_B_MA10
CD25
CD84
CD86
<7> DDR_B_BS1 BA1 A10/AP

147 148
2 2 2 2 2 2 2 2 2 DDR_CS2_DIMMB# 149 VDD13 VDD14 150 DDR_B_BS0
<7> DDR_CS2_DIMMB# DDR_B_WE# CS0_n BA0 DDR_B_RAS# DDR_B_BS0 <7>
151 152
<7> DDR_B_WE# WE_n/A14 RAS_n/A16 DDR_B_RAS# <7>
153 154
M_ODT2 155 VDD15 VDD16 156 DDR_B_CAS#
<7> M_ODT2 DDR_CS3_DIMMB# ODT0 CAS_n/A15 DDR_B_MA13 DDR_B_CAS# <7>
157 158
<7> DDR_CS3_DIMMB# CS1_n A13 +V_DDR_REFB
159 160
M_ODT3 161 VDD17 VDD18 162
<7> M_ODT3
163 ODT1 C0/CS2_n/NC 164 +V_DDR_REFB 20mil
165 VDD19 VREFCA 166 DIMM_CHB_SA2
167 C1, CS3_n,NC SA2 168
.1U_0402_16V7K
171 DQ37 DQ36 172
DDR_B_D33 VSS55 VSS56 DDR_B_D32 1
173 174
CD29
175 DQ33 DQ32 176
DDR_B_DQS4 179 DQS4_c DM4_n/DBI4_n 180 +1.2V_DDR 2
B +3VS +3VS +3VS DDR_B_D38 183 VSS60 DQ39 184 B
185 DQ38 VSS61 186 DDR_B_D35
DDR_B_D34 187 VSS62 DQ35 188
189 DQ34 VSS63 190 DDR_B_D45
DDR_B_D44 191 VSS64 DQ45 192
DQ44 VSS65 DDR_B_D41
1
193 194
RD4 RD5 RD6 DDR_B_D40 195 VSS66 DQ41 196
@ @ 197 DQ40 VSS67 198 DDR_B_DQS#5
0_0201_5% 0_0201_5% 0_0201_5% VSS68 DQS5_c DDR_B_DQS5
199 200
VSS69 VSS70
2
DDR_B_D46 203 204 DDR_B_D47

DIMM_CHB_SA0 DIMM_CHB_SA1 DIMM_CHB_SA2 205 DQ46 DQ47 206
209 DQ42 DQ43 210
DDR_B_D52 VSS73 VSS74 DDR_B_D53
1
211 212
RD38 RD39 RD40 213 DQ52 DQ53 214
@ DDR_B_D49 215 VSS75 VSS76 216 DDR_B_D48
0_0201_5% 0_0201_5% 0_0201_5% DQ49 DQ48
217 218
DQS6_c DM6_n/DBI6_n +1.2V_DDR
2
DDR_B_DQS6 221 222

DDR_B_D55 225 VSS80 DQ54 226
227 DQ55 VSS81 228 DDR_B_D50
DDR_B_D51 229 VSS82 DQ50 230
231 DQ51 VSS83 232 DDR_B_D60
DDR_B_D61 VSS84 DQ60
VREF traces should be at least 20 mils 233
235 DQ61 VSS85
234
236 DDR_B_D57
wide with 20 mils spacing to other DDR_B_D56 237 VSS86
DQ56
DQ57
VSS87
238
DDR_B_DQS#7
239 240
signals 241 VSS88 DQS7_c 242 DDR_B_DQS7
+V_DDR_REFB_R DDR_B_D62 245 VSS89 VSS90 246 DDR_B_D63
+VDDQ_DDR 247 DQ62 DQ63 248
251 DQ58 DQ59 252
PCH_SMBCLK VSS93 VSS94 PCH_SMBDATA
1
253 254
<15,23,79> PCH_SMBCLK SCL SDA DIMM_CHB_SA0 PCH_SMBDATA <15,23,79>
RH207 255 256
+3VS VDDSPD SA0
1K_0201_1% 257 258
+2.5V_MEM VPP1 VTT DIMM_CHB_SA1 +0.6VS
259 260
20mil +V_DDR_REFB 261 VPP2 SA1 262
GND1 GND2
2
A A
1 2 2_0402_1% +V_DDR_REFB
RH485
20mil
1
1 LOTES_ADDR0206-P001A02~D
RH210 CONN@
CH100 1K_0201_1%
0.022U_0201_10V6K
2
2
1
RH212
Vinafix.com
24.9_0201_1%
2
P024-DDR4 DIMMB

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P025-Reserve
0.4(X03)
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P026-Reserve
0.4(X03)
5 4 3 2 1
5 4 3 2 1
+1.8V_GFX_AON
PEG_CTX_C_GRX_P[0..15]
UV18A
<6> PEG_CTX_C_GRX_P[0..15] GPIO25_FBVDD_PSI 1 2
RV1989 DIS@ 2.2K_0201_5%
PEG_CTX_C_GRX_N[0..15] PEG_CTX_C_GRX_P0 AN12 GC6_EVENT#_D 1 2
Part 1 of 7 RV551 DIS@ 10K_0402_5%
<6> PEG_CTX_C_GRX_N[0..15] PEG_CTX_C_GRX_N0 AM12 PEX_RX0 P6 GPU_GPIO0 NVVDD_PWM_VID GPU_PSI
RV1095 1 DIS@ 2 0_0201_5% RV552 1 DIS@ 2 10K_0402_5%
PEG_CRX_GTX_P[0..15] PEG_CTX_C_GRX_P1 AN14 PEX_RX0_N GPIO0 M3 GPU_GC6_FB_EN_GPU NVVDD_PWM_VID <97> SYS_PEX_RST_MON# 1 2
RV557 @ 10K_0201_5%
<6> PEG_CRX_GTX_P[0..15] PEG_CTX_C_GRX_N1 AM14 PEX_RX1 GPIO1 L6 GC6_EVENT#_D 1V8_MAIN_EN 1 2
DV14 RV562 DIS@ 10K_0402_5%
PEG_CRX_GTX_N[0..15] PEG_CTX_C_GRX_P2 AP14 PEX_RX1_N GPIO2 P5 GPU_GPIO3 GC6_EVENT#_D 2 1 GC6_EVENT# FRM_LCK 1 2
T6009 PAD~DTP@ GC6_EVENT# <13> RV564 DIS@ 10K_0402_5%
<6> PEG_CRX_GTX_N[0..15] PEG_CTX_C_GRX_N2 AP15 PEX_RX2 GPIO3 P7 1V8_MAIN_EN I2CB_SCL 1 2
1V8_MAIN_EN <37> RV570 DIS@ 1.8K_0402_5%
PEG_CTX_C_GRX_P3 AN15 PEX_RX2_N GPIO4 L7 FRM_LCK RB751S-40_SOD523-2 I2CB_SDA RV571 1 DIS@ 2 1.8K_0402_5%
PEG_CTX_C_GRX_N3 AM15 PEX_RX3 GPIO5 M7 GPU_PSI DVT1.1_ : change CPN from SCS00006300 to SCS0000FX00 GPU_CORE_CLK RV572 1 DIS@ 2 1.8K_0402_5%
PEG_CTX_C_GRX_P4 PEX_RX3_N GPIO6 LCD_BL_PWM GPU_PSI <97> DIS@ GPU_CORE_DATA
AN17 N8 DVT1.1_78 : change CPN from SCS0000FX00 to SCS00006300 RV573 1 DIS@ 2 1.8K_0402_5%
PEG_CRX_GTX_P0 CV818 2 1 0.22U_0201_6.3V6M DIS@ PEG_CRX_C_GTX_P0 PEG_CTX_C_GRX_N4 AM17 PEX_RX4 GPIO7 L3 GPU_GPIO8 RV1086 1 DIS@ 2 0_0402_5% MEM_VDD_CTL DV15 THERMAL_ALERT# RV553 1 DIS@ 2 10K_0402_5%
PEG_CRX_GTX_N0 2 1 0.22U_0201_6.3V6M DIS@ PEG_CRX_C_GTX_N0 PEG_CTX_C_GRX_P5 AP17 PEX_RX4_N GPIO8 M2 THERMAL_ALERT# MEM_VDD_CTL <37> GPU_LEVEL 2 1GPU_PWR_LEVEL LCD_BL_PWM 1 2
CV819 RV1834 @ 100K_0402_5%
PEG_CTX_C_GRX_N5 AP18 PEX_RX5 GPIO9 L1 MEM_VREF GPU_PWR_LEVEL <58>
D PEG_CRX_GTX_P1 2 1 0.22U_0201_6.3V6M DIS@ PEG_CRX_C_GTX_P1 PEG_CTX_C_GRX_P6 AN18 PEX_RX5_N GPIO10 M5 LCD_VDD MEM_VREF <35,36> GPU_GPIO22_OC_WARN# 1 2 D
CV820 RB751S-40_SOD523-2 RV1982 DIS@ 10K_0402_5%
PEG_CRX_GTX_N1 CV821 2 1 0.22U_0201_6.3V6M DIS@ PEG_CRX_C_GTX_N1 PEG_CTX_C_GRX_N6 AM18 PEX_RX6 GPIO11 N3 GPU_LEVEL DVT1.1_ : change CPN from SCS00006300 to SCS0000FX00 GPU_LEVEL RV554 1 DIS@ 2 10K_0402_5%
PEG_CTX_C_GRX_P7 PEX_RX6_N GPIO12 LCD_BLEN DIS@ HPD_IFPA
GPIO
AN20 M4 DVT1.1_78 : change CPN from SCS0000FX00 to SCS00006300 RV1992 1 DIS@ 2 10K_0201_5%
PEG_CRX_GTX_P2 CV822 2 1 0.22U_0201_6.3V6M DIS@ PEG_CRX_C_GTX_P2 PEG_CTX_C_GRX_N7 AM20 PEX_RX7 GPIO13 N4 HPD_IFPA HPD_IFPB RV1993 1 DIS@ 2 10K_0201_5%
PEG_CRX_GTX_N2 CV823 2 1 0.22U_0201_6.3V6M DIS@ PEG_CRX_C_GTX_N2 PEG_CTX_C_GRX_P8 AP20 PEX_RX7_N GPIO14 P2 HPD_IFPB HPD_IFPD RV1994 1 DIS@ 2 10K_0201_5%
PEG_CTX_C_GRX_N8 AP21 PEX_RX8 GPIO15 R8 SYS_PEX_RST_MON# HPD_IFPE RV1995 1 DIS@ 2 10K_0201_5%
PEG_CRX_GTX_P3 CV824 2 1 0.22U_0201_6.3V6M DIS@ PEG_CRX_C_GTX_P3 PEG_CTX_C_GRX_P9 AN21 PEX_RX8_N GPIO16 M6 HPD_IFPD HPD_IFPC RV1996 1 DIS@ 2 10K_0201_5%
PEG_CRX_GTX_N3 CV825 2 1 0.22U_0201_6.3V6M DIS@ PEG_CRX_C_GTX_N3 PEG_CTX_C_GRX_N9 AM21 PEX_RX9 GPIO17 R1 HPD_IFPE MEM_VDD_CTL RV1997 1 @ 2 10K_0201_5%
PEG_CTX_C_GRX_P10 AN23 PEX_RX9_N GPIO18 P3 3D VISION/STEREO GPU_PEX_RST_HOLD# RV563 1 @ 2 10K_0402_5%
PEG_CRX_GTX_P4 CV826 2 1 0.22U_0201_6.3V6M DIS@ PEG_CRX_C_GTX_P4 PEG_CTX_C_GRX_N10 AM23 PEX_RX10 GPIO19 P4 NB_FGC6 T4977 PAD~DTP@ +1.8V_GFX_AON +3VS
PEG_CRX_GTX_N4 CV827 2 1 0.22U_0201_6.3V6M DIS@ PEG_CRX_C_GTX_N4 PEG_CTX_C_GRX_P11 AP23 PEX_RX10_N GPIO20 P1 GPU_GPIO21
PEG_CTX_C_GRX_N11 PEX_RX11 GPIO21 GPU_GPIO22_OC_WARN#
1
AP24 P8 DIS@
PEG_CRX_GTX_P5 2 1 0.22U_0201_6.3V6M DIS@ PEG_CRX_C_GTX_P5 PEG_CTX_C_GRX_P12 AN24 PEX_RX11_N GPIO22 T8 GPU_PEX_RST_HOLD# GPU_GPIO22_OC_WARN# <98>
CV828 RV1112
PEG_CRX_GTX_N5 PEG_CRX_C_GTX_N5 PEG_CTX_C_GRX_N12 PEX_RX12 GPIO23 HPD_IFPF
2
CV829 2 1 0.22U_0201_6.3V6M DIS@ AM24 L2 T4979 PAD~DTP@ 1.8K_0402_5% DIS@
PEG_CTX_C_GRX_P13 AN26 PEX_RX12_N GPIO24 R4 GPIO25_FBVDD_PSI_R RV1970 1 DIS@ 2 0_0402_5% RV1133
PEG_CRX_GTX_P6 2 1 0.22U_0201_6.3V6M DIS@ PEG_CRX_C_GTX_P6 PEG_CTX_C_GRX_N13 AM26 PEX_RX13 GPIO25 R5 GPIO26_FP_FUSE GPIO25_FBVDD_PSI <96>
CV830 100K_0402_5%
PEG_CRX_GTX_N6 PEG_CRX_C_GTX_N6 PEG_CTX_C_GRX_P14 PEX_RX13_N GPIO26 HPD_IFPC GPIO26_FP_FUSE <37>
2
CV831 2 1 0.22U_0201_6.3V6M DIS@ AP26 U3
PEG_CTX_C_GRX_N14 AP27 PEX_RX14 GPIO27
PEG_CRX_GTX_P7 PEG_CRX_C_GTX_P7 PEG_CTX_C_GRX_P15 PEX_RX14_N
1
2
2 1 0.22U_0201_6.3V6M DIS@ AN27
G
CV832 DIS@
PEG_CRX_GTX_N7 CV833 2 1 0.22U_0201_6.3V6M DIS@ PEG_CRX_C_GTX_N7 PEG_CTX_C_GRX_N15 AM27 PEX_RX15 QV98 LCD_VDD RV1837 1 DIS@ 2 100K_0402_5%
PEX_RX15_N GPU_GC6_FB_EN_GPU 3 1 MEM_VDD_CTL RV1836 1 @ 2 10K_0402_5%
PEG_CRX_GTX_P8 2 1 0.22U_0201_6.3V6M @ PEG_CRX_C_GTX_P8 GPU_GC6_FB_EN <13> GPU_GPIO21
CV834 RV1840 1 DIS@ 2 100K_0402_5%
D
PEG_CRX_GTX_N8 CV835 2 1 0.22U_0201_6.3V6M @ PEG_CRX_C_GTX_N8 PEG_CRX_C_GTX_P0 AK14 AN9 GPU_ADC_IN_R RV1990 1 DIS@ 2 0_0201_5% LCD_BL_PWM RV1841 1 DIS@ 2 100K_0402_5%
PEG_CRX_C_GTX_N0 AJ14 PEX_TX0 ADC_IN AM9 GPU_ADC_IN_N_R RV1991 1 DIS@ 2 0_0201_5% GPU_ADC_IN <98> GPU_GC6_FB_EN_GPU RV566 1 2
PEG_CRX_GTX_P9 CV836 2 1 0.22U_0201_6.3V6M @ PEG_CRX_C_GTX_P9 PEG_CRX_C_GTX_P1 AH14 PEX_TX0_N OVR-M ADC_IN_N GPU_ADC_IN_N <98>
BSS138W 1N SOT-323-3
MEM_VREF RV567 1
DIS@
DIS@ 2
10K_0402_5%
100K_0402_5%
PEG_CRX_GTX_N9 CV837 2 1 0.22U_0201_6.3V6M @ PEG_CRX_C_GTX_N9 PEG_CRX_C_GTX_N1 AG14 PEX_TX1 +1.8V_GFX_AON +1.8V_GFX_AON GPU_PEX_RST_HOLD#RV1976 1 DIS@ 2 100K_0402_5%
PEG_CRX_C_GTX_P2 AK15 PEX_TX1_N DIS@ NB_FGC6 RV1980 1 DIS@ 2 10K_0402_5%
PEG_CRX_GTX_P10 CV838 2 1 0.22U_0201_6.3V6M @ PEG_CRX_C_GTX_P10 PEG_CRX_C_GTX_N2 AJ15 PEX_TX2 AG10 TS_AVDD RV1971 1 2 0_0402_5% RV1084 1 @ 2 0_0402_5% GPIO26_FP_FUSE RV1981 1 DIS@ 2 10K_0402_5%
PEG_CRX_GTX_N10 PEG_CRX_C_GTX_N10 PEG_CRX_C_GTX_P3 PEX_TX2_N TS_AVDD LCD_BLEN
1
CV839 2 1 0.22U_0201_6.3V6M @ AL16 DIS@ DIS@ RV1838 1 @ 2 100K_0402_5%
PEG_CRX_C_GTX_N3 AK16 PEX_TX3 1U_0201_4VAM 2 1 CV9376 +1.8V_GFX_AON
PEG_CRX_GTX_P11 2 1 0.22U_0201_6.3V6M @ PEG_CRX_C_GTX_P11 PEG_CRX_C_GTX_P4 AK17 PEX_TX3_N Thermal Sensor RV1842
10K_0402_5%
CV840 DIS@
PEG_CRX_GTX_N11 CV841 2 1 0.22U_0201_6.3V6M @ PEG_CRX_C_GTX_N11 PEG_CRX_C_GTX_N4 AJ17 PEX_TX4 UV29
PEG_CRX_C_GTX_P5 PEX_TX4_N
5
C AH17 C
PEG_CRX_GTX_P12 PEG_CRX_C_GTX_P12 PEG_CRX_C_GTX_N5 PEX_TX5 DGPU_PEX_RST#
2
CV842 2 1 0.22U_0201_6.3V6M @ AG17 AK9 <27> DGPU_PEX_RST# 1
P
PEG_CRX_GTX_N12 PEG_CRX_C_GTX_N12 PEG_CRX_C_GTX_P6 PEX_TX5_N RES B
RES
CV843 2 1 0.22U_0201_6.3V6M @ AK18 AL10 4
PEG_CRX_C_GTX_N6 AJ18 PEX_TX6 RES AL9 GPU_GC6_FB_EN_GPU# 2 O
PEG_CRX_GTX_P13 PEG_CRX_C_GTX_P13 PEG_CRX_C_GTX_P7 PEX_TX6_N RES D A
G
CV844 2 1 0.22U_0201_6.3V6M @ AL19 AP8 DIS@
PEG_CRX_GTX_N13 CV845 2 1 0.22U_0201_6.3V6M @ PEG_CRX_C_GTX_N13 PEG_CRX_C_GTX_N7 AK19 PEX_TX7 RES GPU_GC6_FB_EN_GPU 2 QV105 TC7SZ08FU_SSOP5
PCI EXPRESS
PEG_CRX_C_GTX_P8 PEX_TX7_N
3
AK20 G BSS138W 1N SOT-323-3
PEG_CRX_GTX_P14 CV846 2 1 0.22U_0201_6.3V6M @ PEG_CRX_C_GTX_P14 PEG_CRX_C_GTX_N8 AJ20 PEX_TX8 AP9 S
PEG_CRX_GTX_N14 PEG_CRX_C_GTX_N14 PEG_CRX_C_GTX_P9 PEX_TX8_N TS_VREF
3
CV847 2 1 0.22U_0201_6.3V6M @ AH20
PEG_CRX_C_GTX_N9 PEX_TX9
2
AG20
G
DIS@
PEG_CRX_GTX_P15 CV848 2 1 0.22U_0201_6.3V6M @ PEG_CRX_C_GTX_P15 PEG_CRX_C_GTX_P10 AK21 PEX_TX9_N R7 I2CB_SCL QV91
PEG_CRX_GTX_N15 CV849 2 1 0.22U_0201_6.3V6M @ PEG_CRX_C_GTX_N15 PEG_CRX_C_GTX_N10 AJ21 PEX_TX10 I2CB_SCL R6 I2CB_SDA RV1082 1 DIS@ 2 0_0402_5% THERMATRIP_GPU#_R 3 1 RV1083 1 DIS@ 2 0_0402_5%
PEG_CRX_C_GTX_P11 PEX_TX10_N I2CB_SDA <28,37> THERMATRIP_GPU# THERMTRIP1# <58>
AL22
D
PEG_CRX_C_GTX_N11 AK22 PEX_TX11 R2
I2C
PEG_CRX_C_GTX_P12 AK23 PEX_TX11_N I2CC_SCL R3 GPU_CORE_CLK <97>
BSS138W 1N SOT-323-3
PEG_CRX_C_GTX_N12 AJ23 PEX_TX12 I2CC_SDA GPU_CORE_DATA <97>
PEG_CRX_C_GTX_P13 AH23 PEX_TX12_N T4 EC_SMB_CK2_PX
PEG_CRX_C_GTX_N13 AG23 PEX_TX13 I2CS_SCL T3 EC_SMB_DA2_PX
PEG_CRX_C_GTX_P14 AK24 PEX_TX13_N I2CS_SDA
PEG_CRX_C_GTX_N14 AJ24 PEX_TX14 +1.8V_GFX_AON
PEG_CRX_C_GTX_P15 AL25 PEX_TX14_N
PEG_CRX_C_GTX_N15 AK25 PEX_TX15
PEX_TX15_N GPCPLL_AVDD
H26 W=20mils +GPCPLL_AVDD
+GPCPLL_AVDD <30>
DIS@
DV13
RV1844 1 DIS@ 2 0_0402_5% 2
GC6_GPU_WAKE# XSN_PLLVDD
AD8 W=20mils +XS_PLLVDD
+XS_PLLVDD <30>
RV1131 1 DIS@ 2 0_0402_5% DGPU_PEX_RST# <27,94> 1VS_GFX_PG
AJ11 1
TP@PAD~D T6012
PEX_WAKE# W=20mils +SP_PLLVDD FBVDD_EN <37,96>
1
AE8
AL13 SP_PLLVDD +SP_PLLVDD <30> ALL_GPWRGD GPU_GC6_FB_EN_GPU 3
RV1132 1 @ 2 0_0402_5%
<14> CLK_PEG_P7 PEX_REFCLK W=20mils +VID_PLLVDD
RV326 RV325 2
1
AK13 AD7
100K_0402_5%
0.1U_0201_10V6K
<14> CLK_PEG_N7 5.1K_0402_5% 5.1K_0402_5%
CLKREQ_PCIE#7_GPU AK12 PEX_REFCLK_N VID_PLLVDD +VID_PLLVDD <30>
RV550
DIS@
CH550
DIS@ DIS@ BAT54CW-7-F_SOT323-3 @
PEX_CLKREQ_N
PEX_TSTCLK_OUT XTALIN_R
2
AJ26 H3 XTALIN RV1998 1 DIS@ 2 0_0201_5% 1
CLK
TP@PAD~D T4991
PEX_TSTCLK_OUT# NC XTAL_IN XTAL_OUT RV1999 1 DIS@ XTAL_OUT_R
2
TP@PAD~D T4992 AK26 H2 2 0_0201_5% LBSS139DW1T1G 2N SOT-363-6 ESD
NC XTAL_OUT
2
B DIS@ B
DGPU_PEX_RST# RV577 1 DIS@ 2 0_0402_5% DGPU_PEX_RST#_R AJ12 J4 XTALOUT RV581 1 DIS@ 2 100K_0201_5% EC_SMB_CK2_PX QV21A 1 6
<27> DGPU_PEX_RST# PEX_RST_N XTAL_OUTBUFF GPU_SMBCLK <58,66>
RV578 1 DIS@ 2 2.49K_0402_1% PEX_TERMP AP29 H1 XTALSSIN RV579 1 DIS@ 2 10K_0201_5%
PEX_TERMP EXT_REFCLK_FL
5
LBSS139DW1T1G 2N SOT-363-6 ESD
DIS@
EC_SMB_DA2_PX QV21B 4 3
N18P-G0_FCBGA960~D GPU_SMBDAT <58,66>
GPU@
+1.8V_GFX_AON
RV580 RV1833 1 @ 2 10M_0402_5%

1 DIS@ 2 1@
CV853
10K_0402_5% 0.1U_0402_10V7K DIS@
+1.8V_GFX_AON YV1
DIS@ 2 RV590
ALL_GPWRGD XTALIN_R XTAL_OUT_R
5
UV19 2 DIS@ 1 10K_0402_5% 1 3

1 3
1
1 RV587 1 1
<17> DGPU_HOLD_RST#
G VCC
B SYS_PEX_RST_MON#_L DGPU_PEX_RST# NC NC
2
4 1 DIS@ 2 DIS@ DIS@
2 Y DGPU_PEX_RST# <27>
<14,42,52,55,66,68,69,79> PCH_PLTRST#_EC DIS@ DIS@ CV857 27MHZ_10PF_XRCGB27M000F2P18R0 CV858
A 2 4
1
12P_0201_50V8J 15P_0201_50V8J
100K_0402_5%
0_0402_5% RV588 RV591

2 2
RV589
DIS@
TC7SZ08FU_SSOP5 1M_0201_5% 10K_0402_5%
2
3
GC6 2.1 funct i on
1
+3VS
2
2
DIS@
G
1
A
DIS@
RV1847 +1.8V_GFX_AON
QV103
1 3 BSS138W 1N SOT-323-3 CLKREQ_PCIE#7_GPU GPU_PWR_LEVEL A
<14> CLKREQ_PCIE#7
10K_0402_5% Low Low Performace
S
DIS@
UV20
High High Performace
2
RV1848 1 DIS@ 2 0_0402_5% 1

P
<27,94> 1VS_GFX_PG B 4 ALL_GPWRGD

RV1846 1 DIS@ 2 0_0402_5% 2 O
<15,37,58,96> DGPU_PWROK A Security Classification Compal Secret Data Compal Electronics, Inc.
G
TC7SZ08FU_SSOP5 Issued Date 2019/11/30 Deciphered Date 2027/06/21 Title

3
P027-N18P_PCIE/DAC/GPIO

5 4 3 2 1
Vinafix.com
5 4 3 2 1
UV18D
Part 4 of 7
AM6
AN6 IFPA_L3
AP3 IFPA_L3_N AC6
D
AN3 IFPA_L2 NC AJ28 D
AN5 IFPA_L2_N NC AJ4
AM5 IFPA_L1 NC AJ5
AL6 IFPA_L1_N NC AL11
AK6 IFPA_L0 NC C15
AJ6 IFPA_L0_N NC D19
AH6 IFPA_AUX_SCL NC D20
NC
IFPA_AUX_SDA_N NC D23
NC D26
AJ9 NC
AH9 IFPB_L3
AP6 IFPB_L3_N V32
AP5 IFPB_L2 NC
AM7 IFPB_L2_N
IFPB_L1 trace width: 16mils
AL7
AN8 IFPB_L1_N differential voltage sensing.
AM8 IFPB_L0 differential signal routing.
AK8 IFPB_L0_N
AL8 IFPB_AUX_SCL
IFPB_AUX_SDA_N L4
VDD_SENSE VCC_SENSE_NVVDD <97>
AK1
AJ1 IFPC_L0
AJ3 IFPC_L0_N L5
IFPC_L1 GND_SENSE VSS_SENSE_NVVDD <97>
AJ2
AH3 IFPC_L1_N
AH4 IFPC_L2
TMDS
AG5 IFPC_L2_N
AG4 IFPC_L3
IFPC_L3_N
C
TEST C
AM1 AK11 TESTMODE

AM2 IFPD_L0 NVJTAG_SEL
IFPD_L0_N GPU_JTAG_TCK
1
AM3 AM10 PAD~D T201 TP@
AM4 IFPD_L1 JTAG_TCK AM11 GPU_JTAG_TDI PAD~D T202 TP@ DIS@
AL3 IFPD_L1_N JTAG_TDI AP12 GPU_JTAG_TDO PAD~D T203 TP@ RV592 +1.8V_GFX_AON +1.8V_GFX_AON
AL4 IFPD_L2 JTAG_TDO AP11 GPU_JTAG_TMS PAD~D T204 TP@ 10K_0402_5%
AK4 IFPD_L2_N JTAG_TMS AN11 GPU_JTAG_TRST# RV593 1 DIS@ 2 10K_0402_5%
IFPD_L3 JTAG_TRST_N
2
AK5 1
IFPD_L3_N
1
DIS@
CV9378 DIS@
AD2 0.1U_0201_10V6K RV1987
AD3 IFPE_L0 2 10K_0201_5%
AD1 IFPE_L0_N
IFPE_L1 SERIAL
2
AC1 UV31
AC2 IFPE_L1_N H6 ROM_CS RV1983 1 DIS@ 2 33.2_0201_1% ROM_CS_R 8 1 ROM_CS_R
AC3 IFPE_L2 ROM_CS_N H4 ROM_SCLK RV1984 1 DIS@ 2 33.2_0201_1% ROM_SCLK_R 7 VCC CS# 2 ROM_SO_R
AC4 IFPE_L2_N ROM_SCLK H5 ROM_SI RV1985 1 DIS@ 2 33.2_0201_1% ROM_SI_R ROM_SCLK_R 6 HOLD#(IO3) DO(IO1) 3
AC5 IFPE_L3 ROM_SI H7 ROM_SO RV1986 1 DIS@ 2 0_0201_5% ROM_SO_R ROM_SI_R 5 CLK W P#(IO2) 4
IFPE_L3_N ROM_SO 9 DI(IO0) GND
+1.8V_GFX_AON GND
AE3 W25Q80EWZPIG_WSON8_6X5
NC ROM_SCLK <34>
AE4
NC ROM_SI <34>
2
AF4 DIS@ DIS@
NC ROM_SO <34>
AF5 RV594
AD4 NC GENERAL 10K_0402_5%
AD5 NC E1
AG1 NC BUFRST_N
NC
1
AF1 M1
B NC OVERT THERMATRIP_GPU# <27,37> B
AG3
AG2 IFPC_AUX_SCL
IFPC_AUX_SDA_N J2 STRAP0
STRAP0 STRAP0 <34>
J7 STRAP1
STRAP1 STRAP1 <34>
AK3 J6 STRAP2
IFPD_AUX_SCL STRAP2 STRAP2 <34>
AK2 J5 STRAP3
IFPD_AUX_SDA_N STRAP3 STRAP3 <34>
J3 STRAP4
STRAP4 STRAP4 <34>
J1 STRAP5
STRAP5 STRAP5 <34>
AB3
AB4 IFPE_AUX_SCL
IFPE_AUX_SDA_N K3
THERMDP K4
AF3 THERMDN
AF2 NC
NC
N18P-G0_FCBGA960~D
GPU@
A A

P028-N18P_eDP/HDMI/mDP

5 4 3 2 1
5 4 3 2 1
PEX_DVDD +1VS_GFX
+1VS_GFX
Please Under GPU: Under:
4.7uF x 3 4.7uF x 3 Under GPU Near GPU 1.6A
0.47uF x 12 1uF x 11
Near: Near:
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
22U_0603_6.3VAM
22U_0603_6.3VAM
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
10uF x 3 10uF x 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1
UV18E 22uF x 2 22uF x 2
CV865
CV866
CV859
CV9332
CV9333
CV9334
CV9335
CV9336
CV9337
CV9326
CV9328
CV9327
CV9330
CV9331
CV9321
CV9322
CV9323
CV869
CV9325
+1.35VSDGPU
+1.35VSDGPU 14A Near GPU
Part 5 of 7
2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 2 2
Under: AA27
AA30 FBVDDQ_0 PEX_DVDD_0
AG19
AG21 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
10uF x 4 FBVDDQ_1 PEX_DVDD_1 DIS@ DIS@ DIS@
DIS@ DIS@ DIS@
10U_0603_6.3V6M
22U_0402_6.3V6M
22U_0402_6.3V6M
10U_0402_6.3V6M
AB27 AG22
22U_0603_6.3VAM
22U_0603_6.3VAM
22U_0603_6.3VAM
DIS@ DIS@ DIS@ DIS@
FBVDDQ_2 PEX_DVDD_2
1uF x 24 1 1 1 1 1 2 1 AB33
AC27 FBVDDQ_3 PEX_DVDD_3
AG24
AH21 +1.8V_GFX_RUN
2.3A(AON+RUN)
CV870
CV871
CV862
CV863
CV872
CV864
CV873
FBVDDQ_4 PEX_DVDD_4
Near: AD27
AE27 FBVDDQ_5 PEX_DVDD_5
AH25
D
22uF x 5 2 2 2 2 2 1 2 AF27 FBVDDQ_6
FBVDDQ_7
Under GPU Near GPU D
10uF x 2 AG27
B13 FBVDDQ_8 PEX_HVDD_0
AG13
AG15
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
DIS@ DIS@ DIS@ DIS@ FBVDDQ_9 PEX_HVDD_1
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
DIS@ DIS@ DIS@ B19 AG16
22U_0603_6.3VAM
22U_0603_6.3VAM
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
E13 FBVDDQ_11 PEX_HVDD_2 AG18
FBVDDQ_12 PEX_HVDD_3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1
E19 AG25
CV874
CV875
CV877
CV9348
CV9349
CV9350
CV9351
CV9352
CV9353
CV9354
CV9355
CV9356
CV9357
CV9358
CV878
CV879
CV9359
CV9360
CV880
CV881
CV9361
CV882
H10 FBVDDQ_14 PEX_HVDD_4 AH15
H11 FBVDDQ_15 PEX_HVDD_5 AH18
H12 FBVDDQ_16 PEX_HVDD_6 AH26 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 2 2
+1.35VSDGPU H13 FBVDDQ_17 PEX_HVDD_7 AH27
Under GPU(below 150mils) H14 FBVDDQ_18
FBVDDQ_19
PEX_HVDD_8
PEX_HVDD_9
AJ27 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
DIS@ DIS@ DIS@
H18 AK27 DIS@ DIS@
H19 FBVDDQ_22 PEX_HVDD_10 AL27
10U_0603_6.3V6M
10U_0603_6.3V6M
DIS@ DIS@ DIS@

FBVDDQ_23 PEX_HVDD_11
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
H20 AM28
H21 FBVDDQ_24 PEX_HVDD_12 AN28
2 2 1 1 1 1 1 1 1 1 1 1 1 1
POWER
FBVDDQ_25 PEX_HVDD_13
H22
+1.8V_GFX_RUN +1.8V_GFX_RUN
CV883
CV884
CV885
CV886
CV887
CV888
CV889
CV890
CV9307
CV9308
CV9309
CV9310
CV9311
CV9312
H23 FBVDDQ_26 +1.8V_GFX_RUN
1 1 2 2 2 2 2 2 2 2 2 2 2 2
H24 FBVDDQ_27
FBVDDQ_28 +PEX_PLL_HVDD
Near GPU RV597 Please Under GPU: Under:
H8 AH12 1 @ 2 0_0603_5%
H9 FBVDDQ_29
FBVDDQ_30
PEX_PLL_HVDD 0.47uF x 13 1uF x 14
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ +FP_FUSE_GPU
4.7uF x 3 4.7uF x 3
1U_0201_4VAM
L27
DIS@ DIS@ M27 FBVDDQ_31
1
N27 FBVDDQ_32 AG12 Near: Near:
CV891
P27 FBVDDQ_33 FP_FUSE_SRC
R27 FBVDDQ_34 10uF x 3 10uF x 3 2.3A(AON+RUN)
+1.35VSDGPU
T27 FBVDDQ_35
FBVDDQ_36
150mA
+PEX_PLL_VDD
2
22uF x 2 22uF x 2 +1.8V_GFX_AON
T30 AG26
Under GPU(below 150mils) T33 FBVDDQ_37 NC T4994 PAD~DTP@ DIS@ Under GPU.J8/K8 Near GPU.J8/K8
Y27 FBVDDQ_38 +1.8V_GFX_AON
FBVDDQ_43
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
1U_0201_4VAM
J8
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
1V8_AON K8
2 2 1 1 1 1 1 1 1 1 1 1 1 1 1V8_AON 1 1 1 1 1 1 1 1 1 1 1 1 1
L8
CV896
CV897
CV898
CV899
CV900
CV901
CV902
CV903
CV9313
CV9314
CV9315
CV9316
CV9317
CV9318
CV892
CV893
CV9364
CV9365
CV9366
CV9367
CV9368
CV9369
CV9371
CV9370
CV9372
CV894
CV895
B16 NC M8
C
E16 FBVDDQ NC C
1 1 2 2 2 2 2 2 2 2 2 2 2 2 H15 FBVDDQ 2 2 2 2 2 2 2 2 2 2 2 2 2
H16 FBVDDQ
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ V27 FBVDDQ AH8 DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
DIS@ DIS@ W27 FBVDDQ IFPAB_PLLVDD AJ8 DIS@ DIS@ DIS@
W30 FBVDDQ IFPAB_RSET
W33 FBVDDQ
FBVDDQ AF7
IFPCD_PLLVDD AF8
IFPCD_RSET +1.8V_GFX_AON
IFPE_PLLVDD
AB8
AD6
1.8V_GFX_AON
W=10mils F1 IFPE_RSET
Under:
0.1U_0402_10V7K
1U_0201_6.3V6M
4.7U_0402_6.3V6M
<96> FBVDDQ_SENSE FBVDDQ_SENSE 1 1 1
CV794
CV796
CV798
1uF x 4
+1.35VSDGPU F2
PROBE_FB_GND IFP_IOVDD
AG8
AG9 2 2 2 Near:
RV600 1 DIS@ 2 40.2_0402_1% J27
IFP_IOVDD
AF6
4.7uF x 3
CALIBRATION PIN GDDR5
FB_CAL_PD_VDDQ IFP_IOVDD
IFP_IOVDD
AG6 DIS@ DIS@ 1uF x 6
DIS@
RV601 1 DIS@ 2 40.2_0402_1% H27 AC7
FB_CAL_x_PD_VDDQ 40.2 ohm FB_CAL_PU_GND IFP_IOVDD AC8
IFP_IOVDD
FB_CAL_x_PU_GND 40.2 ohm RV602 1 DIS@ 2 40.2_0402_1% H25
FB_CAL_TERM_GND AG7
FB_CAL_xTERM_GND 60.4 ohm NC Under GPU Near GPU
AN2
NC
Place near balls
N18P-G0_FCBGA960~D
GPU@
GPU Power Up Sequence GPU GC6 Entry Sequence GPU GC6 Exit Sequence GPU Power Down Sequence
B B
+1.8V_GFX_AON FB_CKE Normal Self-Refresh Self-Refresh Normal +GPU_CORE_VDDS
1V8_MAIN_EN
PXE_Link Active XXX XXX Detect Train +GPU_CORE
+1.8V_GFX_RUN
DGPU_PEX_RST# all other power rails
+GPU_CORE
GPU_GC6_FB_EN
+GPU_CORE_VDDS
+1VS_GFX 1V8_MAIN_EN 40us < T1 < 4ms
+1.35V_GPU
ALL_GPWRGD
T1 < 4ms
A A
The ramp time for any rail must be more than 40us and less than 2ms. GPU_EVENT# 1us < T0
The entire entry/exit sequence must complete within 200 ms.

P029-N18P_Power
0.4(X03)
5 4 3 2 1
5 4 3 2 1
+1.8V_PLLVDD
Under: UV18F
1uF x 4
Near: +GPU_CORE A2
Part 6 of 7
D2
4.7uF x 1 47A +GPU_CORE UV18G AA17 GND_0
GND_1
GND_100
GND_101
D31
AA18 D33
22uF x 1 +1.8V_PLLVDD AA20 GND_2 GND_102 E10
30Ω x 1 Under
+XS_PLLVDD
AA14
VDD_1
Part 7 of 7
VDD_56
V17 AA22 GND_3
GND_4
GND_103
GND_104
E22
<27> +XS_PLLVDD RV575 1 @ 2 0_0402_5% AA21 V20 AB12 E25
AB13 VDD_4 VDD_58 V22 AB14 GND_5 GND_105 E5
AB15 VDD_6 VDD_59 W12 AB16 GND_6 GND_106 E7
1U_0201_4VAM
AB17 VDD_7 VDD_60 W16 AB19 GND_7 GND_107 F28
1 VDD_8 VDD_62 GND_8 GND_108
AB18 W19 AB2 F7
CV851
AB20 VDD_9 VDD_63 W23 AB21 GND_9 GND_109 G10
AB22 VDD_10 VDD_65 Y13 A33 GND_10 GND_110 G13
D 2 AC12 VDD_11 VDD_66 Y15 AB23 GND_11 GND_111 G16 D
AC16 VDD_12 VDD_67 Y17 AB28 GND_12 GND_112 G19
DIS@ AC19 VDD_14 VDD_68 Y18 AB30 GND_13 GND_113 G2
AC23 VDD_15 VDD_69 Y20 AB32 GND_14 GND_114 G22
M12 VDD_17 VDD_70 Y22 AB5 GND_15 GND_115 G25
M16 VDD_18 VDD_71 AB7 GND_16 GND_116 G28
M19 VDD_20 AC13 GND_17 GND_117 G3
M23 VDD_21
VDD_23
W=10mils
VDDS_SENSE_VGA
AC15 GND_18
GND_19
GND_118
GND_119
G30
N13 U1 AC17 G32
+1.8V_PLLVDD VDD_24 RSVD_VDDS_SENSE GNDS_SENSE_VGA T6010 PAD~D @ GND_20 GND_120
N15 U2 AC18 G33
VDD_25 RSVD_GNDS_SENSE T6011 PAD~D @ GND_21 GND_121
N17 AA13 G5
+GPCPLL_AVDD RV574 1 @ 2 0_0402_5% N18 VDD_26 AC20 GND_22 GND_122 G7
<27> +GPCPLL_AVDD VDD_27 GND_23 GND_123
N20 +GPU_CORE AC22 K2
N22 VDD_28 U4 AE2 GND_24 GND_124 K28
1U_0201_4VAM
22U_0603_6.3VAM
4.7U_0402_6.3V6M
P14 VDD_29 XVDD_4 U5 AE28 GND_25 GND_125 K30

1 1 1
POWER
P21 VDD_31 XVDD_5 U6 AE30 GND_26 GND_126 K32
CV850
CV1051
CV1050
R13 VDD_34 XVDD_6 U7 AE32 GND_27 GND_127 K33

R15 VDD_36 XVDD_7 U8 AE33 GND_28 GND_128 K5
2 2 2 R17 VDD_37 XVDD_8 AE5 GND_29 GND_129 K7
DIS@ DIS@ R18 VDD_38 AE7 GND_30 GND_130 M13
DIS@ R20 VDD_39 V1 AH10 GND_31 GND_131 M15
R22 VDD_40 XVDD_9 V2 AA15 GND_32 GND_132 M17
T12 VDD_41 XVDD_10 V3 AH13 GND_33 GND_133 M18
T23 VDD_45 XVDD_13 V6 AH2 GND_36 GND_136 N12
Under Near GPU U13 VDD_47
VDD_48
XVDD_14
XVDD_15
V7 AH22 GND_37
GND_38
GND_137
GND_138
N14
U15 V8 AH24 N16
U18 VDD_49 XVDD_16 AH28 GND_39 GND_139 N19
+1.8V_PLLVDD U20 VDD_51 W2 AH29 GND_40 GND_140 N2
+VID_PLLVDD
Under U22 VDD_52
VDD_53
XVDD_17
XVDD_18
W3 AH30 GND_41
GND_42
GND_141
GND_142
N21
<27> +VID_PLLVDD RV582 1 @ 2 0_0402_5% V13 W4 AH32 N23
V15 VDD_54 XVDD_19 W5 AH33 GND_43 GND_143 N28
VDD_55 XVDD_20 W7 AH5 GND_44 GND_144 N30
GND
1U_0201_4VAM
+GPU_CORE XVDD_21 W8 AH7 GND_45 GND_145 N32

1 XVDD_22 GND_46 GND_146
AJ7 N33
CV854
AK10 GND_47 GND_147 N5

AA12 AK7 GND_48 GND_148 N7
C C
2 AA16 VDD_72 Y1 AL12 GND_49 GND_149 P13
AA19 VDD_73 XVDD_20 Y2 AL14 GND_50 GND_150 P15
DIS@ AA23 VDD_74 XVDD_21 Y3 AL15 GND_51 GND_151 P17
AC14 VDD_75 XVDD_22 Y4 AL17 GND_52 GND_152 P18
AC21 VDD_76 XVDD_23 Y5 AL18 GND_53 GND_153 P20
M14 VDD_77 XVDD_24 Y6 AL2 GND_54 GND_154 P22
M21 VDD_78 XVDD_25 Y7 AL20 GND_55 GND_155 R12
P12 VDD_79 XVDD_26 Y8 AL21 GND_56 GND_156 R14
P16 VDD_80 XVDD_27 AL23 GND_57 GND_157 R16
+1.8V_PLLVDD P19 VDD_81 AL24 GND_58 GND_158 R19
Under
+SP_PLLVDD
P23 VDD_82
VDD_83 XVDD_28
AA1 AL26 GND_59
GND_60
GND_159
GND_160
R21
<27> +SP_PLLVDD RV576 1 @ 2 0_0402_5% T14 AA2 AL28 R23
T21 VDD_84 XVDD_29 AA3 AL30 GND_61 GND_161 T13
U17 VDD_85 XVDD_30 AA4 AL32 GND_62 GND_162 T15
1U_0201_4VAM
V18 VDD_86 XVDD_31 AA5 AL33 GND_63 GND_163 T17

1 VDD_87 XVDD_32 GND_64 GND_164
W14 AA6 AL5 T18
CV852
W21 VDD_88 XVDD_33 AA7 AM13 GND_65 GND_165 T2

VDD_89 XVDD_34 AA8 AM16 GND_66 GND_166 T20
2 DIS@ XVDD_35 AM19 GND_67 GND_167 T22
AM22 GND_68 GND_168 AG11
AB11 R11 AM25 GND_69 GND_169 T28
AB24 VDD_90 VDD_106 R24 AN1 GND_70 GND_170 T32
AD11 VDD_91 VDD_107 U11 AN10 GND_71 GND_171 T5
AD13 VDD_92 VDD_108 U24 AN13 GND_72 GND_172 T7
AD15 VDD_93 VDD_109 V11 AN16 GND_73 GND_173 U12
AD17 VDD_94 VDD_110 V24 AN19 GND_74 GND_174 U14
AD18 VDD_95 VDD_111 Y11 AN22 GND_75 GND_175 U16
AD20 VDD_96 VDD_112 Y24 AN25 GND_76 GND_176 U19
AD22 VDD_97 VDD_113 AN30 GND_77 GND_177 U21
+1.8V_PLLVDD +1.8V_GFX_RUN AD24 VDD_98 AN34 GND_78 GND_178 U23
L11 VDD_95 AN4 GND_79 GND_179 V12
Near LV23 1 DIS@ 2 PBY160808T-300Y-N_2P L13 VDD_96
VDD_97
AN7 GND_80
GND_81
GND_180
GND_181
V14
L15 AP2 V16
L17 VDD_98 AP33 GND_82 GND_182 V19
30 ohm
10U_0402_6.3V6M
VDD_99 GND_83 GND_183

22U_0402_6.3V6M
1 1 L18 B1 V21
VDD_100 GND_84 GND_184
(ESR=0.03) Bead L20 B10 V23
CV855
L22 VDD_101 B22 GND_85 GND_185 W13

CV856
B
L24 VDD_102 B25 GND_86 GND_186 W15 B
2 2 N11 VDD_103 B28 GND_87 GND_187 W17
DIS@ DIS@ N24 VDD_104 B31 GND_88 GND_188 W18
VDD_105 B34 GND_89 GND_189 W20
B4 GND_90 GND_190 W22
B7 GND_91 GND_191 W28
N18P-G0_FCBGA960~D C10 GND_92 GND_192 Y12
C13 GND_93 GND_193 Y14
GPU@
C19 GND_94 GND_194 Y16
C22 GND_95 GND_195 Y19
C25 GND_96 GND_196 Y21
C28 GND_97 GND_197 Y23
C7 GND_98 GND_198
GND_99
L21 AA11
L23 GND_214 GND_200 AA24
M11 GND_215 GND_201 AC11
M24 GND_216 GND_202 AC24
P11 GND_217 GND_203 AD12
T11 GND_218 GND_204 AD14
T24 GND_219 GND_205 AD16
W11 GND_220 GND_206 AD19
W24 GND_221 GND_207 AD21
P24 GND_222 GND_208 AD23
GND_223 GND_209 L12
GND_210 L14
GND_211 L16
GND_212 L19
GND_213
AH11
NC
1
C16
GND_OPT W32 @
GND_OPT RV1973
N18P-G0_FCBGA960~D 0_0402_5%
GPU@
2
A A

P030-N18P_VGA CORE/GND
0.4(X03)
5 4 3 2 1
5 4 3 2 1
UV18B
Part 2 of 7 UV18C
L28 U30
<35> FB_A_D0 FBA_D0 FBA_CMD0 FB_A_CMD0 <35>
M29 T31 Part 3 of 7
<35> FB_A_D1 FBA_D1 FBA_CMD1 FB_A_CMD1 <35>
L29 U29 G9 D13
<35> FB_A_D2 FBA_D2 FBA_CMD2 FB_A_CMD2 <35> <36> FB_B_D0 FBB_D0 FBB_CMD0 FB_B_CMD0 <36>
M28 R34 E9 E14
N31 R33 G8 F14
P29 U32 F9 A12
D R29 U33 F11 B12 D
P28 U28 G11 C14
J28 V28 F12 B14
H29 V29 G12 G15
J29 V30 G6 F15
H28 U34 F5 E15
G29 U31 E6 D15
E31 V34 F6 A14
E32 V33 F4 D14
F30 Y32 G4 A15
C34 AA31 E2 B15
D32 AA29 F3 C17
B33 AA28 C2 D18
C33 AC34 D4 E18
F33 AC33 D3 F18
F32 AA32 C1 A20
H33 AA33 B3 B20
H32 Y28 C4 C18
P34 Y29 B5 B18
P32 W31 C5 G18
P31 Y30 A11 G17
P33 AA34 C11 F17
L31 Y31 D11 D16
L34 Y34 B11 A18
L32 Y33 D8 D17
L33 V31 A8 A17
MEMORY INTERFACE B
<35> FB_A_D31 FBA_D31 FBA_CMD31 FB_A_CMD31 <35> +1.35VSDGPU <36> FB_B_D29 FBB_D29 FBB_CMD29 FB_B_CMD29 <36>
AG28 R28 C8 B17
AF29 AC28 B8 E17
<35> FB_A_D33 FBA_D33 FBA_CMD33 FBA_DEBUG0 FB_A_CMD33 <35> <36> FB_B_D31 FBB_D31 FBB_CMD31 FB_B_CMD31 <36>
AG29 R32 F24 G14
<35> FB_A_D34 FBA_D34 FBA_CMD34 FBA_DEBUG1 FBA_DEBUG0 RV2003 2 DIS@ <36> FB_B_D32 FBB_D32 FBB_CMD32 FB_B_CMD32 <36>
AF28 AC32 T6017 PAD~DTP@ 1 60.4_0201_1% G23 G20
<35> FB_A_D35 FBA_D35 FBA_CMD35 FBA_DEBUG1 RV2002 2 DIS@ <36> FB_B_D33 FBB_D33 FBB_CMD33 FBB_DEBUG0 FB_B_CMD33 <36>
AD30 T6016 PAD~DTP@ 1 60.4_0201_1% E24 C12
<35> FB_A_D36 FBA_D36 <36> FB_B_D34 FBB_D34 FBB_CMD34 FBB_DEBUG1
AD29 G24 C20 T6019 PAD~DTP@
<35> FB_A_D37 FBA_D37 <36> FB_B_D35 FBB_D35 FBB_CMD35
C AC29 D21 T6018 PAD~DTP@ C
<35> FB_A_D38 FBA_D38 <36> FB_B_D36 FBB_D36
AD28 E21
<35> FB_A_D39 FBA_D39 <36> FB_B_D37 FBB_D37 +1.35VSDGPU
AJ29 G21
AK29 F21
AJ30 G27
<35> FB_A_D42 FBA_D42 <36> FB_B_D40 FBB_D40 FBB_DEBUG0 RV2008 2 DIS@
AK28 D27 1 60.4_0201_1%
<35> FB_A_D43 <36> FB_B_D41
MEMORY INTERFACE
AM29 FBA_D43 G26 FBB_D41 FBB_DEBUG1 RV2009 2 DIS@ 1 60.4_0201_1%

AM31 R30 E27
<35> FB_A_D45 FBA_D45 FBA_CLK0 FB_A_CLK0 <35> <36> FB_B_D43 FBB_D43
AN29 R31 E29
<35> FB_A_D46 FBA_D46 FBA_CLK0_N FB_A_CLK#0 <35> <36> FB_B_D44 FBB_D44
AM30 AB31 F29 D12
<35> FB_A_D47 FBA_D47 FBA_CLK1 FB_A_CLK1 <35> <36> FB_B_D45 FBB_D45 FBB_CLK0 FB_B_CLK0 <36>
AN31 AC31 E30 E12
<35> FB_A_D48 FBA_D48 FBA_CLK1_N FB_A_CLK#1 <35> <36> FB_B_D46 FBB_D46 FBB_CLK0_N FB_B_CLK#0 <36>
AN32 D30 E20
<35> FB_A_D49 FBA_D49 <36> FB_B_D47 FBB_D47 FBB_CLK1 FB_B_CLK1 <36>
AP30 A32 F20
<35> FB_A_D50 FBA_D50 <36> FB_B_D48 FBB_D48 FBB_CLK1_N FB_B_CLK#1 <36>
AP32 C31
AM33 K31 C32
<35> FB_A_D52 FBA_D52 FBA_WCK01 FB_A_WCK01 <35> <36> FB_B_D50 FBB_D50
AL31 L30 B32
<35> FB_A_D53 FBA_D53 FBA_WCK01_N FB_A_WCK01# <35> <36> FB_B_D51 FBB_D51
AK33 H34 D29 F8
<35> FB_A_D54 FBA_D54 FBA_WCK23 FB_A_WCK23 <35> <36> FB_B_D52 FBB_D52 FBB_WCK01 FB_B_WCK01 <36>
AK32 J34 A29 E8
<35> FB_A_D55 FBA_D55 FBA_WCK23_N FB_A_WCK23# <35> <36> FB_B_D53 FBB_D53 FBB_WCK01_N FB_B_WCK01# <36>
AD34 AG30 C29 A5
AD32 AG31 B29 A6
AC30 AJ34 B21 D24
A
AD33 AK34 C23 D25

AF31 A21 B27
<35> FB_A_D60 FBA_D60 <36> FB_B_D58 FBB_D58 FBB_WCK67 FB_B_WCK67 <36>
AG34 C21 C27
<35> FB_A_D61 FBA_D61 <36> FB_B_D59 FBB_D59 FBB_WCK67_N FB_B_WCK67# <36>
AG32 B24
AG33 J30 C24
<35> FB_A_D63 FBA_D63 FBA_WCKB01 FB_A_WCKB01 <35> <36> FB_B_D61 FBB_D61
P30 FBA_WCKB01_N
J31
J32
FB_A_WCKB01# <35> +FB_PLLAVDD <36> FB_B_D62
B26
C26 FBB_D62 D6
<35> FB_A_DBI0 FB_A_WCKB23 <35> <36> FB_B_D63 FB_B_WCKB01 <36>
<35> FB_A_DBI1
F31
F34
FBA_DQM0
FBA_DQM1
FBA_WCKB23
FBA_WCKB23_N
J33
AH31
FB_A_WCKB23# <35> Under: E11
FBB_D63 FBB_WCKB01
FBB_WCKB01_N
D7
C6
FB_B_WCKB01# <36>
<35>
<35>
FB_A_DBI2
FB_A_DBI3
M32 FBA_DQM2
FBA_DQM3
FBA_WCKB45
FBA_WCKB45_N
AJ31
FB_A_WCKB45
FB_A_WCKB45#
<35>
<35>
1uF x 3 <36>
<36>
FB_B_DBI0
FB_B_DBI1
E3 FBB_DQM0
FBB_DQM1
FBB_WCKB23
FBB_WCKB23_N
B6
FB_B_WCKB23
FB_B_WCKB23#
<36>
<36>
B
<35> FB_A_DBI4
AD31
AL29 FBA_DQM4 FBA_WCKB67
AJ32
AJ33
FB_A_WCKB67 <35> Near: <36> FB_B_DBI2
A3
C9 FBB_DQM2 FBB_WCKB45
F26
E26
FB_B_WCKB45 <36> B
<35> FB_A_DBI5 FB_A_WCKB67# <35> <36> FB_B_DBI3 FB_B_WCKB45# <36>
<35> FB_A_DBI6
AM32
AF34
FBA_DQM5
FBA_DQM6
FBA_WCKB67_N
4.7uF x 2 <36> FB_B_DBI4
F23
F27
FBB_DQM3
FBB_DQM4
FBB_WCKB45_N
FBB_WCKB67
A26
A27
FB_B_WCKB67 <36>
<35> FB_A_DBI7 FBA_DQM7
+FB_PLLAVDD
22uF x 1 <36>
<36>
FB_B_DBI5
FB_B_DBI6
C30 FBB_DQM5
FBB_DQM6
FBB_WCKB67_N FB_B_WCKB67# <36>
<35> FB_A_EDC0
M31
G31 FBA_DQS_WP0 30Ω x 1 <36> FB_B_DBI7
A24
FBB_DQM7
<35> FB_A_EDC1 FBA_DQS_WP1
E33 D10
<35>
<35>
FB_A_EDC2
FB_A_EDC3
M33 FBA_DQS_WP2
FBA_DQS_WP3
DIS@ 50mA +FB_PLLAVDD
<36>
<36>
FB_B_EDC0
FB_B_EDC1
D5 FBB_DQS_WP0
FBB_DQS_WP1
AE31 K27 CV921 1 2 1U_0201_4VAM C3
<35> FB_A_EDC4 FBA_DQS_WP4 FB_REFPLL_AVDD <36> FB_B_EDC2 FBB_DQS_WP2
AK30 B9
<35> FB_A_EDC5 FBA_DQS_WP5 <36> FB_B_EDC3 FBB_DQS_WP3
AN33 E23 H17
<35>
<35>
FB_A_EDC6
FB_A_EDC7
AF33 FBA_DQS_WP6
FBA_DQS_WP7
Under GPU +1.8V_GFX_RUN <36>
<36>
FB_B_EDC4
FB_B_EDC5
E28 FBB_DQS_WP4
FBB_DQS_WP5
FBB_PLL_AVDD +FB_PLLAVDD
U27 LV24 1 2 PBY160808T-300Y-N_2P B30
M30 FBA_PLL_AVDD
DIS@ <36> FB_B_EDC6
A23 FBB_DQS_WP6 1 1
120mA
H30 RES 120mA <36> FB_B_EDC7 FBB_DQS_WP7
CV9379 CV9319
E34 RES
RES
1
CV923
1
CV9320
1
CV924 300mA D9
RES 2
DIS@
1U_0201_4VAM
2
DIS@
4.7U 6.3V M X6S 0402
M34 H31 DIS@ DIS@ DIS@ E4
AF30 RES FB_VREF 1U_0201_4VAM 4.7U 6.3V M X6S 0402 22U_0603_6.3VAM B2 RES
AK31 RES 2 2 2 A9 RES
RES RES
1
AM34 D22
AF32 RES
RES
DIS@ D28 RES
RES
Under GPU
A30
RV1988
1K_0402_1% Under GPU B23 RES
RES
2
N18P-G0_FCBGA960~D
GPU@
N18P-G0_FCBGA960~D
GPU@
A A

P031-N18P_MEM Interface

5 4 3 2 1
Vinafix.com
5 4 3 2 1
D D
C C
B B
A A
P032-Reserve
0.4(X03)
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Title
P033-Reserve
Size Document Number Rev

Vinafix.com A LA-J191P 0.4(X03)

5 4 3 2 1
5 4 3 2 1
SMB_ALT_ADDR State DEVID_SEL State PCIE_CFG State VGA_DEVICE State

Low Single GPU Low Original Device Low Normal signal swing Low 3D Device
+1.8V_GFX_AON
High Dual GPU High ID
Re-brand Device ID High Reduce the signal High VGA Device
amplitude
1
DIS@
RV1080
0_0201_5%
2
2
2
@ @ @
D D
RV639 RV640 RV641
100K_0201_5% 10K_0201_5% 100K_0201_5%
1
ROM_SI
<28> ROM_SI ROM_SO
<28> ROM_SO ROM_SCLK
<28> ROM_SCLK
2
2
2
DIS@ DIS@ DIS@
RV642 RV643 RV644
100K_0201_5% 10K_0201_5% 100K_0201_5%
1
1
1
+1.8V_GFX_AON
2
2
@ @ @ @ @ @
RV645 RV646 RV647 RV648 RV649 RV650
100K_0201_5% 100K_0201_5% 100K_0201_5% 100K_0201_5% 100K_0201_5% 100K_0201_5%
1
1
<28> STRAP0 STRAP0
<28> STRAP1 STRAP1
<28> STRAP2 STRAP2
<28> STRAP3 STRAP3
C <28> STRAP4 STRAP4 C
<28> STRAP5 STRAP5
2
@ @ @ DIS@ DIS@ DIS@

RV651 RV652 RV653 RV654 RV655 RV656
100K_0201_5% 100K_0201_5% 100K_0201_5% 100K_0201_5% 100K_0201_5% 100K_0201_5%
1
B B
A A

P034-N18P_MISC
C 0.4(X03)
5 4 3 2 1
5 4 3 2 1
Memory Part i t i on A- L ower 32 bi t UV23
MF=0
UV24
<31> FB_A_EDC0
C2
EDC0_A DQ0_A
B4
FB_A_D2 <31> <31> FB_A_EDC5
C2
EDC0_A
MF=1 DQ0_A
B4
FB_A_D40 <31>
C13 A3 C13 A3
<31> FB_A_EDC1 EDC1_A DQ1_A FB_A_D3 <31> <31> FB_A_EDC4 EDC1_A DQ1_A FB_A_D41 <31>
T2 B3 T2 B3
<31> FB_A_EDC3 EDC0_B DQ2_A FB_A_D0 <31> <31> FB_A_EDC6 EDC0_B DQ2_A FB_A_D42 <31>
T13 B2 BYTE0 T13 B2
<31> FB_A_EDC2 EDC1_B DQ3_A FB_A_D1 <31> <31> FB_A_EDC7 EDC1_B DQ3_A FB_A_D43 <31>
E3 E3 BYTE5
DQ4_A FB_A_D4 <31> DQ4_A FB_A_D45 <31>
E2 E2
DQ5_A FB_A_D7 <31> DQ5_A FB_A_D44 <31>
D2 F2 D2 F2
<31> FB_A_DBI0 DBI0#_A DQ6_A FB_A_D5 <31> <31> FB_A_DBI5 DBI0#_A DQ6_A FB_A_D47 <31>
D13 G2 D13 G2
<31> FB_A_DBI1 DBI1#_A DQ7_A FB_A_D6 <31> <31> FB_A_DBI4 DBI1#_A DQ7_A FB_A_D46 <31>
R2 B11 R2 B11
<31> FB_A_DBI3 DBI0#_B DQ8_A FB_A_D10 <31> <31> FB_A_DBI6 DBI0#_B DQ8_A FB_A_D34 <31>
R13 A12 R13 A12
<31> FB_A_DBI2 DBI1#_B DQ9_A FB_A_D9 <31> <31> FB_A_DBI7 DBI1#_B DQ9_A FB_A_D35 <31>
B12 B12
DQ10_A FB_A_D8 <31> DQ10_A FB_A_D32 <31>
B13 BYTE1 B13 BYTE4
DQ11_A FB_A_D11 <31> DQ11_A FB_A_D33 <31>
J10 E12 J10 E12
<31> FB_A_CLK0 CK_T DQ12_A FB_A_D12 <31> <31> FB_A_CLK1 CK_T DQ12_A FB_A_D36 <31>
K10 E13 K10 E13
<31> FB_A_CLK#0 FB_A_CMD7 CK_C DQ13_A FB_A_D14 <31> <31> FB_A_CLK#1 FB_A_CMD33 G10 CK_C DQ13_A FB_A_D37 <31>
G10 F13 F13
<31> FB_A_CMD7 CKE#_A DQ14_A FB_A_D15 <31> <31> FB_A_CMD33 CKE#_A DQ14_A FB_A_D38 <31>
M10 G13 M10 G13
D CKE#_B DQ15_A FB_A_D13 <31> CKE#_B DQ15_A FB_A_D39 <31> D
U4 U4
DQ0_B FB_A_D25 <31> DQ0_B FB_A_D50 <31>
V3 V3
DQ1_B FB_A_D27 <31> DQ1_B FB_A_D49 <31>
U3 U3
DQ2_B FB_A_D26 <31> DQ2_B FB_A_D48 <31>
J5 U2 BYTE3 J5 U2
<31> FB_A_CMD8 CABI#_A DQ3_B FB_A_D24 <31> <31> FB_A_CMD30 CABI#_A DQ3_B FB_A_D51 <31>
K5 P3 K5 P3 BYTE6
CABI#_B DQ4_B FB_A_D31 <31> CABI#_B DQ4_B FB_A_D52 <31>
P2 P2
DQ5_B FB_A_D29 <31> DQ5_B FB_A_D53 <31>
N2 N2
DQ6_B FB_A_D28 <31> DQ6_B FB_A_D54 <31>
M2 M2
DQ7_B FB_A_D30 <31> DQ7_B FB_A_D55 <31>
U11 U11
DQ8_B FB_A_D17 <31> DQ8_B FB_A_D58 <31>
V12 V12
FBA_ZQ_LWR_A DQ9_B FB_A_D16 <31> FBA_ZQ_UPR_A DQ9_B FB_A_D60 <31>
RV619 2 DIS@ 1 121_0402_1% J14 U12 RV620 2 DIS@ 1 121_0402_1% J14 U12
FBA_ZQ_LWR_B ZQ_A DQ10_B FB_A_D18 <31> FBA_ZQ_UPR_B ZQ_A DQ10_B FB_A_D57 <31>
RV617 2 DIS@ 1 121_0402_1% K14 U13 BYTE2 RV618 2 DIS@ 1 121_0402_1% K14 U13
ZQ_B DQ11_B FB_A_D19 <31> ZQ_B DQ11_B FB_A_D59 <31>
P12 P12 BYTE7
DQ12_B FB_A_D21 <31> DQ12_B FB_A_D56 <31>
P13 P13
DQ13_B FB_A_D20 <31> DQ13_B FB_A_D61 <31>
N13 N13
DQ14_B FB_A_D22 <31> DQ14_B FB_A_D63 <31>
M13 M13
DQ15_B FB_A_D23 <31> DQ15_B FB_A_D62 <31>
N5 H3 N5 H3
TCK CA0_A FB_A_CMD13 <31> TCK CA0_A FB_A_CMD29 <31>
F10 G11 F10 G11
TDI CA1_A FB_A_CMD15 <31> TDI CA1_A FB_A_CMD31 <31>
N10 G4 N10 G4
TDO CA2_A FB_A_CMD0 <31> TDO CA2_A FB_A_CMD16 <31>
F5 H12 F5 H12
TMS CA3_A FB_A_CMD11 FB_A_CMD9 <31> TMS CA3_A FB_A_CMD22 FB_A_CMD25 <31>
H5 H5
CA4_A FB_A_CMD12 FB_A_CMD11 <31> CA4_A FB_A_CMD21 FB_A_CMD22 <31>
H10 H10
J12 J12
J11 J11
J4 J4
J3 J3
CA9_A FB_A_CMD5 <31> CA9_A FB_A_CMD17 <31>
L3 L3
CA0_B FB_A_CMD10 <31> CA0_B FB_A_CMD27 <31>
D4 M11 D4 M11
<31> FB_A_WCK01 WCK_T_A CA1_B FB_A_CMD1 <31> <31> FB_A_WCKB45 WCK_T_A CA1_B FB_A_CMD28 <31>
D5 M4 D5 M4
<31> FB_A_WCK01# WCK_C_A CA2_B FB_A_CMD32 <31> <31> FB_A_WCKB45# WCK_C_A CA2_B FB_A_CMD19 <31>
R11 L12 R11 L12
<31> FB_A_WCK23 WCK_T_B CA3_B FB_A_CMD11 FB_A_CMD14 <31> <31> FB_A_WCKB67 WCK_T_B CA3_B FB_A_CMD22 FB_A_CMD20 <31>
R10 L5 R10 L5
<31> FB_A_WCK23# WCK_C_B CA4_B FB_A_CMD12 <31> FB_A_WCKB67# WCK_C_B CA4_B FB_A_CMD21
L10 L10
CA5_B K12 FB_A_CMD3 CA5_B K12 FB_A_CMD24
C +FBA_VREFC0 K1 CA9_B +FBA_VREFC0 K1 CA9_B C
VREFC +1.35VSDGPU VREFC +1.35VSDGPU
C1 C1
FB_A_CMD2 J1 VDDQ1 E1 FB_A_CMD18 J1 VDDQ1 E1
<31> FB_A_CMD2 RESET# VDDQ2 <31> FB_A_CMD18 RESET# VDDQ2
H1 H1
MEM_VREF levels VDDQ3 L1
1
CV926 VDDQ3 L1
B1 VDDQ4 P1 B1 VDDQ4 P1
70% of rail Terminat i on Enabl e D1 VSS1 VDDQ5 T1
@DIS@
820P_0402_25V7 D1 VSS1 VDDQ5 T1
F1 VSS2 VDDQ6 J2 2 F1 VSS2 VDDQ6 J2
50% of rail Terminat i on Disabl e G1 VSS3 VDDQ7 K2 G1 VSS3 VDDQ7 K2
+1.35VSDGPU M1 VSS4 VDDQ8 C4 M1 VSS4 VDDQ8 C4
N1 VSS5
VSS6
VDDQ9
VDDQ10
F4 CRB 10nF N1 VSS5
VSS6
VDDQ9
VDDQ10
F4
R1 N4 R1 N4
VSS7 VDDQ11 VSS7 VDDQ11
1
U1 T4 U1 T4
RV623 A2 VSS8 VDDQ12 B5 A2 VSS8 VDDQ12 B5
@DIS@ V2 VSS9 VDDQ13 U5 V2 VSS9 VDDQ13 U5
549_0402_1% C3 VSS10 VDDQ14 B10 C3 VSS10 VDDQ14 B10
D3 VSS11 VDDQ15 U10 +1.35VSDGPU D3 VSS11 VDDQ15 U10
2
F3 C11 F3 C11
RV624 1 @DIS@ 2 931_0402_1% +FBA_VREFC0 G3 VSS13 VDDQ17 F11 G3 VSS13 VDDQ17 F11
+FBA_VREFC0_R
1
M3 N11 M3 N11
W=16mils N3 VSS15
VSS16
VDDQ19
VDDQ20
T11 RV2004 N3 VSS15
VSS16
VDDQ19
VDDQ20
T11
1
1 R3 J13 DIS@ R3 J13

RV625 CV927 T3 VSS17 VDDQ21 K13 10K_0201_1% T3 VSS17 VDDQ21 K13
DIS@ @DIS@ A4 VSS18 VDDQ22 C14 A4 VSS18 VDDQ22 C14
2
1.33K_0402_1% 820P_0402_25V7 E4 E14 E4 E14
2 H4 VSS20 VDDQ24 H14 FB_A_CMD33 H4 VSS20 VDDQ24 H14
2
L4 L14 L4 L14
D VSS22 VDDQ26 FB_A_CMD18 VSS22 VDDQ26
1
P4 P14 P4 P14
2 V4 VSS23 VDDQ27 T14 V4 VSS23 VDDQ27 T14
<27,36> MEM_VREF C5 VSS24 VDDQ28 C5 VSS24 VDDQ28
G QV101
VSS25 VSS25
1
S @DIS@ T5 T5
VSS26 VSS26
3
BSS138W 1N SOT-323-3 C10 A1 RV2005 C10 A1

T10 VSS27 VDD1 V1 DIS@ T10 VSS27 VDD1 V1
A11 VSS28 VDD2 H2 10K_0201_1% A11 VSS28 VDD2 H2
E11 VSS29 VDD3 L2 E11 VSS29 VDD3 L2
VSS30 VDD4 VSS30 VDD4
2
H11 E5 H11 E5
+1.35VSDGPU L11 VSS31 VDD5 P5 L11 VSS31 VDD5 P5
P11 VSS32 VDD6 E10 P11 VSS32 VDD6 E10
V11 VSS33 VDD7 P10 V11 VSS33 VDD7 P10
1
B C12 H13 C12 H13 B

RV2006 D12 VSS35 VDD9 L13 D12 VSS35 VDD9 L13
DIS@ F12 VSS36 VDD10 A14 F12 VSS36 VDD10 A14
10K_0201_1% G12 VSS37 VDD11 V14 G12 VSS37 VDD11 V14
M12 VSS38 VDD12 +1.8V_GFX_AON M12 VSS38 VDD12 +1.8V_GFX_AON
VSS39
+1.35VSDGPU
Under DRAM VSS39
2
N12 N12
FB_A_CMD7 R12 VSS40 A5 R12 VSS40 A5
T12 VSS41 VPP1 V5 T12 VSS41 VPP1 V5
FB_A_CMD2 A13 VSS42 VPP2 A10 A13 VSS42 VPP2 A10
V13 VSS43 VPP3 V10 V13 VSS43 VPP3 V10
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
VSS44 VPP4 1 1 1 1 1 1 1 1 VSS44 VPP4
1
B14 B14
CV929
CV930
CV931
CV932
CV933
CV934
CV9305
CV9306
RV2007 D14 VSS45 R4 D14 VSS45 R4
VSS46 NC1 FB_A_WCKB23 <31> VSS46 NC1 FB_A_WCK67 <31>
DIS@ F14 G5 F14 G5
10K_0201_1% G14 VSS47 NC2 M5 2 2 2 2 2 2 2 2 G14 VSS47 NC2 M5
M14 VSS48 NC3 R5 M14 VSS48 NC3 R5
VSS49 NC4 FB_A_WCKB23# <31> VSS49 NC4 FB_A_WCK67# <31>
2
N14 D10 FB_A_WCKB01# <31>

N14 D10 FB_A_WCK45# <31>
R14 VSS50 NC5 D11 R14 VSS50 NC5 D11
VSS51 NC6 FB_A_WCKB01 <31> DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ VSS51 NC6 FB_A_WCK45 <31>
U14 180-BALL U14 180-BALL
VSS52 SGRAM GDDR6 VSS52 SGRAM GDDR6
+1.35VSDGPU
Around DRAM Close to DRAM
VRAM@ MT61K256M32JE-13-A_FBGA180~D
+1.35VSDGPU
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV117
CV937
CV938
CV939
CV940
CV941
CV942
CV943
CV944
CV945
CV946
CV947
CV948
CV949
CV950
CV951
CV952
CV953
CV954
CV955
CV956
CV957
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV217
CV958
CV959
CV960
CV961
CV962
CV963
CV964
CV965
CV966
CV967
CV968
CV969
CV970
CV971
CV972
CV973
CV974
CV975
CV976
CV977
CV978
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
+1.35VSDGPU
+1.35VSDGPU
Under DRAM +1.35VSDGPU
CRB FBVDDQ_MEM: 22uF*6pcs 10uF*6pcs 0.47uF*36pcs

CRB 1V8_AON:0.47uF *8pcs
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A A
CV979
CV980
CV981
CV982
CV983
CV984
CV985
CV986
CV118
CV119
CV120
CV121
CV122
CV123
CV124
CV125
1 1 1 1 1 1 1 1
CV218
CV219
CV220
CV221
CV222
CV223
CV224
CV225
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

P035-N18P_GDDR5_A

5 4 3 2 1
5 4 3 2 1
Memory Part i t i on A- L ower 32 bi t

UV25 UV26
MF=0 MF=1
C2 B4 C2 B4
<31> FB_B_EDC0 EDC0_A DQ0_A FB_B_D0 <31> <31> FB_B_EDC5 EDC0_A DQ0_A FB_B_D42 <31>
C13 A3 C13 A3
<31> FB_B_EDC1 EDC1_A DQ1_A FB_B_D1 <31> <31> FB_B_EDC4 EDC1_A DQ1_A FB_B_D43 <31>
T2 B3 T2 B3
<31> FB_B_EDC3 EDC0_B DQ2_A FB_B_D2 <31> <31> FB_B_EDC6 EDC0_B DQ2_A FB_B_D40 <31>
T13 B2 BYTE0 T13 B2
<31> FB_B_EDC2 EDC1_B DQ3_A FB_B_D3 <31> <31> FB_B_EDC7 EDC1_B DQ3_A FB_B_D41 <31>
E3 E3 BYTE5
DQ4_A FB_B_D4 <31> DQ4_A FB_B_D44 <31>
E2 E2
DQ5_A FB_B_D5 <31> DQ5_A FB_B_D47 <31>
D2 F2 D2 F2
<31> FB_B_DBI0 DBI0#_A DQ6_A FB_B_D6 <31> <31> FB_B_DBI5 DBI0#_A DQ6_A FB_B_D46 <31>
D13 G2 D13 G2
<31> FB_B_DBI1 DBI1#_A DQ7_A FB_B_D7 <31> <31> FB_B_DBI4 DBI1#_A DQ7_A FB_B_D45 <31>
R2 B11 R2 B11
<31> FB_B_DBI3 DBI0#_B DQ8_A FB_B_D10 <31> <31> FB_B_DBI6 DBI0#_B DQ8_A FB_B_D34 <31>
R13 A12 R13 A12
<31> FB_B_DBI2 DBI1#_B DQ9_A FB_B_D11 <31> <31> FB_B_DBI7 DBI1#_B DQ9_A FB_B_D35 <31>
B12 B12
DQ10_A FB_B_D8 <31> DQ10_A FB_B_D32 <31>
B13 BYTE1 B13
DQ11_A FB_B_D9 <31> DQ11_A FB_B_D33 <31>
J10 E12 J10 E12 BYTE4
<31> FB_B_CLK0 CK_T DQ12_A FB_B_D12 <31> <31> FB_B_CLK1 CK_T DQ12_A FB_B_D36 <31>
K10 E13 K10 E13
<31> FB_B_CLK#0 FB_B_CMD7 CK_C DQ13_A FB_B_D14 <31> <31> FB_B_CLK#1 FB_B_CMD33 CK_C DQ13_A FB_B_D37 <31>
G10 F13 G10 F13
<31> FB_B_CMD7 CKE#_A DQ14_A FB_B_D15 <31> <31> FB_B_CMD33 CKE#_A DQ14_A FB_B_D39 <31>
M10 G13 M10 G13
D CKE#_B DQ15_A FB_B_D13 <31> CKE#_B DQ15_A FB_B_D38 <31> D
U4 U4
DQ0_B FB_B_D26 <31> DQ0_B FB_B_D50 <31>
V3 V3
DQ1_B FB_B_D25 <31> DQ1_B FB_B_D49 <31>
U3 BYTE3 U3
DQ2_B FB_B_D24 <31> DQ2_B FB_B_D51 <31>
J5 U2 J5 U2
<31> FB_B_CMD8 CABI#_A DQ3_B FB_B_D27 <31> <31> FB_B_CMD30 CABI#_A DQ3_B FB_B_D48 <31>
K5 P3 K5 P3 BYTE6
CABI#_B DQ4_B FB_B_D30 <31> CABI#_B DQ4_B FB_B_D52 <31>
P2 P2
DQ5_B FB_B_D28 <31> DQ5_B FB_B_D55 <31>
N2 N2
DQ6_B FB_B_D29 <31> DQ6_B FB_B_D53 <31>
M2 M2
DQ7_B FB_B_D31 <31> DQ7_B FB_B_D54 <31>
U11 U11
DQ8_B FB_B_D18 <31> DQ8_B FB_B_D57 <31>
V12 V12
FBB_ZQ_LWR_A DQ9_B FB_B_D17 <31> FBB_ZQ_UPR_A J14 DQ9_B FB_B_D56 <31>
RV631 2 DIS@ 1 121_0402_1% J14 U12 RV632 2 DIS@ 1 121_0402_1% U12
FBB_ZQ_LWR_B ZQ_A DQ10_B FB_B_D19 <31> FBB_ZQ_UPR_B K14 ZQ_A DQ10_B FB_B_D58 <31>
RV633 2 DIS@ 1 121_0402_1% K14 U13 RV630 2 DIS@ 1 121_0402_1% U13
ZQ_B DQ11_B FB_B_D16 <31> ZQ_B DQ11_B FB_B_D59 <31>
P12 BYTE2 P12 BYTE7
DQ12_B FB_B_D20 <31> DQ12_B FB_B_D61 <31>
P13 P13
DQ13_B FB_B_D21 <31> DQ13_B FB_B_D60 <31>
N13 N13
DQ14_B FB_B_D22 <31> DQ14_B FB_B_D63 <31>
M13 M13
DQ15_B FB_B_D23 <31> DQ15_B FB_B_D62 <31>
N5 H3 N5 H3
TCK CA0_A FB_B_CMD13 <31> TCK CA0_A FB_B_CMD29 <31>
F10 G11 F10 G11
TDI CA1_A FB_B_CMD15 <31> TDI CA1_A FB_B_CMD31 <31>
N10 G4 N10 G4
TDO CA2_A FB_B_CMD0 <31> TDO CA2_A FB_B_CMD16 <31>
F5 H12 F5 H12
TMS CA3_A FB_B_CMD9 <31> TMS CA3_A FB_B_CMD25 <31>
H5 H5
CA4_A FB_B_CMD12 FB_B_CMD11 <31,36> CA4_A FB_B_CMD21 FB_B_CMD22 <31,36>
H10 H10
CA5_A FB_B_CMD3 FB_B_CMD12 <31> CA5_A FB_B_CMD24 FB_B_CMD21 <31>
J12 J12
J11 J11
J4 J4
J3 J3
CA9_A FB_B_CMD5 <31> CA9_A FB_B_CMD17 <31>
L3 L3
CA0_B FB_B_CMD10 <31> CA0_B FB_B_CMD27 <31>
D4 M11 D4 M11
<31> FB_B_WCK01 WCK_T_A CA1_B FB_B_CMD1 <31> <31> FB_B_WCKB45 WCK_T_A CA1_B FB_B_CMD28 <31>
D5 M4 D5 M4
<31> FB_B_WCK01# WCK_C_A CA2_B FB_B_CMD32 <31> <31> FB_B_WCKB45# WCK_C_A CA2_B FB_B_CMD19 <31>
R11 L12 R11 L12
<31> FB_B_WCK23 WCK_T_B CA3_B FB_B_CMD14 <31> <31> FB_B_WCKB67 WCK_T_B CA3_B FB_B_CMD20 <31>
R10 L5 R10 L5
<31> FB_B_WCK23# WCK_C_B CA4_B FB_B_CMD12 FB_B_CMD11 <31,36> <31> FB_B_WCKB67# WCK_C_B CA4_B FB_B_CMD21 FB_B_CMD22 <31,36>
L10 L10
CA5_B K12 FB_B_CMD3 CA5_B K12 FB_B_CMD24
C +FBC_VREFC1 K1 CA9_B +FBC_VREFC1 K1 CA9_B C
VREFC +1.35VSDGPU VREFC +1.35VSDGPU
C1 C1
J1 VDDQ1 E1 J1 VDDQ1 E1
<31> FB_B_CMD2 RESET# VDDQ2 1 <31> FB_B_CMD18 RESET# VDDQ2
H1 CV988 H1
VDDQ3 L1 @DIS@ VDDQ3 L1
B1 VDDQ4 P1 820P_0402_25V7 B1 VDDQ4 P1
D1 VSS1 VDDQ5 T1 2 D1 VSS1 VDDQ5 T1
F1 VSS2
VSS3
VDDQ6
VDDQ7
J2 CRB 10nF F1 VSS2
VSS3
VDDQ6
VDDQ7
J2
G1 K2 G1 K2
M1 VSS4 VDDQ8 C4 M1 VSS4 VDDQ8 C4
MEM_VREF levels N1 VSS5 VDDQ9 F4 N1 VSS5 VDDQ9 F4
+1.35VSDGPU R1 VSS6 VDDQ10 N4 R1 VSS6 VDDQ10 N4
70% of rail Terminat i on Enabl e U1 VSS7 VDDQ11 T4 U1 VSS7 VDDQ11 T4
A2 VSS8 VDDQ12 B5 A2 VSS8 VDDQ12 B5
50% of rail Terminat i on Disabl e VSS9 VDDQ13 VSS9 VDDQ13
1
V2 U5 V2 U5
RV634 C3 VSS10 VDDQ14 B10 C3 VSS10 VDDQ14 B10
@DIS@ D3 VSS11 VDDQ15 U10 D3 VSS11 VDDQ15 U10
549_0402_1% F3 VSS12 VDDQ16 C11 F3 VSS12 VDDQ16 C11
G3 VSS13 VDDQ17 F11 G3 VSS13 VDDQ17 F11
2
M3 N11 +1.35VSDGPU M3 N11

RV635 1 @DIS@ 2 931_0402_1% +FBC_VREFC1 N3 VSS15 VDDQ19 T11 N3 VSS15 VDDQ19 T11
+FBC_VREFC1_R
R3 VSS16 VDDQ20 J13 R3 VSS16 VDDQ20 J13

W=16mils VSS17 VDDQ21 VSS17 VDDQ21
1
T3 K13 T3 K13
1
1 A4 C14 RV2010 A4 C14

RV636 CV989 E4 VSS19 VDDQ23 E14 DIS@ E4 VSS19 VDDQ23 E14
DIS@ @DIS@ H4 VSS20 VDDQ24 H14 10K_0201_1% H4 VSS20 VDDQ24 H14
1.33K_0402_1% 820P_0402_25V7 L4 VSS21 VDDQ25 L14 L4 VSS21 VDDQ25 L14
2
2 P4 P14 P4 P14
VSS23 VDDQ27 FB_B_CMD33 VSS23 VDDQ27
2
V4 T14 V4 T14
D VSS24 VDDQ28 VSS24 VDDQ28
1
C5 C5
2 QV102 T5 VSS25 FB_B_CMD18 T5 VSS25
<27,35> MEM_VREF C10 VSS26 A1 C10 VSS26 A1
G @DIS@
BSS138W 1N SOT-323-3 T10 VSS27 VDD1 V1 T10 VSS27 VDD1 V1
S
3
1
A11 H2 A11 H2
+1.35VSDGPU E11 VSS29 VDD3 L2 RV2011 E11 VSS29 VDD3 L2
H11 VSS30 VDD4 E5 DIS@ H11 VSS30 VDD4 E5
L11 VSS31 VDD5 P5 10K_0201_1% L11 VSS31 VDD5 P5
1
P11 E10 P11 E10

2
RV2012 V11 P10 V11 P10
B DIS@ C12 VSS34 VDD8 H13 C12 VSS34 VDD8 H13 B
10K_0201_1% D12 VSS35 VDD9 L13 D12 VSS35 VDD9 L13
F12 VSS36 VDD10 A14 F12 VSS36 VDD10 A14
2
G12 V14 G12 V14

FB_B_CMD7 M12 VSS38 VDD12 +1.8V_GFX_AON M12 VSS38 VDD12 +1.8V_GFX_AON
FB_B_CMD2
N12 VSS39
VSS40
+1.35VSDGPU
Under DRAM N12 VSS39
VSS40
R12 A5 R12 A5
T12 VSS41 VPP1 V5 T12 VSS41 VPP1 V5
VSS42 VPP2 VSS42 VPP2
1
A13 A10 A13 A10

V13 VSS43 VPP3 V10 V13 VSS43 VPP3 V10
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
RV2013 1 1 1 1 1 1 1 1
B14 VSS44 VPP4 B14 VSS44 VPP4
CV991
CV992
CV993
CV994
CV995
CV996
CV997
CV998
DIS@
10K_0201_1% D14 VSS45 R4 D14 VSS45 R4
F14 VSS46 NC1 G5 FB_B_WCKB23 <31> F14 VSS46 NC1 G5 FB_B_WCK67 <31>
VSS47 NC2 VSS47 NC2
2
G14 M5 2 2 2 2 2 2 2 2 G14 M5
M14 VSS48 NC3 R5 M14 VSS48 NC3 R5
N14 VSS49 NC4 D10 FB_B_WCKB23# <31> N14 VSS49 NC4 D10 FB_B_WCK67# <31>
VSS50 NC5 FB_B_WCKB01# <31> VSS50 NC5 FB_B_WCK45# <31>
R14 D11 R14 D11
VSS51 NC6 FB_B_WCKB01 <31> DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ VSS51 NC6 FB_B_WCK45 <31>
U14 180-BALL U14 180-BALL
VSS52 SGRAM GDDR6 VSS52 SGRAM GDDR6
+1.35VSDGPU
+1.35VSDGPU
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0201_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV317
CV999
CV1000
CV1001
CV1002
CV1003
CV1004
CV1005
CV1006
CV1007
CV1008
CV1009
CV1010
CV1011
CV1012
CV1013
CV1014
CV1015
CV1016
CV1017
CV1018
CV1019
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV417
CV1020
CV1021
CV1022
CV1023
CV1024
CV1025
CV1026
CV1027
CV1028
CV1029
CV1030
CV1031
CV1032
CV1033
CV1034
CV1035
CV1036
CV1037
CV1038
CV1039
CV1040
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
+1.35VSDGPU
Under DRAM +1.35VSDGPU +1.35VSDGPU
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 1 1 1 1 1 1
A A
CV1041
CV1042
CV1043
CV1044
CV1045
CV1046
CV1047
CV1048
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CV318
CV319
CV320
CV321
CV322
CV323
CV324
CV325
CV418
CV419
CV420
CV421
CV422
CV423
CV424
CV425
2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@ DIS@

P036-N18P_GDDR5_B

5 4 3 2 1
5 4 3 2 1
+1.8V_3.3V_GFX_RUN Discharge
follow Fireload +5VALW
+1.8V_GFX_AON
DVT2.1_12:improve voltage drop RZ92, RZ1962, RV597, +3VALW +1.35VSDGPU

RV574, RV575, RV576 & RV582 change to short pad
1
DIS@
DIS@ RV11
1
+1.8VALW +1V8_3.3V_GFX_RUN_R +1.8V_GFX_RUN DIS@ DIS@ DIS@ 100_0201_5%
UZ24 RV12 RV8 RV657
100K_0201_5% 10_0201_5% 100K_0201_5%
2
1 8 RZ92 1 @ 2 0_0805_5%
2 VIN VOUT 7

VIN VOUT
2
@ 1 DIS@ DIS@
1V8_MAIN_RUN_EN
3
3 6 CZ98 1 2 2200P_0402_25V7K CZ99 QV3B
D EN CT 0.1U_0402_10V6K D
4 5 DIS@ DIS@ DIS@
+5VALW VBIAS GND DGPU_PWR_EN# 2 RV399
1 DIS@ 9 2 QZ6B QZ6A 1 DGPU_PWR_EN#_R 5
GND
6
CV817 LBSS139DW1T1G 2N SOT-363-6 ESD LBSS139DW1T1G 2N SOT-363-6 ESD
0.1U_0402_10V7K G5029ARC1D TDFN2X2 10K_0402_5%
4
6
DIS@ DIS@
0.1U_0402_10V7K
2 RZ106 5 2 LBSS139DW1T1G 2N SOT-363-6 ESDQV3A
<27,96> FBVDD_EN 1
0_0402_5%
CV499
1 2 1V8_AON_EN 2
1
@ DV16 2 DIS@
1V8_MAIN_EN
1
2
<27> 1V8_MAIN_EN
DIS@
1 1V8_MAIN_RUN_EN 2 1 1V8_AON_EN
RB751S-40_SOD523-2 DA57
3
<37,97> GPU_CORE_PG
BAT54CW-7-F_SOT323-3
+1.8VALW to +1.8V_3.3V_GFX_AON +3VALW +GPU_CORE +1VS_GFX

DIS@ +1.8V_GFX_AON_R +1.8V_GFX_AON +3VALW +1.8V_GFX_RUN
+1.8VALW UZ30
1
DIS@
1
1 8 RZ1962 1 @ 2 0_0805_5% RV103 DIS@ DIS@ DIS@ DIS@
2 VIN VOUT 7 100K_0201_5% RV1808 RV112 RV111 RV1811
VIN VOUT DIS@ 10_0201_5% 10_0201_5% 100_0201_5%
100K_0201_5%
1V8_AON_EN 1 DIS@ 2 3 6 CZ2155 1 2 100P_0402_50V8J
EN CT
2
RZ1964 0_0402_5%
2
4 5
+5VALW VBIAS GND 9
C GND C

QZ18 DIS@
G5029ARC1D TDFN2X2 DIS@ 2N7002KW_SOT323-3 QZ17A
3
QZ14A DIS@ D DIS@ LBSS139DW1T1G 2N SOT-363-6 ESD DIS@
1
+3V_PCH
6
LBSS139DW1T1G 2N SOT-363-6 ESD QZ14B QZ17B
2
5 G 1V8_MAIN_RUN_EN 2 5
2
<37,97> NVVDD_EN
5
UZ31 S
3
4
4
1
P
<14,37> DGPU_PWR_EN INB 1V8_AON_EN
1
4
2 O
<15,27,58,96> DGPU_PWROK INA
0.01UF_0402_25V7K
G
@ DIS@
1
CV920 RV1350
3
MC74VHC1G32DFT2G_SC70-5~D 1M_0201_5%
DIS@
2
+1V_GFX Enable +1.8V_GFX_AON

+1.8V_GFX_AON
NVVDD Enable
DA56 DA58
RB751S-40_SOD523-2 RB751S-40_SOD523-2
DIS@ RV99 1 DIS@ 2 10K_0201_5% GPU_CORE_PG 1 2 2 1 THERMATRIP_GPU# <27,28>
CV917
0.1U_0402_10V7K DIS@ DIS@
1 2
DIS@
RV1130
10K_0402_5%
1 2 1V8_MAIN_EN
B <37,97> NVVDD_EN B
DIS@
5
1U_0201_6.3V6M
UV28 1
1
1 RH5893 1 DIS@ 2 0_0201_5%
CV299
CV919
G VCC
4 B DGPU_PWR_EN <14,37>
<94> PEX_VDD_EN RV1807 1 DIS@ 2 0_0402_5% 0.01UF_0402_25V7K
Y 2 GPU_CORE_PG DIS@
A GPU_CORE_PG <37,97>
2
2
2
@ DIS@
1
CV918 RV1128 TC7SZ08FU_SSOP5

3
0.01UF_0402_25V7K 1M_0201_5%
@DIS@
2
RT899 1 @DIS@ 2 0_0201_5%

1
+FP_FUSE_GPU
+1.8V_GFX_AON DIS@
FB Power control
N18PG62@
RV2016 1 2 3.74K_0402_1% UZ34
FB_PW_CTL <96>
1 8
2 VIN VOUT 7
VIN VOUT
BOM option,N18PG62 Use 1.2V FB power +5VALW
DIS@
3 6 CZ2158 1 2 100P_0201_25V8J 1 DIS@
EN CT CV9375
4 5 1U_0201_6.3V6M
+3VS VBIAS GND
3
N18PG62@ N18PG62@ 9
1U_0201_6.3V6M
1U_0201_6.3V6M
1 1 GND 2
RV2017 1 2 10K_0201_1% 5
CV9373
CV9374
QV104A
D
DIS@
DIS@
G
G5029ARC1D TDFN2X2
S
LBSS139DW1T1G_SOT363-6
4
2 2
@N18PG62@ DVT2.1_14:Only N18PG62 sku FBVDD control by MEM_VDD_CTL,so this schematic shuold put in EE side.
change location name as below :
1
A N18PG62@ CV9380 A
change from PR721 to RV2016
RV2018 1000P_0402_50V7K change from PQ700 to QV104
6
0_0402_5% change from PC728 to CV9380

<27> GPIO26_FP_FUSE
2
1 2 2 N18PG62@ change from PR716 to RV2017

D
<27> MEM_VDD_CTL
G
change from PR717 to RV2018
S QV104B change from PC706 to CV9381
Add net name "FB_PW_CTL"
1
LBSS139DW1T1G_SOT363-6 Change Bom structure from DIS@ to N18PG62@

1
N18PG62@
CV9381
0.1U_0402_25V7K Issued Date 2019/11/30 Deciphered Date 2027/06/21 Title
2
P037-DC/DC-VGA
5 4 3 2 1
5 4 3 2 1
LCD backlight PWR CTRL eDP & TS Conn. I2C0_SDA_TS 2 1 RC183

+3VS_TS
499_0402_1% @
I2C0_SCK_TS 499_0402_1% 2 @ 1 RC184
DV1 TS_DETECT# 100K_0201_5% 1 2 RC5835
2 +3VALW I2C2_IRQ_TS 100K_0201_5% 1 @ 2 RH5823
<58> PANEL_BKEN_EC TS_I2C_RST# 100K_0201_5% 1 2 RH5902
1 DISPOFF#
2
TOUCH_SCREEN_PD# <14> TS_I2C_RST#
1
<13> PANEL_BKEN_PCH 3 RV299
RV107 100K_0201_5%
1
BAT54CW-7-F_SOT323-3~D 10K_0201_5%
1
DVT2.1_06:Add SD000020G00 (80.6k)to prevent g516a1y51u leakage RR45 D74
PESD5V0H1BSF_SOD962-2-2
1
@ 0_0201_5%
2
B+ +INV_PWR_SRC_R +INV_PWR_SRC
B+ DV2 TOUCH_SCREEN_PD#_R
EMC@
2
UZ6 +INV_PWR_SRC 2
<6,13> BIA_PWM_PCH
6
1 4 5 RZ1145 1BreakDown@
2 0.01_0603_1%
IN OUT 1 INV_PWM D2 D1
1
CV172 3 6
IN OUT
1
10U_0603_16V6M RV2014 B+ 3 5 2
2 <58> BIA_PWM_EC
2
2 7
0.1U_0402_25V6
80.6K_0201_1% RV109 G2 G1
D <58> BL_PG FLAG GND D
10U_0603_25V6M
Q7B
Q7A
1 BAT54CW-7-F_SOT323-3~D 4.7K_0201_5%
EN_INVPWR 1 OVP_INV_PWR_
1
8
CV169
S2 S1
<58> EN_INVPWR EN(#EN) OVTH
CV168
1
G516A1Y51U_TSOT23-8 RV121
2
2
1M_0201_5%
Active High OVP_INV_PWR_
2
DISPOFF#
Ron=50ohm
VIN_OVTH=1.24(R1+R2/R2)
2
=1.24(1000K/68K)=19.48V
RV120
68K_0201_1% DVT2_03:Add GND to fix schematic issue
CV158 1 2 0.1U_0201_10V6K EDP_TXP0_C
<6> EDP_TXP0
1
EDP_TXN0_C DVT2.1_02:Del RV110,RV113 and net "LCD_TST_R","EDP_HPD_R" for layout placement
DVT2.1_05:change from SD028220380 to SD043220380 for layout placement <6> EDP_TXN0 CV159 1 2 0.1U_0201_10V6K
JEDP1
INV_PWM 1 2
EN_INVPWR 1 2 LCD_TST <58>
RV135 2 1 220K_0201_5% DISPOFF# 3 4
5 3 4 6
<58> SOLC 5 6 +EDPVDD
7 8
<13,58> EDP_HPD 7 8 EDP_AUXN_C
9 10
+EDPVDD 11 9 10 12 EDP_AUXP_C
+INV_PWR_SRC 13 11 12 14
CV160 1 2 0.1U_0201_10V6K EDP_TXP1_C 15 13 14 16 EDP_TXP0_C
<6> EDP_TXP1 15 16 EDP_TXN0_C
17 18
19 17 18 20
ALS+ IR CCD+ DMIC Chicony: IR LED MAX:1000mA(12.6V) Estimate-->1400mA(9V) <6> EDP_TXN1 CV161 1 2 0.1U_0201_10V6K EDP_TXN1_C 21
23
19
21
23
20
22
24
22
24
EDP_TXP1_C
EDP_TXN1_C
25 26
Power Consumption for Camera (RGB / IR)=200mA(3.3v) 27
29
25
27
26
28
28
30
EDP_TXP2_C
EDP_TXN2_C
31 29 30 32
TS_DETECT# 33 31 32 34 EDP_TXP3_C
<13> TS_DETECT# I2C0_SDA_TS_R 33 34 EDP_TXN3_C
LITEON: IR LED 800mA(B+ Peak power) CV162 1 2 0.1U_0201_10V6K EDP_TXP2_C
<17>
<17>
I2C0_SDA_TS
I2C0_SCK_TS
0_0201_5%
0_0201_5%
0_0201_5%
1
1
1
2 RR42
2 RR41
2 RR44
I2C0_SCK_TS_R
I2C2_IRQ_TS_R
35
37
39
35
37
36
38
36
38
40 LCD_DBC_R RV1843 1 2 0_0201_5%
Power Consumption for Camera (RGB / IR)=254mA(3.3v) <6> EDP_TXP2 <15>
<15>
I2C2_IRQ_TS
TS_I2C_RST#
41 39
41
40
42
42 TOUCH_SCREEN_PD#_R LCD_DBC <16>
RGB Cam:143.5mA IR Cam:110.6mA <6> EDP_TXN2 CV163 1 2 0.1U_0201_10V6K EDP_TXN2_C

+INV_PWR_SRC
+3VS_TS
43
45 Power
Power
Power
Power
44
46
pin define:20pin 47
GND GND
48
49 50
51 GND GND 52
53 GND GND 54
55 GND GND 56
+3VS_Hinge 57 GND GND 58
C 59 GND GND 60 C
CV164 1 2 0.1U_0201_10V6K EDP_TXP3_C 61 GND GND 62
Near JCCD1 PIN45 <6> EDP_TXP3 GND GND
1 63 64
CV165 1 2 0.1U_0201_10V6K EDP_TXN3_C 65 PTH PTH 66
<6> EDP_TXN3 PTH PTH
CV184 67 68
0.1U_0201_10V6K PTH PTH
2
I-PEX_20698-042E-01
DVT2_01:change CV184 from SE00001G000 to SE00000SV00 fix schematic issue CONN@
JCCD1
P_SENSOR_PIN3 1 2
3 1 2 4
+3VS_Hinge 3 4
5 6 ALS & P Sensor
5 6 ISH_I2C1_SCL_ALS EDP_AUXN_C
<17> P_SENSOR_PWR_SAVE#
<17> P_DET#
0_0201_5%
0_0201_5%
2
2
1 RR39
1 RR35
7
9 7
9
8
10
8
10 ISH_I2C1_SDA_ALS
RR48 1
RR47 1
2 0_0201_5%
2 0_0201_5% ISH_I2C1_SCL
ISH_I2C1_SDA
<17,59>
<17,59>
<6> EDP_AUXN CV166 1 2 0.1U_0201_10V6K
I-PEX_20698-042E-01 Connector Panel 500nits
<17> ISH_P_SENSOR_INT#
0_0201_5%
S_BIO
2 1 RR50
11
13 11
13
12
14
12
14
<6> EDP_AUXP CV167 1 2 0.1U_0201_10V6K EDP_AUXP_C Signal Pin -->300mA +INV_PWR_SRC 7.6W(1A)
<13> S_BIO
15
17 15
17
16
18
16
18
DMIC_CLK_CODEC_C
Power Pin -->2A +EDPVDD 1.8W(750mA)
19 20
21 19 20 22 DMIC_DAT_CODEC_C DMIC
23 21 22 24
+DMIC_DVDD_PIN25 25 23 24 26
+3VS_Hinge 25 26
27 28
29 27 28 30
+3VS_Hinge 29 30 ISH_I2C1_SDA_P
+3V_ALS_PIN29 31 32 RR73 1 2 0_0201_5%
33 31 32 34 ISH_I2C1_SCL_P RR74 1 2 0_0201_5%
0_0201_5% 2 1 RR49 ISH_ALS_INT#_RR 35 33 34 36
<17> ISH_ALS_INT# 37 35 36 38 USB20_N11_R LV22
39 37 38 40 USB20_P11_R USB20_P11 1 2 USB20_P11_R
CAM_CBL_DET# 39 40 <16> USB20_P11 1 2
41 42
<13> CAM_CBL_DET# 41 42 +EDPVDD +3VS_TS +3VS_TS
43 44 USB20_N11 4 3 USB20_N11_R
+3V_CAM B+_CAM
45 Power Power 46
<16> USB20_N11 4 3
+3VS_Hinge Power Power
DLM0NSN900HY2D_4P
1
47 48
10U_0603_6.3V6M
0.1U_0201_10V6K
AZ5B25-01F_DFN0603P2Y2
GND GND
1
49 50 EMC@ 1 D18
CAM_CBL_DET# 51 GND GND 52
C3003
GND GND 1 1
53 54 D327 D328
CV157
55 GND GND 56 CV156
EMC@
GND GND 2
1
EMI@ 57 58 8.2P_0402_50V8D @
EMC@
EMC@
D123 59 GND GND 60 2 2
61 GND GND 62
GND GND
2
63 64
65 PTH PTH 66
67 PTH PTH 68
B
AZ5B25-01F_DFN0603P2Y2 PTH PTH B
2
I-PEX_20698-042E-01
CONN@
Near to connecter
IR Digital Camera
+3VS_Hinge
DMIC_CLK_CODEC_C RE116 1 20_0201_5% DMIC_CLK_CODEC
DMIC_DAT_CODEC_C DMIC_CLK_CODEC <56>
RE117 1 20_0201_5% DMIC_DAT_CODEC DMIC_DAT_CODEC <56>
100K_0201_5% 1 @ 2 RE200 S_BIO
100K_0201_5% 1 @ 2 RE201 RE310 1 @ 2 0_0201_5% PCH_DMIC_CLK_R <15>
RE309 1 @ 2 0_0201_5% PCH_DMIC_DAT_R <15>
1 1 DVT2_05 : Change RE116,RE117 to pop ; RE310,RE309 to "@"

for DMIC model from Codec to PCH contact control function
27P_0201_25V8
@ CE3321
27P_0201_25V8
@ CE3322
DVT2.1_06: Add SD000020G00 (80.6k)to prevent g516a1y51u leakage

2 2 B+_CAM_R B+_CAM
DMIC_DAT_CODEC B+ B+_CAM
DMIC_CLK_CODEC UZ7
B+ 4 5 0.01_0603_1% 2BreakDown@1 RZ1967
IN OUT
1
1 3 6
IN OUT
2
0.1U_0402_25V6
RV2015
C3314 2 7 @ 80.6K_0201_1% B+
10U_0603_25V6M
1
TVNST52302AB0_SOT523-3 10U_0603_16V6M <58> B+_CAM_PG FLAG GND
C3316
DE9 2 1 8 OVP_B+_CAM
C3315
<58> IRCAM_EN EN(#EN) OVTH
1
EMC@
2
2
G516A1Y51U_TSOT23-8
1
RR120
Active High 1M_0201_5%
Ron=50ohm OVP_B+_CAM
2
VIN_OVTH=1.24(R1+R2/R2)
1
=1.24(160K/10K)=19.84V
RR119
68K_0201_1%
2
A A

2019/11/30
Compal Secret Data
2027/06/21 Title
Issued Date Deciphered Date
P038-eDP/CCD/TS
Size Document Number Re v
0.4(X03)
5 4 3 2 1
5 4 3 2 1
+INV_PWR_SRC & +EDPVDD monitor

D +EDPVDD D
2
+3VALW RV18
100K_0201_5%
1
2
2 1
PANEL_MONITOR <58>
RV25 RV15 0_0201_5%
1M_0201_5%
3
1
L2N7002DW1T1G_SC88-6
5 QV10B
+INV_PWR_SRC
4
6
L2N7002DW1T1G_SC88-6
2 QV10A
1
0.1U_0201_25V6K
CV155
1
2
C C
B B
A A

P039-DP to HDMI Converter PS175
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-J191P 0.4(X03)
5 4 3 2 1
Vinafix.com
5 4 3 2 1
I2C ADDR I2C Slave Address
NC 0x72 (default)
100P_0201_50V8J
Darwin 2.0 Pull up 3.3V 0x34 +3VS_WLAN
BLM15PX330SN1D_2P
CW223
DAR@
1
2
JWLA2(main antenna)
LW10
DAR@ JWLA2
CTRL2 1 2 CTRL2_R 1
1 2 2 1
DAR@ 3 2
D 1 CTRL3_R 3 D
4
100P_0201_50V8J
LW11
BLM15PX330SN1D_2P 5 4 6
<40> CSIO_0 5 GND_1 7
CW224 2 GND_2
DAR@ HEFEN_AFC48-S05FKA-HF
CONN@
+3VS_WLAN_MCU +3VS_WLAN_MCU
0.1U_0201_10V6K
1U_0201_6.3V6M
2
RW226 1 1
@RF@1M_0201_5% CW125 CW126
DAR@ DAR@
SYS_CFG +3VS_WLAN +3VS_WLAN_MCU
1
2 2 2 UW1 DAR@
RW227
RW1233 1 DAR@ 2 0_0402_5% 20
VDDD NC V5V
5
DAR@1M_0201_5% 21 6
VDDIO CC1
CW123 1DAR@2 0.1U_0201_10V6K 22 4
VCCD CC2
1
SWD_DAT_MCU 24 9 I2C_SDA TP_P17 RW136 1 DAR@ 2 0_0201_5% CCG5C_SMBDAT

P1.1/GPIO/SWD_DATA P0.0/SCB0_I2C_SDA CCG5C_SMBDAT <48,58>
SWD_CLK_MCU 1 10 I2C_SCL TP_P01 RW31 1 DAR@ 2 0_0201_5% CCG5C_SMBCLK
TP_P17 +3VS_WLAN_MCU P1.2/GPIO/SWD_CLK P0.1/SCB0_I2C_SCL CCG5C_SMBCLK <48,58>
RW1261 @ 2 0_0402_5% PIN3
ADDR0.NC 16 UART_T X TP_P32
TP_P32 P3.2/SCB3_I2C_SDA WIFI_UART_RX_R <52>
RW1271 @ 2 0_0402_5% ADDR1:1Mohm
RW135 1 @ 2 1K_0201_5% 2 17 UART_RX TP_P33
TP_P33 +3VS_WLAN_MCU P1.3/GPIO P3.3/SCB3_I2C_SCL WIFI_UART_TX_R <52> +3VS_WLAN_MCU
RW1281 @ 2 0_0402_5%
SYS_CFG 3
RW1291 @ 2 0_0402_5% TP_P01 P1.5/GPIO 11 TP_P23 RW32 1 DAR@ 2 0_0402_5% CTRL1_R RE3551 DAR@ 2 100K_0201_5%
P2.3/HPD CSIO_2 <40>
2
RW30 1 @ 2 0_0402_5% DEBUG_INT 8

<58> DAR_INT# P1.7/GPIO TP_P25 CTRL3_R
RW351 12 RW33 1 @ 2 0_0402_5% RE3561 DAR@ 2 100K_0201_5%
4.7K_0201_5% RW137 1 DAR@ 2 0_0402_5% TP_P26 14 P2.5/VBUS_DISCHARGE
DAR@ <40> CSIO_3 P2.6/GPIO
C C
13 CTRL0 CTRL0
P3.0/GPIO
1
XRES_MCU_R XRES_MCU 7
XRES 15 CTRL1 CTRL1 RW330 1 @DAR@ 2 0_0402_5% CTRL1_R
P3.1/GPIO CTRL1_R <58>
2
+3VS_WLAN_MCU CW228 19 18 CTRL2 CTRL2
0.1U_0201_10V6K GND P3.4/GPIO
RW130 1 @ 2 0_0402_5% @DAR@ 25 23 CTRL3 CTRL3 RW331 1 @DAR@ 2 0_0402_5% CTRL3_R
1 VSS P3.6/GPIO CTRL3_R <58>
RW132 1 @ 2 0_0402_5% XRES_MCU_R CYPD4126-24LQXIT_QFN24_4X4 DVT2_21 :

RW133 1 @ 2 0_0402_5% SWD_CLK_MCU RW330,RW331 change to unpop for RF request
RW134 1 @ 2 0_0402_5% SWD_DAT_MCU
0.1" spacing 0.035" through holes

or 0.1" spacing 0.050 SMT pads
100P_0201_50V8J
DAR@
+3VS_WLAN
CW225 1 JWLA2(AUX antenna)
BLM15PX330SN1D_2P
LW20
DAR@ 2 JWLA1
CTRL0 1 2 CTRL0_R 1
1 2 2 1
1 2
DAR@ 3
CTRL1_R 4 3
100P_0201_50V8J
LW21
BLM15PX330SN1D_2P 5 4 6
<40> CSIO_1 5 GND_1
DAR@ 2 7
CW226 GND_2
HEFEN_AFC48-S05FKA-HF
P-sensor CONN@
B B
+3VS_WLAN_MCU
+3VS_WLAN_MCU
2.2K_0201_5% 2 DAR@ 1 RE228 PSEN_I2C_SDA
2.2K_0201_5% 2 DAR@ 1 RE229 PSEN_I2C_SCK +3VS_WLAN_MCU
2
1
QH15A DAR@
G1
PMDXB600UNE_DFN1010B-6 @ RT3999
2.2K_0201_5%
CCG5C_SMBDAT RE256 1 DAR@ 2 0_0201_5% 6 1 PSEN_I2C_SDA
D1
S1
U18 DAR@
PSEN_I2C_SCK 1 10 0_0402_5% 2 DAR@ 1 RW360
CCG5C_SMBCLK RE257 1 DAR@ PSEN_I2C_SCK SCL NIRQ PSEN_INT# <58>
2 0_0201_5% 3 4
D2
S2
PSEN_I2C_SDA 2 9
PMDXB600UNE_DFN1010B-6 SDA CSIO4
QH15B DAR@ RE232 1 DAR@ 2 0_0201_5% 3 8 0_0201_5% 2 DAR@ 1 RE233
G2
<40> CSIO_2 CSIO2 CSIO3 CSIO_3 <40>

5
1 DAR@ 2 +3VS_PSEN 4 7 0_0201_5% 2 DAR@ 1 RE230

+3VS_WLAN_MCU VDD CSIO0 CSIO_0 <40>
+3VS_WLAN_MCU RW361 0_0402_5%
5 6 0_0201_5% 2 DAR@ 1 RE231
+3VS_PSEN GND CSIO1 CSIO_1 <40>
SX9331IULTRT_DFN10_1P8X2P1
1U_0201_6.3V6M
1
CW250
DAR@
2
A A

P040-HDMI Connector
C LA-J191P 0.4(X03)

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P058-EC_MEC 5105
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS C
5 4 3 2 1
5 4 3 2 1
+3.3V_TBT_FLASH_R +3.3V_TBT_FLASH_R
+3.3V_TBT_LC
TR Port R
10K_0201_5%
10K_0201_5%
10K_0201_5%
10K_0201_5%
1
1
RT6
RT7
RT8
RT9
TBT_JTAG_TDI
2
+3.3V_TBT_FLASH_R
TBT_JTAG_TMS
3.3K_0201_5%
3.3K_0201_5%
3.3K_0201_5%
3.3K_0201_5%
+3V_LDO
0.1U_0201_10V6K
1
1
TBT_JTAG_TCK
1
CT47
TBT_JTAG_TDO
RT15
RT18
RT16
RT17
2
RT2 1 2 0_0402_5%
2
2
UT16
8 1 TBT_ROM_CS#
TBT_ROM_HOLD# 7 VCC CS# 2 TBT_ROM_DO
TBT_ROM_CLK 6 HOLD#(IO3) DO(IO1) 3 TBT_ROM_WP#
D TBT_ROM_DI 5 CLK WP#(IO2) 4 D
9 DI(IO0) GND
thermal pad
W25Q80DVZPIG_WSON8
UT1A
PCIE_PTX_TRX_P1 0.22U_0201_6.3V6K 2 1 CT176 PCIE_PTX_C_TRX_P1 Y23 V23 PCIE_PRX_C_TTX_P1 0.22U_0201_6.3V6K 2 1 CT179 PCIE_PRX_TTX_P1
<16> PCIE_PTX_TRX_P1
CPU PCIE TX
PCIE_PTX_TRX_N1 0.22U_0201_6.3V6K 2 1 CT177 PCIE_PTX_C_TRX_N1 Y22 PCIE_RX0_P PCIE_TX0_P V22 PCIE_PRX_C_TTX_N1 0.22U_0201_6.3V6K 2 1 CT181 PCIE_PRX_TTX_N1 PCIE_PRX_TTX_P1 <16>
CPU PCIE RX
<16> PCIE_PTX_TRX_N1 PCIE_RX0_N PCIE_TX0_N PCIE_PRX_TTX_N1 <16>
PCIE_PTX_TRX_P2 0.22U_0201_6.3V6K 2 1 CT175 PCIE_PTX_C_TRX_P2 T23 P23 PCIE_PRX_C_TTX_P2 0.22U_0201_6.3V6K 2 1 CT178 PCIE_PRX_TTX_P2
<16> PCIE_PTX_TRX_P2 PCIE_PTX_TRX_N2 2 1 PCIE_PTX_C_TRX_N2 T22 PCIE_RX1_P PCIE_TX1_P P22 PCIE_PRX_C_TTX_N2 2 1 CT180 PCIE_PRX_TTX_N2 PCIE_PRX_TTX_P2 <16>
0.22U_0201_6.3V6K CT174 0.22U_0201_6.3V6K
PCIe GEN3
PCIE_PTX_TRX_P3 0.22U_0201_6.3V6K 2 1 CT6 PCIE_PTX_C_TRX_P3 M23 K23 PCIE_PRX_C_TTX_P3 0.22U_0201_6.3V6K 2 1 CT5 PCIE_PRX_TTX_P3
<16> PCIE_PTX_TRX_P3 PCIE_PTX_TRX_N3 2 1 CT8 PCIE_PTX_C_TRX_N3 M22 PCIE_RX2_P PCIE_TX2_P K22 PCIE_PRX_C_TTX_N3 2 1 CT7 PCIE_PRX_TTX_N3 PCIE_PRX_TTX_P3 <16>
0.22U_0201_6.3V6K 0.22U_0201_6.3V6K
PCIE_PTX_TRX_P4 0.22U_0201_6.3V6K 2 1 CT2 PCIE_PTX_C_TRX_P4 H23 F23 PCIE_PRX_C_TTX_P4 0.22U_0201_6.3V6K 2 1 CT1 PCIE_PRX_TTX_P4
<16> PCIE_PTX_TRX_P4 PCIE_PTX_TRX_N4 2 1 CT4 PCIE_PTX_C_TRX_N4 H22 PCIE_RX3_P PCIE_TX3_P F22 PCIE_PRX_C_TTX_N4 2 1 CT3 PCIE_PRX_TTX_N4 PCIE_PRX_TTX_P4 <16>
0.22U_0201_6.3V6K 0.22U_0201_6.3V6K
T4 TBT_PERST#
V19 PERST# PCIeReset:need buffer between PCH and AR
<14> CLK_PCIE_P5 T19 REFCLK_100_IN_P N16 TBT_PCIE_RBIAS 1 2 3.01K_0201_1%
RT1
<14> CLK_PCIE_N5 CLKREQ_PCIE#5 Y6 REFCLK_100_IN_N PCIE_RBIAS Y2
<14> CLKREQ_PCIE#5 PCIE_CLKREQ# PEWAKE#
0.22U_0201_6.3V6K 2 1 CT18 CPU_DP1_N0_C AB7 AB21 TBT_PCIE_WAKE#
<6> CPU_DP1_N0 CPU_DP1_P0_C AC7 DPSNK1_ML0_N DPSRC_ML0_P AC21
0.22U_0201_6.3V6K 2 1 CT17
<6> CPU_DP1_P0 DPSNK1_ML0_P DPSRC_ML0_N
0.22U_0201_6.3V6K 2 1 CT19 CPU_DP1_P1_C AB9 AC19
<6> CPU_DP1_P1 2 1 CT20 CPU_DP1_N1_C AC9 DPSNK1_ML1_P DPSRC_ML1_P AB19
0.22U_0201_6.3V6K
<6> CPU_DP1_N1 DPSNK1_ML1_N DPSRC_ML1_N +3.3V_TBT_SX
SOURCE PORT 0
CPU_DP1_P2_C
SINK PORT 1
0.22U_0201_6.3V6K 2 1 CT21 AC11 AB17
<6> CPU_DP1_P2 2 1 CT22 CPU_DP1_N2_C AB11 DPSNK1_ML2_P DPSRC_ML2_P AC17 +3VALW
0.22U_0201_6.3V6K
<6> CPU_DP1_N2 DPSNK1_ML2_N DPSRC_ML2_N
0.22U_0201_6.3V6K 2 1 CT23 CPU_DP1_P3_C AB13 AC15
<6> CPU_DP1_P3 2 1 CT24 CPU_DP1_N3_C AC13 DPSNK1_ML3_P DPSRC_ML3_P AB15 CLKREQ_PCIE#5
0.22U_0201_6.3V6K RT320 1 @ 2 10K_0201_5%
<6> CPU_DP1_N3 DPSNK1_ML3_N DPSRC_ML3_N
0.22U_0201_6.3V6K 2 1 CT25 CPU_DP1_AUXP_C N1 N4
<6> CPU_DP1_AUXP 2 1 CT26 CPU_DP1_AUXN_C N2 DPSNK1_AUX_P DPSRC_AUX_P N5 TBT_RESET_N_EC
0.22U_0201_6.3V6K RT34 1 @ 2 10K_0201_5%
<6> CPU_DP1_AUXN DPSNK1_AUX_N DPSRC_AUX_N RTD3_USB_PWR_EN RT311 1 @ 2 10K_0201_5%
PCH_DP1_HPD AA2 TBT_FORCE_PWR_R RT33 1 @ 2 10K_0201_5%
<13> PCH_DP1_HPD DPSNK1_HPD DPSRC_HPD SIO_SLP_S3#
CPU DPSRC_HPD
R5 RT45 1 @ 2 10K_0201_5%
0.22U_0201_6.3V6K 2 1 CT583 CPU_DP2_P0_C A5 TDOCK_BATLOW# RT37 1 2 10K_0201_5%

<6> CPU_DP2_P0 2 1 CT584 CPU_DP2_N0_C B5 DPSNK2_ML0_P RTD3_CIO_PWR_EN_R 1 2
0.22U_0201_6.3V6K RT47 10K_0201_5%
<6> CPU_DP2_N0 DPSNK2_ML0_N DG_GPIO8 1 2
RT50 2.2K_0201_5%
0.22U_0201_6.3V6K 2 1 CT585 CPU_DP2_P1_C B3 W1 GPIO_0 TBT_CIO_PLUG_EVENT# RT381 1 2 10K_0201_5%
<6> CPU_DP2_P1 CPU_DP2_N1_C DPSNK2_ML1_P GPIO_0 GPIO_1 GPIO_0
LC GPIO
0.22U_0201_6.3V6K 2 1 CT586 A3 W2 RT382 1 @ 2 10K_0201_5%
<6> CPU_DP2_N1 DPSNK2_ML1_N GPIO_1 SML0_ALERT#_TR_R
SINK PORT 2
C Y1 RT5846 1 @ 2 0_0201_5% C
0.22U_0201_6.3V6K 2 1 CT587 CPU_DP2_P2_C C2 TMU_CLKOUT AA1 TBT_CIO_PLUG_EVENT# SML0_ALERT#_TR <15>
<6> CPU_DP2_P2 2 1 CT588 CPU_DP2_N2_C C1 DPSNK2_ML2_P CIO_PLUG_EVENT# W6 DG_GPIO8 TBT_CIO_PLUG_EVENT# <13> DPSRC_HPD
0.22U_0201_6.3V6K RT43 1 2 100K_0201_5%
<6> CPU_DP2_N2 DPSNK2_ML2_N TMU_CLKIN
0.22U_0201_6.3V6K 2 1 CT589 CPU_DP2_P3_C E2
<6> CPU_DP2_P3 2 1 CT590 CPU_DP2_N3_C E1 DPSNK2_ML3_P V1
0.22U_0201_6.3V6K
<6> CPU_DP2_N3 DPSNK2_ML3_N I2C_SDA V2 TBT_I2C_SDA <44>
CPU_DP2_AUXP_C I2C_SCL RTD3_USB_PWR_EN TBT_I2C_SCL <44>
POC GPIO
0.22U_0201_6.3V6K 2 1 CT591 P1 V5
<6> CPU_DP2_AUXP 2 1 CT592 CPU_DP2_AUXN_C P2 DPSNK2_AUX_P USB_FORCE_PWR V4 TBT_FORCE_PWR_R
0.22U_0201_6.3V6K RT558 1 2 0_0201_5%
<6> CPU_DP2_AUXN DPSNK2_AUX_N FORCE_PWR U2 TDOCK_BATLOW# TBT_FORCE_PWR <17>
PCH_DP2_HPD Y4 BATLOW# U1 SIO_SLP_S3# RTD3_USB_PWR_EN RT44 1 2 100K_0201_5%
<13> PCH_DP2_HPD DPSNK2_HPD SLP_S3# T5 RTD3_CIO_PWR_EN_R SIO_SLP_S3# <15,78,79> TBT_FORCE_PWR_R
RT22 1 2 0_0201_5% RT40 1 2 100K_0201_5%
RTD3_PWR_EN RTD3_CIO_PWR_EN <14> RTD3_PWN_EN/GPPC_H16 GPIO_0 RT39 1 2 100K_0201_5%
AC3 E5 TBT_RESET_N_EC RT29 1 @ 2 0_0201_5% GPIO_1 RT35 1 2 100K_0201_5%
AB3 U0_SSRXp1 RESET# CCG5_AR_RST# <44> SML0_ALERT#_TR_R 1 2
RT32 100K_0201_5%
U0_SSRXn1 XTAL_25_IN TBT_RESET_N_EC <58> XTAL_25_IN_R DG_GPIO8
Misc
D22 1 2 RT49 1 @ 2 10K_0201_5%
USB
AB5 XTAL_25_IN D23 XTAL_25_OUT 1 2 XTAL_25_OUT_R RT30 33_0201_1%
AC5 U0_SSTXn1 XTAL_25_OUT RT31 33_0201_1%
U0_SSTXp1 YT1
TBT_JTAG_TDI W20 3 1
TBT_JTAG_TMS Y20 TDI Y18 TBT_ROM_DI OUT IN
TBT_JTAG_TCK W19 TMS EE_DI W16 TBT_ROM_DO 4 2 TBT_A_HPD_SCL RT48 1 2 100K_0201_5%
TBT_JTAG_TDO Y19 TCK EE_DO W18 TBT_ROM_CS# GND GND TBT_B_HPD_SDA RT42 1 2 100K_0201_5%
TDO MISC EE_CS# TBT_ROM_CLK 1 1 PCH_DP1_HPD
Y16 25MHZ_20PF_8Y25070020 RT90 1 2 100K_0201_5%
TBT_RBIAS J6 EE_CLK W4 TBT_ROM_WP# CT61 CT62 PCH_DP2_HPD RT361 1 2 100K_0201_5%
1 2 TBT_RSENSE J5 RBIAS EE_WP# 20P_0201_25V8J 20P_0201_25V8J
4.75K_0201_0.5% RT10 RSENSE 2 2
PortA
1 2 0_0201_5% TBT_A_TRX_DTX_P1_R B21 A13 TBT_B_TRX_DTX_P1_R RT24 1 2 0_0201_5%
TypeC
RX0_P(B21)/RX1+(B11) RT5832
<45> TBT_A_TRX_DTX_P1 1 2 0_0201_5% TBT_A_TRX_DTX_N1_R A21 ASSRXp1 BSSRXp1 B13 TBT_B_TRX_DTX_N1_R TBT_B_TRX_DTX_P1 <45>
RX0_N(A21)/RX1-(B10) RT5833 RT23 1 2 0_0201_5% RX0_P(A13)/RX1+(B11)
<45> TBT_A_TRX_DTX_N1 ASSRXn1 BSSRXn1 TBT_B_TRX_DTX_N1 <45> RX0_N(B13)/RX1-(B10)
TX0_P(A19)/TX1+( A2 ) CT37 2 1 0.22U_0201_6.3V6M TBT_A_TTX_DRX_P1_C A19 A11 TBT_B_TTX_DRX_P1_C CT579 1 2 0.22U_0201_6.3V6M DG_PA_USB2_MXCTL RT36 1 2 100K_0201_5%
TX0_N(B19)/TX1-(A3) <45> TBT_A_TTX_DRX_P1 CT38 2 1 0.22U_0201_6.3V6M TBT_A_TTX_DRX_N1_C B19 ASSTXp1 BSSTXp1 B11 TBT_B_TTX_DRX_N1_C CT580 1 2 0.22U_0201_6.3V6M TBT_B_TTX_DRX_P1 <45> TX0_P(A11)/TX1+( A2 )
DG_PB_USB2_MXCTL RT41 1 2 100K_0201_5%
<45> TBT_A_TTX_DRX_N1 ASSTXn1 BSSTXn1 TBT_B_TTX_DRX_N1 <45> TX0_N(B11)/TX1-(A3)
2 0_0201_5% TBT_A_TRX_DTX_P2_R TBT_B_TRX_DTX_P2_R
TypeC
RX1_P(A15))/RX2+(A11 ) RT5834 1 A15 B7 RT27 1 2 0_0201_5%
PortB
<45> TBT_A_TRX_DTX_P2 1 2 0_0201_5% TBT_A_TRX_DTX_N2_R B15 ASSRXp2 BSSRXp2 A7 TBT_B_TRX_DTX_N2_R TBT_B_TRX_DTX_P2 <45>
RX1_N(B15)/RX2-(A10) RT5835 RT26 1 2 0_0201_5% RX1_P(B7))/RX2+(A11)
<45> TBT_A_TRX_DTX_N2 ASSRXn2 BSSRXn2 TBT_B_TRX_DTX_N2 <45>
TBT PORTS
RX1_N(A7)/RX2-(A10)
TX1_P(A17)/TX2+(B2 ) CT39 2 1 0.22U_0201_6.3V6M TBT_A_TTX_DRX_P2_C A17 A9 TBT_B_TTX_DRX_P2_C CT581 1 2 0.22U_0201_6.3V6M
<45> TBT_A_TTX_DRX_P2 TBT_A_TTX_DRX_N2_C ASSTXp2 BSSTXp2 TBT_B_TTX_DRX_N2_C TBT_B_TTX_DRX_P2 <45>
Port A
PORT B
TX1_N(B17)/TX2-(B3) CT40 2 1 0.22U_0201_6.3V6M B17 B9 CT582 1 2 0.22U_0201_6.3V6M TX1_P(A9)/TX2+(B2 )

<45> TBT_A_TTX_DRX_N2 ASSTXn2 BSSTXn2 TBT_B_TTX_DRX_N2 <45> TX1_N(B9)/TX2-(B3)
H4 L4 K11+D11/L4
<44> TBT_A_SBU1 J4 ASBU1 BSBU1 L5 TBT_B_SBU1 <44>
L11+E11/L5
<44> TBT_A_SBU2 ASBU2 BSBU2 TBT_B_SBU2 <44>
E20 E19
CCG5
CCG5
D20 PA_USB2_D_P PB_USB2_D_P D19

PA_USB2_D_N PB_USB2_D_N
TBT_A_HPD_SCL T2 T1 TBT_B_HPD_SDA
M4 PA_HPD PB_HPD M5
<44> TBTA_I2C_INT# DG_PA_USB2_MXCTL PA_I2C_INT PB_I2C_INT DG_PB_USB2_MXCTL TBTB_I2C_INT# <44>
R2 R1
RT12 1 2 200_0201_1% TBTA_USB2_RBIAS H19 PA_USB2_MXCTL PB_USB2_MXCTL F19 TBTB_USB2_RBIAS 1 2
B PA_USB2_RBIAS PB_USB2_RBIAS 200_0201_1% RT164
B
V8 W5 TEST_PWRGD 1 2
THERMDA TEST_PWR_GOOD R4 100_0201_5% RT165 +3VALW CT9
D4 TEST_EN B23 0.1U_0201_10V6K
L8 TEST_EDM USB2_ATEST AB23 1 2
FUSE_VQPS_64 PCIE_ATEST J9
DEBUG ATEST_P
A23 J11
A1 PA_MONDC ATEST_N H5 UT19
PB_MONDC VGA_RES
5
AC23 TC7SH08FU_SSOP5~D
AC1 PC_MONDC RT334 1 2 0_0201_5% 1
<14,27,52,55,66,68,69,79> PCH_PLTRST#_EC
P
D5 USB_MONDC B 4 TBT_PERST#_R 1 2 TBT_PERST#
MONDC_SVR RT335 1 2 0_0201_5% 2 O RT337 0_0201_5%
<13> PCH_PLTRST#_EC_AR A
1
TBT_PERST_N/GPP_F_4
RT338
3
100K_0201_5%
THUNDERBOLT_BGA337
Titan Redge DP
2
+3VALW
For vPRO docking support vHPD

1
CT10
0.1U_0201_10V6K
UT18 2
PCH/TBT_Wake_N/GPP_K_18 TBT_WAKE# RT340 1 2 0_0201_5% 1 5
<16> TBT_WAKE# NO V+
TBT_A_HPD_SCL RT5842 1 @ 2 0_0201_5% SML0_SMBCLK PCIE_WAKE# RT343 1 2 0_0201_5% 3 4 TBT_PCIE_WAKE#_R 1 2 TBT_PCIE_WAKE#
SML0_SMBCLK <15> EC <52,58,68,69> PCIE_WAKE# NC COM RT346 0_0201_5%
1
RT5843 1 2 0_0201_5% TBT_A_HPD 1 2 6 2
TBT_A_HPD <44> <58> RTD3_SELECT IN GND
RT345 0_0201_5% RT347
1
TS5A3159ADCKR_SC70-6 1M_0201_5%
RT348
10K_0201_5%
2
RTD3 GPIO refer by Intel RVP
2
TBT_B_HPD_SDA RT5844 1 @ 2 0_0201_5% SML0_SMBDATA
SML0_SMBDATA <15>
RT5845 1 2 0_0201_5% TBT_B_HPD GPIO intel RVP Fiorano FUNCTION TABLE
TBT_B_HPD <44>
NC TO COM NO TO COM
IN IN NC NO
A TBT_PERST_N GPP_F_4_SATAXPCIE PCH_PLTRST#_EC_AR/GPP_F4 COM TO NC COM TO NO A
TBT_Wake_N GPP_K_18_NMIB TBT_WAKE#/GPP_K18 L ON OFF L COM X
RTD3_PWN_EN GPP_H_16_SML4_CLK RTD3_CIO_PWR_EN/GPP_H16 H OFF ON H X COM
Vinafix.com
Title
TBT-TR(1/2) DP, PCIE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom
LA-J191P 0.4(X03)
5 4 3 2 1
5 4 3 2 1
+3.3V_TBT_S0 change pn to SHI0000N600 +3VS
1 2 +3.3V_TBT_SX
LT14 1UH_LQM18NN1R0K00D_10% UT1B
+0.9V_TBT_SVR +3.3V_TBT_S0
1U_0201_6.3V6M
47U_0603_6.3V6M
47U_0603_6.3V6M
1 1 1
H9 G1 input
VCC0P9_SVR_PAB_ANA1 VCC3P3_SVR1
Output H11 G2
CT163
CT164
CT165
H12 VCC0P9_SVR_PAB_ANA2 VCC3P3_SVR2 H2
2 2 2 H13 VCC0P9_SVR_PAB_ANA3 VCC3P3_SVR3 E6
H15 VCC0P9_SVR_PAB_ANA4 VCC3P3A
H16 VCC0P9_SVR_PAB_ANA5 L6
VCC0P9_SVR_PAB_ANA6 VCC3P3_S0 +3.3V_TBT_SX
D D
T12 F18 +3VALW
T13 VCC0P9_SVR_PC_ANA1 VCC3P3_SX1 R6
VCC0P9_SVR_PC_ANA2 VCC3P3_SX2
input
T15 +0.9V_TBT_SVR
VCC0P9_SVR_PC_ANA3 J13
T9 VCC0P9_SVR1 L11
T11 VCC0P9_SVR_USB_ANA1 VCC0P9_SVR2 L13
VCC0P9_SVR_USB_ANA2 VCC0P9_SVR3
Output
M8
+0.9V_TBT_PCIE N6 VCC0P9_SVR4 M11
VCC0P9_SVR_DPAUX_ANA VCC0P9_SVR5 M13
J18 VCC0P9_SVR6 N8
L19 VCC0P9_PCIE VCC0P9_SVR7 N11
M19 VCC0P9_ANA_PCIE_1_1 VCC0P9_SVR8 N13
L18 VCC0P9_ANA_PCIE_1_2 VCC0P9_SVR9 R8
M16 VCC0P9_ANA_PCIE_2_1 VCC0P9_SVR10 R11
M18 VCC0P9_ANA_PCIE_2_2 VCC0P9_SVR11 R13
+0.9V_TBT_LC VCC0P9_ANA_PCIE_2_3 VCC0P9_SVR12 R16
VCC0P9_SVR13 T8
J8 VCC0P9_SVR14 T16 +TBT_SVR_IND
+0.9V_TBT_LVR_OUT VCC0P9_LC VCC0P9_SVR15 E8
VCC0P9_SVR_BRD_SENSE
VCC
H8
H6 VCC0P9_LVR K1
VCC0P9_LVR_SENSE SVR_IND1 K2
SVR_IND2 L1
H18 SVR_IND3 L2
L16 VCC3P3_ANA_USB2 SVR_IND4
E16 VCC3P3_ANA_PCIE H1
+3.3V_TBT_ANA VCC3P3_ANA SVR_VSS1 J1
+3.3V_TBT_ANA_PCIE +3.3V_TBT_LC V6 SVR_VSS2 J2
VCC3P3_LC SVR_VSS3
+3.3V_TBT_ANA_USB2 Output
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10K_0201_5%
2
1 1 1 1 A6 AB18
Pin H18
Pin L16
Pin E16
A8 VSS_ANA1 VSS_ANA67 AB20
CT100
CT399
RT554
CT302
CT539
Pin V6
A10 VSS_ANA2 VSS_ANA68 AB22
A12 VSS_ANA3 VSS_ANA69 AC6
2 2 2 2 A14 VSS_ANA4 VSS_ANA70 AC8
VSS_ANA5 VSS_ANA71
1
A16 AC10
C C
B6 VSS_ANA9 VSS_ANA75 AC18
B12 VSS_ANA12 VSS_ANA78 E4
B14 VSS_ANA13 VSS_ANA79 F5
B16 VSS_ANA14 VSS_ANA80 J12
B18 VSS_ANA15 VSS_ANA81 F6
B20 VSS_ANA16 VSS_ANA82 J15
B22 VSS_ANA17 VSS_ANA83 B2
D8 VSS_ANA18 VSS_ANA84 B1
D9 VSS_ANA19 VSS_ANA85 D1
D11 VSS_ANA20 VSS_ANA86 A2
D12 VSS_ANA21 VSS_ANA87 J16
D13 VSS_ANA22 VSS_ANA88 V13
D18 VSS_ANA25 VSS_ANA91 M6
GND
E9 VSS_ANA26 VSS_ANA92 U23
E11 VSS_ANA27 VSS_ANA93 U22
E15 VSS_ANA28 VSS_ANA94 T20
H20 VSS_ANA29 VSS_ANA95 R23
E22 VSS_ANA30 VSS_ANA96 R22
E23 VSS_ANA31 VSS_ANA97 R20
F9 VSS_ANA32 VSS_ANA98 R19
F16 VSS_ANA33 VSS_ANA99 R18
F20 VSS_ANA34 VSS_ANA100 W11
G22 VSS_ANA35 VSS_ANA101 Y11
G23 VSS_ANA36 VSS_ANA102 C23
L20 VSS_ANA37 VSS_ANA103 F15
L22 VSS_ANA38 VSS_ANA104 V9
+0.9V_TBT_SVR L23 VSS_ANA39 VSS_ANA105 V15
J19 VSS_ANA40 VSS_ANA106 V20
+3.3V_TBT_SX J20 VSS_ANA41 VSS_ANA107 W8
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
J22 VSS_ANA42 VSS_ANA108 W9

J23 VSS_ANA43 VSS_ANA109 W22
1 1 1 1 1 1 1
Pin E8
Pin H11
Pin H13
Pin H16
Pin J13
Pin L11
Pin M11
B
+3VALW M20 VSS_ANA44 VSS_ANA110 W23 B
CT305
CT306
CT307
CT308
CT309
CT310
CT311
N20 VSS_ANA45 VSS_ANA111 Y9

N22 VSS_ANA46 VSS_ANA112 Y13
1U_0201_6.3V6M
1U_0201_6.3V6M
2 2 2 2 2 2 2 N23 VSS_ANA47 VSS_ANA113 AA22
C22 VSS_ANA48 VSS_ANA114 AA23
1 1 VSS_ANA49 VSS_ANA115
E18 AB6
CT314
CT315
Pin R6
Pin F18
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
W13 VSS_ANA50 VSS_ANA116 AB8

AB2 VSS_ANA51 VSS_ANA117 AB10
Pin N6
Pin R8
Pin T8
1 1 1 1 1 1 1
Pin N11
Pin R16
Pin T13
Pin T16
2 2 A4 VSS_ANA52 VSS_ANA118 AB12

CT316
CT317
CT318
CT319
CT320
CT321
CT322
B4 VSS_ANA53 VSS_ANA119 AB14

+0.9V_TBT_SVR Y8 VSS_ANA54 VSS_ANA120 AB16
2 2 2 2 2 2 2 F2 VSS_ANA55 VSS_ANA121 N19
D2 VSS_ANA56 VSS_ANA122 N18
F1 VSS_ANA57 VSS_ANA123 F8
AC4 VSS_ANA58 VSS_ANA124 F13
AB4 VSS_ANA59 VSS_ANA125 F12
Y5 VSS_ANA60 VSS_ANA126 F11
+3.3V_TBT_S0 Y12 VSS_ANA61 VSS_ANA127 E13
W12 VSS_ANA62 VSS_ANA128 E12
D6 VSS_ANA63 VSS_ANA129 W15
AB1 VSS_ANA64 VSS_ANA130 Y15
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
AC2 VSS_ANA65 VSS_ANA131

CT323
CT324
CT325
CT326
1 1 1 1 1 1 VSS_ANA66
CT327
CT328
Pin E6
Pin L6
+0.9V_TBT_LVR_OUT +0.9V_TBT_LC
SVR_VSS:Minimum of 4 vias must be used.
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
2 2 2 2 2 2
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
10U_0402_6.3V6M
10U_0402_6.3V6M
1 1 1 1 1
Pin H6
Pin H8
Pin J8
Share same GND plane

CT329
CT330
CT331
CT332
CT333
L12
R15
R12
M9
L15
N15
M1
M2
N12
M15
V16
R9
L9
F4
V18
T6
T18
N9
M12
2 2 2 2 2
+TBT_SVR_IND
+0.9V_TBT_SVR
VCC0P9_SVR:0.9V @ 1.8A max +0.9V_TBT_PCIE
A Minimum of 4vias must be used A
LT10 1 2 0.68UH_MLV-YT10NR68N-M1L_2.7A_30%
10U_0402_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
47U_0603_6.3V6M
47U_0603_6.3V6M
47U_0603_6.3V6M
CT334
CT335
CT336
1 1 1 1
CT337
1 1 1 1
Pin L19
Pin M19
Pin L18
Pin M16
CT338
CT339
CT340
CT341
THUNDERBOLT_BGA337
2 2 2 2
2 2 2 2
Title
TBT-TR(2/2) PWR,VSS
C LA-J191P 0.4(X03)
5 4 3 2 1
5 4 3 2 1
+5VALW +VDDD_SUPPLY_3.3V
+Vsys
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1 1 1 1 1
CT48
CT45
CT46
CT49
CT55
CT57
CT555
2 2 2 2 2 2 2
+VDDD_SUPPLY_3.3V UT11 +TBT_VBUS1 +TBT_VBUS2
D10 D1 input
D TBT_I2C_SDA VDDD VBUS_P1 D
3.3V Output
C10 L3 input
TBT_I2C_SCL VDD_IO VBUS_P2 +3V_LDO
CT50 1U_0201_6.3V6M
+5VALW +5VALW 2 1 B10 input
VCCD A5 +Vsys RT52 1BreakDown@
2 0.01_0603_1%
1000P_0201_25V7K
1000P_0201_25V7K
@ @ J2 VSYS
1 1 20Mil
V5V_P1
CA250
CA251
20Mil L9 CYPD5225-96BZXI_BGA96_6X6
V5V_P2 J1
2 2 CSP_P1
+3VALW CCG5_XRES1 H6 L2
<42> CCG5_AR_RST# XRES CSP_P2
1 2 CCG5_SWD_IO1 B2 B3
SW D_IO/AR_RST# /GPIO_B2 CSN_P1
2
RT665 0_0201_5%
2.2K_0201_5%
2.2K_0201_5%
2.2K_0201_5%
2.2K_0201_5%
+VDDD_SUPPLY_3.3V I2C_ADDR_CFG1 C2 K8
RT161
RT159
RT157
RT153
SW D_CLK/I2C_CFG_EC/GPIO_C2 CSN_P2
I2C_SLAVE TO COMMUNICATE
WITH TR
I2C_PD_DAT
1
<42> TBT_I2C_SDA RT196 1 2 0_0201_5% D2 H4
RT108 1 2 49.9K_0201_1% CCG5_VBUS_5V_ON1# I2C_SDA_SCB2_AR/GPIO_D2 NC1 H5
TR <42> TBT_I2C_SCL RT197 1 2 0_0201_5% I2C_PD_CLK E2
I2C_SCL_SCB2_AR/GPIO_E2
NC2
NC3
H8 +3VALW
RT109 1 2 49.9K_0201_1% CCG5_VBUS_5V_ON2# G8
RT198 1 2 0_0201_5% F2 NC4
<42> TBTA_I2C_INT#
RT110 1 2 49.9K_0201_1% VBUS_C_CTRL_P1# I2C_INT_AR_P1/GPIO_F2
RT199 1 2 0_0201_5% G2 L4 MOD_ID2
<42> TBTB_I2C_INT#
RT111 1 2 49.9K_0201_1% VBUS_C_CTRL_P2# I2C_INT_AR_P2/GPIO_G2 VSEL_1_P2 / GPIO_L4 H10 TBT_A_SBU2 RT154 1 @ 2 100K_0201_5%
VSEL_2_P2 / GPIO_H10 B6
CCG5_SWD_IO1 UV_OCP_TRIP_P1 / GPIO_B6 2 0_0201_5% CCG5_ILIM2# TBT_B_SBU2
Pull up at EC side
RT150 1 @ 2 4.7K_0201_5% L5 B7 RT120 1 RT155 1 @ 2 100K_0201_5%
<58> CCG5_I2C_INT1# I2C_INT_EC/GPIO_L5 UV_OCP_TRIP_P2 / GPIO_B7 B8
CCG5_SMBDAT K6 VCON_OCP_TRIP_P1 / GPIO_B8 B9
<58,59> CCG5_SMBDAT I2C_SDA_SCB1_EC/GPIO_K6 VCON_OCP_TRIP_P2 / GPIO_B9 G10
CCG5_XRES1
EC <58,59> CCG5_SMBCLK
CCG5_SMBCLK L6
I2C_SCL_SCB1_EC/GPIO_L6
SDA_4/GPIO_G10
SCL_4/GPIO_F10
F10 FRS_ON_P1
FRS_ON_P2
+VDDD_SUPPLY_3.3V RT104 1 2 4.7K_0201_5% L7
GPIO_L7 TBT_A_SBU1 RT156 1 @ 2 100K_0201_5%
CT119 1 2 0.1U_0201_10V6K TBT_B_SBU1 RT158 1 @ 2 100K_0201_5%
L8 K5
OVP_TRIP_P2 / GPIO_L8 OVP_TRIP_P1 / GPIO_K5
MOD_ID1 L10 J10 RT119 1 2 0_0201_5% CCG5_ILIM1#
C SCL_3 / VSEL_1_P1 /GPIO_L10 SDA_3 / VSEL_2_P1 / GPIO_J10 C
Dual CCG5 I2C address:0x40

CCG5_VBUS_5V_ON2# B4 K3 CCG5_VBUS_5V_ON1#
VBUS_P_CTRL_P2/ P4_2 VBUS_P_CTRL_P1
RT103 1 @ 2 1K_0201_5% I2C_ADDR_CFG1 VBUS_C_CTRL_P2# B5 K4 VBUS_C_CTRL_P1#
+VDDD_SUPPLY_3.3V <81> VBUS_C_CTRL_P2# VBUS_C_CTRL_P2/ P4_1 VBUS_C_CTRL_P1 VBUS_C_CTRL_P1# <81>
(0 - VBUS Path on, Z- VBUS (0 - VBUS Path on, Z- VBUS
Path off) Path off)
RT105 1 2 1K_0201_5%
To configure CCG5 I2C address

<45> TBTB_CC1 K9 K2 TBTA_CC1 <45>
Don't mount RT103 and RT105 for the I2C TBTB_CC2(K2) PINA5 1 2 CC1_P2 CC1_P1 1 2 TBTA_CC1(K2) PINA5
address 0x08. This is the default one.
Mount RT105 for the I2C address 0x40. CT51 390P_0201_50V7K CT53 390P_0201_50V7K
Mount RT103 for the I2C address 0x42. <45> TBTB_CC2
K10 H2 TBTA_CC2 <45>
TBTB_CC2(K10) PINB5 1 2 CC2_P2 CC2_P1 1 2 TBTA_CC2(H2) PINB5
CT59 390P_0201_50V7K CT58 390P_0201_50V7K
+3VALW RT57 1 @ 2 10K_0201_5% RT55 1 @ 2 10K_0201_5% +3VALW
E10/T1 <42> TBT_B_HPD E10 K7 K7/T2
HPD_P2/GPIO_E10 HPD_P1/GPIO_K7 TBT_A_HPD <42>
Pull down on TBT Pull down on TBT
RT69 1 2 0_0201_5% K11 A10 RT163 1 2 0_0201_5%
RT64 1 2 0_0201_5% L11 LSTX_P2/GPIO_K11 LSTX_P1/GPIO_A10 A11 RT170 1 2 0_0201_5%
CCG5 debug TBT_B_SBU1
LSRX_P2/GPIO_L11 LSRX_P1/GPIO_A11
TBT_A_SBU1
AMI still suggest us to reserve it for source level debug.
<42> TBT_B_SBU1
D11 B11 TBT_A_SBU1 <42> A10+B11/H4
+VDDD_SUPPLY_3.3V K11+D11/L4 TBT_B_SBU2 E11 AUX_P_P2/GPIO_D11 AUX_P_P1/GPIO_B11 C11 TBT_A_SBU2 A11+C11/J4
<42> TBT_B_SBU2 AUX_N_P2/GPIO_E11 AUX_N_P1/GPIO_C11 TBT_A_SBU2 <42>
JCCG1 L11+E11/L5
1 SBU1(E1)/A8 <45> TBTB_SBU1
E1 A3 TBTA_SBU1 <45> SBU1(A3)/A8
1 2 CCG5_XRES1 SBU1(F1)/B8 F1 SBU1_P2 SBU1_P1 A4
2 3 I2C_ADDR_CFG1 <45> TBTB_SBU2 SBU2_P2 SBU2_P1 TBTA_SBU2 <45> SBU1(A4)/B8
3 4 CCG5_SWD_IO1 TBT PORT B
4 5 CCG5_SMBDAT +5VALW CCG5_SMBCLK RT67 1 2 0_0201_5% H11 A8 RT265 1 2 0_0201_5% CCG5_SMBCLK
TBT PORT A
5 6 CCG5_SMBCLK CCG5_SMBDAT RT68 1 2 0_0201_5% J11 UART_TX_P2/GPIO_H11 UART_TX_P1/GPIO_A8 A9 RT264 1 2 0_0201_5% CCG5_SMBDAT
6 7 UART_RX_P2/GPIO_J11 UART_RX_P1/GPIO_A9
7 8 UART2TXD RT183 1 2 0_0201_5% F11 A6
8 9 UART2_TXD <17> <16> USB20_P5 D+_SYS_P2 D+_SYS_P1 USB20_P4 <16>
UART2RXD RT184 1 2 0_0201_5% UART2_RXD <17> <16> USB20_N5 G11 A7 USB20_N4 <16>
9 10 D-_SYS_P2 D-_SYS_P1
10 K1 B1 D+_B_P1/D+_B6
<45> SW_TBT_B_USB20_P2 D+_B_P2 D+_B_P1 SW_TBT_A_USB20_P2 <45>
D+_B_P2/D+_B6 L1 C1 D-_B_P1/D-_B7
<45> SW_TBT_B_USB20_N2 D-_B_P2 D-_B_P1 SW_TBT_A_USB20_N2 <45>
11 D-_B_P2/D-_B7 G1 A1 D+_T_P1/D+_A6
GND1 <45> SW_TBT_B_USB20_P1 D+_T_P2 D+_T_P1 SW_TBT_A_USB20_P1 <45> D-_T_P1/D-_A7
B 12 D+_T_P2/D+_A6 H1 A2 B
GND2 D-_T_P2/D-_A7 <45> SW_TBT_B_USB20_N1 D-_T_P2 D-_T_P1 SW_TBT_A_USB20_N1 <45>
D5 H7
ACES_50521-01041-P01 D6 GND1 GND19 G7
D7 GND2 GND18 G6
CONN@ GND3 GND17
D8 G5
E4 GND4 CSP_GND_P2 G4
E5 GND5 CSP_GND_P1 F8
E6 GND6 GND14 F7
E7 GND7 GND13 F6
E8 GND8 GND12 F5
Type-C port1 USB2 Power Share GND9 GND11
GND10
F4
+3VALW CT68
+TBT_VBUS1 +5VALW 2 1 SA0000AIJ50, S IC CYPD5225-96BZXIT BGA USB-CTR FDQ50
UT10
1 10
2 VOUT1 VIN1 9 0.1U_0201_10V6K
VOUT2 VIN2
5
UT9
1 CCG5_VBUS_5V_ON1#
<16> USB_OC4#
enable Active high. K3 CCG5_R_Port1 RILIM ILIM(A)(14300/RLIM)
G Vcc
3 8 4 B
CCG5_ILIM1#
FRS_ON_P1 1 2 FRS_ON1_R 5 FLTB EN 7 USB_ILIM1 Y 2 (Kohm)
0_0201_5% RT142 FON ILIM A enable Active low +5VALW +TBT_VBUS1 Min Typ Max CCG5_ILIM2#
74AUP1G02GW_TSSOP5
3.84K 3.165 3.723 4.282 HIGH MOD_ID1=L1,MOD_ID2=N/A, Titan Ridge
3
2
4 6
NC GND 11
10U_0402_10V6M
RT93
EXP 7.68K 1.582 1.861 2.140 LOW
10U_0603_25V6M
100K_0201_5% 1 1
AOZ1356DI-01_DFN12_3X3 +VDDD_SUPPLY_3.3V +VDDD_SUPPLY_3.3V
CT250
CT56
USB_ILIM2 USB_ILIM1
1
2 2
1
1
1
RT179 RT176
Type-C port2 USB2 Power Share RT180

7.68K_0402_1%
RT173
7.68K_0402_1%
100K_0201_1%
L1 =VDD/8=0.4125V
@ 100K_0201_1%
N/A
close UT10,PIN12 UT10.PIN1
MOD_ID1 MOD_ID2
2
CCG5_ILIM2# CCG5_ILIM1#
2
1
1
+TBT_VBUS2 +5VALW +3VALW CT69 +5VALW +TBT_VBUS2
1
RT175 RT174
2 1 7.68K_0402_1% 7.68K_0402_1% RT177 RT178
100K_0201_5%
100K_0201_5%
D D
2
A UT12 QT12 QT13 14.3K_0201_1% @ 100K_0201_1%
RT171
RT172
A
10U_0402_10V6M
1 10 2 2
VOUT1 VIN1 0.1U_0201_10V6K
2
2 9
10U_0603_25V6M
1 1 G G
VOUT2 VIN2
2
5
UT13
CT52
CT54
S S
CCG5_VBUS_5V_ON2#
3
1
<16> USB_OC5#
enable Active high. B4 CCG5_R_Port2 L2N7002WT1G_SC-70-3
G Vcc
1
3 8 4 L2N7002WT1G_SC-70-3
FRS_ON_P2 1 2 FRS_ON2_R 5 FLTB EN 7 USB_ILIM2 Y 2 2 2
0_0201_5% RT143 FON ILIM A enable Active low Resistor values for MOD_ID settings
are decides based on the table shown
2
74AUP1G02GW_TSSOP5
Need Cypree advice
3
4 6 RT91
NC
GND 11 100K_0201_5%
EXP close UT12, PIN12 UT12, PIN1
AOZ1356DI-01_DFN12_3X3
1
PD CTRL - CCG5 Dual Port
5 4 3 2 1
Vinafix.com
5 4 3 2 1
TBT_A_TRX_DTX_P1 1 2
DT3 AZ5B75-01B.R7G_CSP0603P2Y2
EMC@
TBT_A_TRX_DTX_N1 1 2
+TBT_VBUS1 +TBT_VBUS1 EMC@
TBTA_SBU2 1 2
EMC@ DT4 AZ5B75-01B.R7G_CSP0603P2Y2
D+_B_P1/D+_B6 DLM0NSN900HY2D_4P EMC@
4 3 SW _TBT_A_USB20_P2_C JUSBC2
<44> SW _TBT_A_USB20_P2 4 3 SW _TBT_A_USB20_N2_C
A1 B12 1 2
D-_B_P1/D-_B7 GND_A1 GND_B12 DT6 AZ5B75-01B.R7G_CSP0603P2Y2
1 2 SW _TBT_A_USB20_N2_C TBT_A_TTX_DRX_P1 A2 B11 TBT_A_TRX_DTX_P1 EMC@
<44> SW _TBT_A_USB20_N2 1 2 <42> TBT_A_TTX_DRX_P1 TBT_A_TTX_DRX_N1 SSTXP1 SSRXP1 TBT_A_TRX_DTX_N1 TBT_A_TRX_DTX_P1 <42>
A3 B10
LT7 <42> TBT_A_TTX_DRX_N1 SSTXN1 SSRXN1 TBT_A_TRX_DTX_N1 <42> SW _TBT_A_USB20_P2_C 1 2
CT167 1 2 0.47U_0402_25V6K A4 B9 CT166 1 2 0.47U_0402_25V6K DT8 AZ5B75-01B.R7G_CSP0603P2Y2
VBUS_A4 VBUS_B9 EMC@
D TBTA_CC1 A5 B8 TBTA_SBU2 D
<44> TBTA_CC1 CC1 SUB2 TBTA_SBU2 <44> TBTA_CC2 1 2
SW _TBT_A_USB20_P1_C A6 B7 SW _TBT_A_USB20_N2_C DT10 AZ5B75-01B.R7G_CSP0603P2Y2
EMC@ SW _TBT_A_USB20_N1_C A7 DP1 DN2 B6 SW _TBT_A_USB20_P2_C EMC@
D+_T_P1/D+_A6 DLM0NSN900HY2D_4P DN1 DP2
Bottom
4 3 SW _TBT_A_USB20_P1_C TBTA_SBU1 A8 B5 TBTA_CC2 TBT_A_TTX_DRX_N2 1 2
<44> SW _TBT_A_USB20_P1 4 3 <44> TBTA_SBU1 SUB1 CC2 TBTA_CC2 <44>
TOP
CT365 1 2 0.47U_0402_25V6K A9 B4 CT168 1 2 0.47U_0402_25V6K EMC@
1 2 SW _TBT_A_USB20_N1_C VBUS_A9 VBUS_B4
<44> SW _TBT_A_USB20_N1 1 2 TBT_A_TRX_DTX_N2 TBT_A_TTX_DRX_N2 TBT_A_TTX_DRX_P2
A10 B3 1 2
LT6 <42> TBT_A_TRX_DTX_N2 TBT_A_TRX_DTX_P2 SSRXN2 SSTXN2 TBT_A_TTX_DRX_P2 TBT_A_TTX_DRX_N2 <42>
D-_T_P1/D-_A7
<42> TBT_A_TRX_DTX_P2 A11 B2 TBT_A_TTX_DRX_P2 <42> DT14 AZ5B75-01B.R7G_CSP0603P2Y2
SSRXP2 SSTXP2 EMC@
A12 B1
GND_A12 GND_B1
1 4
2 GND1 GND4 5 TBT_A_TTX_DRX_P1 1 2
+TBT_VBUS1 3 GND2 GND5 6 DT2 AZ5B75-01B.R7G_CSP0603P2Y2
8 GND3 GND6 7 EMC@
GND8 GND7
11/21 JUSBC GND7 GND8 is NPTH TBT_A_TTX_DRX_N1
FOX_UT11123-107B9-7H 1 2
CONN@ DT7 AZ5B75-01B.R7G_CSP0603P2Y2
EMC@
1
TBTA_CC1 1 2
DT34 EMI@ EMC@
AZ4520-01F.R7G_DFN1610P2E2
SW _TBT_A_USB20_P1_C 1 2
2
DVT2.1_13:USBC2 footprint change and NPTH change from GND5,GND6 to GND7,GND8 DT11 AZ5B75-01B.R7G_CSP0603P2Y2
EMC@
SW _TBT_A_USB20_N1_C 1 2
EMC@
EMI request TBTA_SBU1 1 2
EMC@
TBT_A_TRX_DTX_N2 1 2
C C
EMC@
TBT_A_TRX_DTX_P2 1 2
EMC@
TBT_B_TRX_DTX_P1 1 2
EMC@
TBT_B_TRX_DTX_N1 1 2
+TBT_VBUS2 +TBT_VBUS2 DT20 AZ5B75-01B.R7G_CSP0603P2Y2
EMC@
TBTB_SBU2 1 2
JUSBC1 EMC@
A1 B12
EMC@ GND_A1 GND_B12 SW _TBT_B_USB20_N2_C 1 2
D-_B_P2/D-_B7 DLM0NSN900HY2D_4P TBT_B_TTX_DRX_P1 A2 B11 TBT_B_TRX_DTX_P1 DT23 AZ5B75-01B.R7G_CSP0603P2Y2
SW _TBT_B_USB20_N2_C <42> TBT_B_TTX_DRX_P1 TBT_B_TTX_DRX_N1 SSTXP1 SSRXP1 TBT_B_TRX_DTX_N1 TBT_B_TRX_DTX_P1 <42>
4 3 A3 B10 EMC@
<44> SW _TBT_B_USB20_N2 4 3 <42> TBT_B_TTX_DRX_N1 SSTXN1 SSRXN1 TBT_B_TRX_DTX_N1 <42>
CT171 1 2 0.47U_0402_25V6K A4 B9 CT170 1 2 0.47U_0402_25V6K SW _TBT_B_USB20_P2_C 1 2
1 2 SW _TBT_B_USB20_P2_C VBUS_A4 VBUS_B9 DT25 AZ5B75-01B.R7G_CSP0603P2Y2
<44> SW _TBT_B_USB20_P2 1 2 TBTB_CC1 TBTB_SBU2
A5 B8 EMC@
LT1 <44> TBTB_CC1 CC1 SUB2 TBTB_SBU2 <44>
D+_B_P2/D+_B6
EMC@ SW _TBT_B_USB20_P1_C A6 B7 SW _TBT_B_USB20_N2_C TBTB_CC2 1 2
D+_T_P2/D+_A6 DLM0NSN900HY2D_4P SW _TBT_B_USB20_N1_C A7 DP1 DN2 B6 SW _TBT_B_USB20_P2_C DT26 AZ5B75-01B.R7G_CSP0603P2Y2
4 3 SW _TBT_B_USB20_P1_C DN1 DP2 EMC@
<44> SW _TBT_B_USB20_P1
Bottom
4 3 TBTB_SBU1 A8 B5 TBTB_CC2
<44> TBTB_SBU1 SUB1 CC2 TBTB_CC2 <44> TBT_B_TTX_DRX_N2 1 2
TOP
1 2 SW _TBT_B_USB20_N1_C CT169 1 2 0.47U_0402_25V6K A9 B4 CT172 1 2 0.47U_0402_25V6K DT29 AZ5B75-01B.R7G_CSP0603P2Y2
B <44> SW _TBT_B_USB20_N1 B
1 2 VBUS_A9 VBUS_B4 EMC@
D-_T_P2/D-_A7 LT5 TBT_B_TRX_DTX_N2 A10 B3 TBT_B_TTX_DRX_N2
<42> TBT_B_TRX_DTX_N2 TBT_B_TRX_DTX_P2 SSRXN2 SSTXN2 TBT_B_TTX_DRX_P2 TBT_B_TTX_DRX_N2 <42> TBT_B_TTX_DRX_P2
A11 B2 1 2
<42> TBT_B_TRX_DTX_P2 SSRXP2 SSTXP2 TBT_B_TTX_DRX_P2 <42>
A12 B1 EMC@
GND_A12 GND_B1
1 4
2 GND1 GND4 5
3 GND2 GND5 6 TBT_B_TTX_DRX_P1 1 2
GND3 GND6 11/21 JUSBC GND7 GND8 is NPTH
8 7 DT19 AZ5B75-01B.R7G_CSP0603P2Y2
GND8 GND7 EMC@
+TBT_VBUS2 FOX_UT11123-107B9-7H
TBT_B_TTX_DRX_N1 1 2
CONN@
EMC@
TBTB_CC1 1 2
1
EMC@
DT33 EMI@ DVT2.1_13:USBC1 footprint change and NPTH change from GND5,GND6 to GND7,GND8 SW _TBT_B_USB20_P1_C 1 2
AZ4520-01F.R7G_DFN1610P2E2 DT27 AZ5B75-01B.R7G_CSP0603P2Y2
EMC@
2
SW _TBT_B_USB20_N1_C 1 2
EMC@
TBTB_SBU1 1 2
EMI request DT30 AZ5B75-01B.R7G_CSP0603P2Y2
EMC@
TBT_B_TRX_DTX_N2 1 2
EMC@
TBT_B_TRX_DTX_P2 1 2
EMC@
A A

Size
P045-PD USB TYPE-C CONN.
Document Number Rev
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Vinafix.com Security Classification Compal Secret Data
Title
TBT-TR(1/2) DP, PCIE
Size Document Number Re v
Custom
LA-J191P 0.4(X03)

5 4 3 2 1
5 4 3 2 1
+3V_MUX +3.3V_CPS +1.2V_RUN +1.2V_MUX +3V_MUX

+3V_MUX +3.3V_VDD_DCI
LT11 1 2
2
+3VALW +3V_MUX LT2 1 2 BLM18KG331SN1D_2P BLM18KG331SN1D_2P
0.1U_0201_10V6K
0.01U_0201_10V6K
0.1U_0201_10V6K
0.01U_0201_10V6K
0.1U_0201_10V6K
0.01U_0201_10V6K
0.1U_0201_10V6K
2 1
4.7U_0201_6.3V6M
0.1U_0201_10V6K
0.01U_0201_10V6K
1 1 1 1 1 1 1 1 1 1 0_0201_5% RT135 RT5841
CT153
CT139
CT135
CT149
CT156
CT142
CT145
CT154
CT141
CT157
10K_0201_5%
4.7U_0402_6.3V6M
0.1U_0201_10V6K
D 1 1 1 D
1BreakDown@
2
CT133
CT161
RT138 0.01_0603_1% CT116
1
2 2 2 2 2 2 2 2 2 2
1U_0201_6.3V6M PS8802_RST#
2 2 2
1
CT210
1U_0201_6.3V6M
2
X01:0508 CT113 0201 change 0402 1.2V power ripple requirement: <30mV
Need fine tuning sequence
+3V_MUX
CPU_DP3_AUXN_C_MUX RT121 1 2 100K_0201_5%
MUX_FLIP_SEL RT364 1 @ 2 100K_0201_5%

+3V_MUX MUX_USB_SEL RT72 1 2 4.7K_0201_5%
C
PD3_USBC_AMSEL RT362 1 @ 2 100K_0201_5% C
Crypress PD countrol PS880 by I2C to PS8802 port

TI PD PS880 by HW GPIO pin to PS8802 port
Pin36 need pull up
+1.2V_MUX +3.3V_CPS +3.3V_VDD_DCI
CPU_DP3_AUXP_C_MUX RT137 1 2 100K_0201_5%
1
4.7K_0201_5%
@ RT71
RX1p/B11
UT2
2
Address:0x10-0x2F
PS8802_ADDR
1 27
10 VDD_DM1 VDD33_1 52
16 VDD_DM2 VDD33_2
38 VDD_DM3 49
VDD_DM4 VDD_DCI
6 19 PS8802_ADDR
7 VDD_R1 ADDR0 22
VDD_R2 ADDR1
13 43 PS8802_RST#
VDD_A1 RESET#
1
47
4.7K_0201_5%
@ RT73
VDD_A2
PS8802_SBU1_R
30
VDD_D1 SBU1
33 0_0201_5% 2 1 RT101 MUX_SBU1 <48> SUB1 PINA8
34 PS8802_SBU2_R 2 1
SBU2
0_0201_5% RT100 MUX_SBU2 <48> SUB2 PINB8
2
2 MUX_USB3_RX0_P RT349 1 2 0_0201_5%

USB3_CRX_C_RD_DTX_P1 RX1p MUX_USB3_RX0_N MUX_USB3_RX0_P_RC RX1p/B11
<49>
CT86 1 2 0.22U_0201_6.3V6K 12 3 RT350 1 2 0_0201_5% RX1n/B10
USB3_1
<16> USB3_CRX_DTX_P1 USB3_CRX_C_RD_DTX_N1 SSRXp RX1n MUX_USB3_RX0_N_RC <49>

RX CT87 1 2 0.22U_0201_6.3V6K 11
<16> USB3_CRX_DTX_N1 SSRXn 9 MUX_USB3_RX1_P RT352 1 2 0_0201_5%
USB3_CTX_C_RD_DRX_P1 RX2p MUX_USB3_RX1_N MUX_USB3_RX1_P_RC <49> RX2p/A11
<16> USB3_CTX_DRX_P1
CT88 1 2 0.22U_0201_6.3V6K
USB3_CTX_C_RD_DRX_N1
15
SSTXp RX2n
8 RT351 1 2 0_0201_5% MUX_USB3_RX1_N_RC <49> RX2n/A10
TX CT89 1 2 0.22U_0201_6.3V6K 14
<16> USB3_CTX_DRX_N1 SSTXn 41 MUX_USB3_TX0_P_C 0.22U_0201_6.3V6K 1 2 CT102
ADDR: I2C control bus address. Internally pull down at 150k, 3.3V I/O TX1p 42 MUX_USB3_TX0_N_C 0.22U_0201_6.3V6K 1 2 CT103 MUX_USB3_TX0_P <49> TX1p/A2
L: Slave address 0x10-0x2F(default) CT90 1 2 0.22U_0201_6.3V6K CPU_DP3_P0_C 17 TX1n MUX_USB3_TX0_N <49>TX1n/A3
H: Slave address 0x30-0x4F <6> CPU_DP3_P0 CPU_DP3_N0_C ML0p MUX_USB3_TX1_P_C
<6> CPU_DP3_N0 CT91 1 2 0.22U_0201_6.3V6K 18 45 0.22U_0201_6.3V6K 1 2 CT104
B ML0n TX2p 44 MUX_USB3_TX1_N_C 0.22U_0201_6.3V6K 1 2 CT105 MUX_USB3_TX1_P <49> TX2p/B2 B
CT92 1 2 0.22U_0201_6.3V6K CPU_DP3_P1_C 20 TX2n MUX_USB3_TX1_N <49>TX2n/B3

DPEQ:DP Receiver equalization setting; Internally pull down at 150k, 3.3V I/O <6> CPU_DP3_P1 CPU_DP3_N1_C ML1p
<6> CPU_DP3_N1 CT93 1 2 0.22U_0201_6.3V6K 21
L: Compensation for channel loss up to 12dB(Default) ML1n 28 MUX_I2C_CLK_R 0_0201_5% 2 1 RT98 MUX_I2C_CLK <48>
DDI3
H: Compensation for channel loss up to 18dB CT94 1 2 0.22U_0201_6.3V6K CPU_DP3_P2_C 23 CSCL 29 MUX_I2C_DATA_R 0_0201_5% 2 1 RT95 MUX_I2C_DATA <48>
CCG5(PULL high on PD)
<6> CPU_DP3_P2 CPU_DP3_N2_C ML2p CSDA
<6> CPU_DP3_N2 CT95 1 2 0.22U_0201_6.3V6K 24
ML2n 35 PD3_USBC_AMSEL
CEQ: USB Type-C connector facing Rx channel receiver equalization setting; CT96 1 2 0.22U_0201_6.3V6K CPU_DP3_P3_C 25 CE_DP 36 MUX_USB_SEL
<6> CPU_DP3_P3 CPU_DP3_N3_C ML3p CE_USB MUX_FLIP_SEL keep R for debug
Internally pull down at 150k, 3.3V I/O. CT97 1 2 0.22U_0201_6.3V6K 26 37
L: Compensation for channel loss up to 16dB(Default) <6> CPU_DP3_N3 ML3n FLIP
H: Compensation for channel loss up to 18dB CT98 1 2 0.1U_0201_10V6K CPU_DP3_AUXP_C_MUX 31 40 PCH_DP3_HPD_R 0_0201_5% 2 1 RT86
<6> CPU_DP3_AUXP CPU_DP3_AUXN_C_MUX 32 AUXp IN_HPD PCH_DP3_HPD <13,48> Either Option#1 or Option#2
CT99 1 2 0.1U_0201_10V6K
SSEQ: USB Host facing Rx channel receiver equalization setting;
<6> CPU_DP3_AUXN AUXn 39 PS8802_REXT Option#2
Internally pull down at 150k, 3.3V I/O. REXT 4 GPIO control by PD
L: Compensation for channel loss up to 12dB(Default) DCI_CLK_R RSV1
<17> DCI_CLK RT89 1 2 0_0201_5%
DCI_DATA_R
50
DCI_CLK RSV2
5 CE_PD,CE_USB,FLIP
1
H: Compensation for channel loss up to 18dB RT92 1 2 0_0201_5% 51 46
DCI debug <17> DCI_DATA DCI_DATA RSV3 -----------------------------
48 RT84
RSV4 4.99K_0201_1% Option#1
I2C control by PD
53 CSCL,CSDA
ePAD
2
PS8802QFN52GTRA3_QFN52_6P5X4P5
SA0000AIM30, S IC PS8802QFN52GTR-A3 QFN 52P SWITCH
DVT2.1_07:update SA0000AIM30 Footprint
A A

Title
TBT-TR(2/2) PWR,VSS
Custom
LA-J191P 0.4(X03)
5 4 3 2 1
5 4 3 2 1
+Single_vsys +5VALW +VDDD2_SUPPLY_3.3V
1U_0201_6.3V6M
1U_0201_6.3V6M
1U_0201_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1 1 1 1 1
CT215
CT216
CT193
CT280
CT290
CT194
CT192
2 2 2 2 2 2 2
D D
+VDDD2_SUPPLY_3.3V UT5
CCG5 40-QFN
CCG5_VBUS_5V_ON3#
+3V_LDO 3.3V Output 31
VDDD VBUS_P_CTRL
11
32 12 VBUS_C_CTRL_P3#
VDDIO VBUS_C_CTRL VBUS_C_CTRL_P3# <81>
RT66 1BreakDown@
2 0.01_0603_1% +Single_vsys 19
VSYS
CT195 2 1 1U_0201_6.3V6M 33 20 USB_ILIM3# RT5847 1 @ 2 0_0201_5% USB_ILIM3
+VDDD2_SUPPLY_3.3V VCCD I2C_SDA_SCB3/GPIO/VSEL_2
21 Single_MOD_ID1 +3VALW DVT2_06 :
I2C_SCL_SCB3/GPIO/VSEL_1 Add RT5847 SD043000080 (0ohm) but unpop
Add Net name "USB_ILIM3#" to fix schematic issue
1
+5VALW
RT221
RT190 1 2 49.9K_0201_1% CCG5_VBUS_5V_ON3# @ 10K_0201_5%
8
RT191 1 2 49.9K_0201_1% VBUS_C_CTRL_P3# V5V
PCH_DP3_HPD
2
18
PCH_DP3_HPD HPD/GPIO PCH_DP3_HPD <13,47>
RT222 1 @ 2 100K_0201_5%
+3VALW 7
CC2 MUX_C_CC2 <49> CC2 PINB5
2 1
390P_0201_50V7K CT207
Type-C
1
10K_0201_5%
10K_0201_5%
RT242
RT341
9
CC1 MUX_C_CC1 <49> CC1 PINA5
2 1
2
390P_0201_50V7K CT208
Single CCG5 I2C address:0x42 <47> MUX_I2C_DATA
3
I2C_SDA_SCB2_TBT/GPIO
MUX PS8802 <47> MUX_I2C_CLK 4
I2C_SCL_SCB2_TBT/GPIO 26 D+_Bot/D+_B6
CCG5_I2C_ADDR_CFG3 Single_MOD_ID2 DPLUS_BOT SW _TBT_C_USB20_P2 <49>
RT5 1 2 1K_0201_5% 5
+VDDD2_SUPPLY_3.3V I2C_INT_TBT/GPIO SW _TBT_C_USB20_N2 <49>
25 D-_Bot/D-_B7
DMINUS_BOT
RT11 1 @ 2 1K_0201_5%
NoAR PORT C
C C
To configure CCG5 I2C address 28 D+_Top/D+_A6
Don't mount RT5 and RT11 for the I2C DPLUS_TOP SW _TBT_C_USB20_P1 <49>
address 0x08. This is the default one. 27 D-_Top/D-_A7
Mount RT11 for the I2C address 0x40. DMINUS_TOP SW _TBT_C_USB20_N1 <49>
Mount RT5 for the I2C address 0x42.
CCG5_SW D_DAT3 6
SWD_IO/AR_RST/GPIO 23
CCG5 debug CCG5_I2C_ADDR_CFG3 2
SWD_CLK/I2C_CFG_EC/GPIO
DPLUS_SYS USB20_P3 <16,51>
PCH USB2.0 (USB2.0 Redriver)
AMI still suggest us to reserve it for source level debug. 24 USB20_N3 <16,51>
DMINUS_SYS
Pull up at EC side
JCCG2 15
<58> CCG5_I2C_INT2# I2C_INT_EC/GPIO
1 29
1 2 CCG5_XRES3 +VDDD2_SUPPLY_3.3V CCG5_SMBDAT_L UART_TX/GPIO CCG5C_SMBCLK <40,48,58>
RT559 1 2 0_0201_5% 16
2 3 CCG5_I2C_ADDR_CFG3
CCG5_SW D_DAT3
EC <40,48,58> CCG5C_SMBDAT
CCG5_SMBCLK_L
I2C_SDA_SCB1_EC/GPIO 30 CCG5C_SMBDAT <40,48,58>
3 4 RT560 1 2 0_0201_5% 17 UART_RX/GPIO
4 5 CCG5_SMBDAT_L <40,48,58> CCG5C_SMBCLK I2C_SCL_SCB1_EC/GPIO
5 6 CCG5_SMBCLK_L
SUB2 PINB8 CCG5_SBU2 <49>
6 7 34
Type-C
7 8 +5VALW SBU2
SUB1 PINA8 CCG5_SBU1 <49>
8 9 35
9 10 SBU1
10 36
AUX_P/GPIO
SUB1 MUX_SBU1 <47>
1
11 CSP 37
GND1 12 AUX_N/GPIO
SUB2 MUX_SBU2 <47> PS8802
GND2 40 38
CSN LSTX/GPIO
+TBT_VBUS3 39
ACES_50521-01041-P01
LSRX/GPIO
CONN@ RT220 1 2 0_0603_5% 22
VBUS
+VDDD2_SUPPLY_3.3V 14
OVP_TRIP/I2C_SDA_CSB4/GPIO 13 FRS_ON_P3
RT230 1 2 4.7K_0201_5% CCG5_XRES3 10 UV_OCP_TRIP/I2C_SDA_SCB4/GPIO
XRES 41
2 VSS
CT206
0.1U_0201_10V6K
1
CYPD5125-40LQXIT_QFN40_6X6
B B
S IC CYPD5126-40LQXIT QFN USB CTRL FDQ50
Type-C port2 USB2 Power Share DVT2_02:change UT5 from SA0000CB200 to SA0000CB220 avoide mixing BOM
+TBT_VBUS3 +5VALW +3VALW CT201

2 1
UT4
1 10
Pull high ON PCH side 2 VOUT1 VIN1 9 0.1U_0201_10V6K
VOUT2 VIN2
5
<16> USB_OC3# UT3

1 CCG5_VBUS_5V_ON3#
enable Active high.
G Vcc
3 8 4 B
FRS_ON_P3 1 2 FRS_ON3_R 5 FLTB EN 7 USB_ILIM3 Y 2
0_0201_5% RT195 FON ILIM A enable Active low
FON Internal pulled down with a resistor 74AUP1G02GW_TSSOP5
3
2
4 6
NC GND 11 RT94
EXP
100K_0201_5%
AOZ1356DI-01_DFN12_3X3 Non-PD device get 1.65A@5V(ARD0.5)
1
RILIM ILIM(A)(14300/RLIM)
(Kohm) CCG5_ILIM3#
Min Typ Max
LOW
Re-driver PS8802
+5VALW +TBT_VBUS3 7.68K 1.582 1.861 2.140 HIGH
+VDDD2_SUPPLY_3.3V +VDDD2_SUPPLY_3.3V
USB_ILIM3
10U_0402_10V6M
10U_0603_25V6M
L0=0V (Unpop
1 1 LOW
1
RT240)
CT202
L4=VDD*4/8=1.65
CT196
RT206 L1-VDD/8 (pop RT240

HIGH RT240)
75K_0201_1% @ 100K_0201_1%
2 2
Single_MOD_ID1 Single_MOD_ID2
2
1
1
RT201
close UT10,PIN12 UT10.PIN1 7.68K_0402_1% RT204 RT290
A 75K_0201_1% 14.3K_0201_1% A
2
Size Document Number
PD CTRL - CCG5 Single Port
Rev
5 4 3 2 1
5 4 3 2 1
MUX_USB3_RX0_P_RC 1 2
EMC@
MUX_USB3_RX0_N_RC 1 2
EMC@
+TBT_VBUS3 +TBT_VBUS3
CCG5_SBU2 1 2
EMC@
EMC@
DLM0NSN900HY2D_4P JUSBC3 SW_TBT_C_USB20_N2_C 1 2
D+_Top/D+_A6 4 3 SW_TBT_C_USB20_P1_C A1 B12 DT46 AZ5B75-01B.R7G_CSP0603P2Y2
D <48> SW_TBT_C_USB20_P1 4 3 GND_A1 GND_B12 D
EMC@
MUX_USB3_TX0_P A2 B11 MUX_USB3_RX0_P_RC
SW_TBT_C_USB20_N1_C <47> MUX_USB3_TX0_P MUX_USB3_TX0_N SSTXP1 SSRXP1 MUX_USB3_RX0_N_RC MUX_USB3_RX0_P_RC <47> SW_TBT_C_USB20_P2_C
D-_Top/D-_A7 1 2 A3 B10 1 2
<48> SW_TBT_C_USB20_N1 1 2 <47> MUX_USB3_TX0_N SSTXN1 SSRXN1 MUX_USB3_RX0_N_RC <47>
LT9 C3175 1 2 0.47U_0402_25V6K A4 B9 CT573 1 2 0.47U_0402_25V6K EMC@
VBUS_A4 VBUS_B9
MUX_C_CC1 A5 B8 CCG5_SBU2 MUX_C_CC2 1 2
<48> MUX_C_CC1 CC1 SUB2 CCG5_SBU2 <48>
SW_TBT_C_USB20_P1_C A6 B7 SW_TBT_C_USB20_N2_C EMC@
SW_TBT_C_USB20_N1_C A7 DP1 DN2 B6 SW_TBT_C_USB20_P2_C
EMC@ DN1 DP2 MUX_USB3_TX1_N 1 2
Bottom
DLM0NSN900HY2D_4P CCG5_SBU1 A8 B5 MUX_C_CC2 DT49 AZ5B75-01B.R7G_CSP0603P2Y2
SW_TBT_C_USB20_P2_C <48> CCG5_SBU1 SUB1 CC2 MUX_C_CC2 <48>
D+_Bot/D+_B6 4 3 EMC@
TOP
<48> SW_TBT_C_USB20_P2 4 3 CT374 1 2 0.47U_0402_25V6K A9 B4 CT376 1 2 0.47U_0402_25V6K
VBUS_A9 VBUS_B4 MUX_USB3_TX1_P 1 2
D-_Bot/D-_B7 1 2 SW_TBT_C_USB20_N2_C MUX_USB3_RX1_N_RC A10 B3 MUX_USB3_TX1_N DT50 AZ5B75-01B.R7G_CSP0603P2Y2
<48> SW_TBT_C_USB20_N2 1 2 <47> MUX_USB3_RX1_N_RC MUX_USB3_RX1_P_RC SSRXN2 SSTXN2 MUX_USB3_TX1_P MUX_USB3_TX1_N <47>
A11 B2 EMC@
LT8 <47> MUX_USB3_RX1_P_RC SSRXP2 SSTXP2 MUX_USB3_TX1_P <47>
A12 B1
GND_A12 GND_B1
1 4 MUX_USB3_TX0_P 1 2
2 GND1 GND4 5 DT36 AZ5B75-01B.R7G_CSP0603P2Y2
+TBT_VBUS3 3 GND2 GND5 6 EMC@
8 GND3 GND6 7
GND8 GND7 MUX_USB3_TX0_N 1 2
FOX_UT11123-107B9-7H DT37 AZ5B75-01B.R7G_CSP0603P2Y2
CONN@ 11/21 JUSBC GND7 GND8 is NPTH EMC@
MUX_C_CC1
1
1 2
EMC@
DT35 EMI@
AZ4520-01F.R7G_DFN1610P2E2 SW_TBT_C_USB20_P1_C 1 2
2
DVT2.1_13:USBC3 footprint change and NPTH change from GND5,GND6 to GND7,GND8 EMC@
C
SW_TBT_C_USB20_N1_C 1 2 C
EMC@
CCG5_SBU1 1 2
EMI request
RT125&RT122 near type-C connector EMC@
MUX_USB3_RX1_N_RC 1 2
CCG5_SBU1 RT125 1 2 2M_0201_5% DT42 AZ5B75-01B.R7G_CSP0603P2Y2
EMC@
CCG5_SBU2 RT122 1 2 2M_0201_5%
MUX_USB3_RX1_P_RC 1 2
EMC@
MUX_USB3_RX0_P_RC 1 @ 2 220K_0201_5%
RT355
MUX_USB3_RX0_N_RC 1 @ 2 220K_0201_5%
RT354
MUX_USB3_RX1_N_RC 1 @ 2 220K_0201_5%
RT356
MUX_USB3_RX1_P_RC 1 @ 2 220K_0201_5%
RT360
B B
CNL/CFL Type-C External (Back Panel) Topology with Active Mux

PCH
Pre-Cap Pre-Cap
Via Via
M1 M2 M3 M4 M5 M6 M7
BO
CMC
ESD
TX
BO
M1 M2 M3 M4 M5 M6 M7
Type-C Connector
Act i ve Mux
Crx
Via
Via M4 M5
M1 M2 M3 M6 M7
BO
CMC
ESD
RX
BO
M1 M2 M3 M4 M5 M6 M7
A A
Notes
------------------------------------------------------------------------------------
Crx Cap Value: 297nF to 363nF including tolerance Recommended
------------------------------------------------------------------------------------- Short Protect i on DELL CONFIDENTIAL/PROPRIETARY
Rb Resistor Value: 220kΩ ± 5%

P049-Reserve

5 4 3 2 1
5 4 3 2 1
3V LDO
D D
+3V_LDOP
DT62
RB520SM-30T2R_EMD2-2 UT7
2 1 LDO_IN 1 5 RT60 1BreakDown@
2 0.01_0603_1%
+TBT_VBUS1 VCC VOUT
2
1U_0201_6.3V6M
Use RB520SM Vf=0.51V@200mA, for 5V input GND
CT43 1
DT60 3 4
RB520SM-30T2R_EMD2-2 0.1U_0402_50V7K NC EN
CT44
2 1 1 2
+TBT_VBUS2 RT9069-33GB_SOT23-5 2
RE2364 1 2 0_0201_5%
DT63
2 1 RT543 1 2 300K_0201_5%
+TBT_VBUS3
+3VALW
2
1
RT544
300K_0201_5% @ CT373
1U_0402_25V6K
2
1
ALW _PWRGD_3V_5V RT689 1 2 100K_0201_5%
C C
QT2
S TR AO7401 1P SC70-3
1 3
S
+3V_LDOP
RT545
1M_0201_5%
G
2
1 2
2
CT375
RT546 0.01U_0402_16V7K
10K_0201_5% 1 2
+3V_LDO
QT3
1
S TR AO7401 1P SC70-3
1
D 3 RT62 1BreakDown@
2 0.01_0603_1%
S
+3VALW
RT548
G
2
6
D 100K_0201_1%
B QT4A 2 1 2 B
DMN66D0LDW -7_SOT363-6 G
2
S
1
RT549
0_0201_5%
3 1
D
ALW _PWRGD_3V_5V RT550 1 2 0_0201_5% 5 QT4B
<15,83> ALW _PWRGD_3V_5V G DMN66D0LDW -7_SOT363-6
1 S
0.1U_0402_25V6
4
CT576
A A
P050-Reserve
0.4(X03)
5 4 3 2 1
5 4 3 2 1
D D
USB2.0 Re-driver for TypeC NoTBT port

+3VS
+3VS
0.1U_0201_10V6K
1U_0201_6.3V6M
UT8
12
VCC 2 USB20_P3
1 1 D1P USB20_P3 <16,48,51>
USB20_P3 7 1 USB20_N3
CT300
CT301
<16,48,51> USB20_P3 USB20_N3 D2P D1M USB20_N3 <16,48,51>

<16,48,51> USB20_N3 8
D2M
2 2 6
+3VS 5 EQ 11
RSTN VREG
1
1 4
0.1U_0201_10V6K
3.9K_0201_1%
@ PAD~D T99
3 SCL/CD
RT302
SDA 1
UI8_ENA_HS 9 10
CT355
@
ENA_HS GND
1
0.1U_0201_10V6K
2
C @ RT300 TUSB212IRW BR_X2QFN12_1P6X1P6 2 C
1
CT303
47K_0201_5%
2
UI8_ENA_HS 2
1
@ RT301
47K_0201_5%
2
I(ACTIVE_HS)- High Speed Active Current - (30 mA Max)
B B
A A
P051-Reserve
0.4(X03)
5 4 3 2 1
5 4 3 2 1
M.2 Slot-A Key-A (WLAN + BT) +3VS_WLAN
Close to UWL1 pin4,5 RF Reserved.

+3VS_WLAN
Close to UWL1 pin72,73 RF Reserved.

RW16 1 @ 2 0_0201_5%
0.1U_0201_10V6K
0.01U_0201_16V7
10U_0402_10V6M
15P_0201_50V8J
0.1U_0201_10V6K
0.01U_0201_16V7
10U_0402_10V6M
15P_0201_50V8J
1 1 1 1 1 1 1 1
CW5
CW2
CW3
CW4 RF@
CW80
CW1
CW50
CW6 RF@
RF@
DLM0NSN900HY2D_4P 2 2 2 2 2 2 2 2
4 3 CLK_PCIE_P6_R
<14> CLK_PCIE_P6 4 3
1 2 CLK_PCIE_N6_R
<14> CLK_PCIE_N6 1 2
LN2 +3VS_WLAN
UWL1 @
4
RW17 1 @ 2 0_0201_5% 5 3.3V_1
D 3.3V_2 D
72 29 PCIE_WAKE# <42,58,68,69>
73 3.3V_3 PEWAKE# 30
3.3V_4 CLKREQ# CLKREQ_PCIE#6 <14>
A48 31
3.3V_5 PERST# PCH_PLTRST#_EC <14,27,42,55,66,68,69,79>
A49
3.3V_6
EMC@ 27 SUSCLK_R RW1 1 2 0_0201_5% SUSCLK
DLM0NSN900HY2D_4P SUSCLK(32KHZ)(3.3V) SUSCLK <15>
4 3 USB20_P14_R 1
<16> USB20_P14 4 3 UIM_POWER_SRC/GPIO1
2 14
3 UIM_POWER_SNK SYSCLK/GNSS0 15
1 2 USB20_N14_R UIM_SWP TX_BLANKING/GNSS1
<16> USB20_N14 1 2
LN1 11 7 +3VS_WLAN
12 COEX_TXD RESERVED
13 COEX_RXD
COEX3
6
16 GND_1 17 WLAN_WIGIG60GHZ_DIS#_R RW1201 @ 2 10K_0201_5%
WIFI_UART_RX RW160 1 DAR@ 2 0_0201_5% 18 RESERVED_1 GND_2 20
UART_RXD
WIFI_UART_TX RW161 1 DAR@ 2 0_0201_5% 19 RESERVED_2 GND_3 23 BT_RADIO_DIS#_R RW1211 @ 2 10K_0201_5%
UART_TXD
66 RESERVED_3 GND_4 26
WAKE_BT RW162 1 DAR@ 2 0_0201_5% 67 RESERVED_4 GND_5 32 UART_WAKE_HOST RH265 1 DAR@ 2 100K_0201_5%
<17> WAKE_BT RESERVED_5 GND_6
21 35
+1.8VALW 24 RESERVED_7 GND_8 41
RESERVED_9 GND_10 68
GND_11 71 WAKE_BT RW302 1 @ 2 10K_0201_5%
CLK_PCIE_N6_R 33 GND_12 74
10K_0201_5% 2 DAR@ 1 RW303 WLAN_WIGIG60GHZ_DIS#_R CLK_PCIE_P6_R 34 REFCLKN0 GND_13 75
REFCLKP0 GND_14 76
10K_0201_5% 2 DAR@ 1 RW305 BT_RADIO_DIS#_R CW10 1 DAR@ 2 0_0201_5% PCIE_PRX_C_DTX_N7 36 GND_15 77
<16> PCIE_PRX_DTX_N7 PCIE_PRX_C_DTX_P7 PETN0 GND_16
<16> PCIE_PRX_DTX_P7 CW11 1 DAR@ 2 0_0201_5% 37 78
PETP0 GND_17 79
CW7 1DAR@ 2 0.1U_0201_10V6K PCIE_PTX_C_DRX_N7 39 GND_18 80
<16> PCIE_PTX_DRX_N7 PCIE_PTX_C_DRX_P7 PERN0 GND_19
CW8 1DAR@ 2 0.1U_0201_10V6K 40 81
<16> PCIE_PTX_DRX_P7 PERP0 GND_20
GND_21
82 XTAL SEL GPP_J4
83
RW20 1 @ 2 0_0201_5% CLINK_CLK_R 42 GND_22 84
<13> CLINK_CLK CLINK_DATA_R CLINK_CLK GND_23
<13> CLINK_DATA RW21 1 @ 2 0_0201_5% 43 85
RW22 1 @ 2 0_0201_5% CLINK_RST#_R 44 CLINK_DATA GND_24 86
<13> CLINK_RST# CLINK_RESET GND_25 87
GPP_J4/CNV_BRI_DT (Internal 20 K Pull Down)
GND_26 88
45
SDIO_RESET#
GND_27
GND_28
89 0 = 38.4/19.2MHZ (DEFAULT)
C
46 90 C
47 SDIO_WAKE# GND_29 91
48 SDIO_DATA3 GND_30 92 1 = 24MHZ (25 MHZ WHEN XTAL FREQ
49 SDIO_DATA2 GND_31 93 DIVIDER NON ZERO) +1.8VALW
50 SDIO_DATA1 GND_32 94
51 SDIO_DATA0 GND_33 95
Level Shift Circuit (Killer9560 GPIO 1.8V) 52 SDIO_CMD
SDIO_CLK
GND_34
GND_35
96
G1 RW4 1 2 10K_0201_5%
GND_36 G2
UART_WAKE_HOST RW220 UART_WAKE# DIR2.0 GPIO1.8V GND_37 CNV_BRI_PTX_R_DRX
1 DAR@ 2 0_0201_5% 53 G3 RW5 1 @ 2 20K_0201_5%
+1.8VALW <17> UART_WAKE_HOST CNV_BRI_PTX_R_DRX 54 UART WAKE#(3.3V) UART_CTS GND_38 G4
CNV_BRI_PRX_R_DTX_R 55 LPSS_UART_RTS/BRI_DT UART_TX GND_39 G5
CNV_RGI_PTX_R_DRX_R LPSS_UART_RXD/BRI_RSP GND_40
CNV_RGI_PRX_R_DTX
56
LPSS_UART_TXD/RGI_DT UART_RX GND_41
G6
57 G7
UW2 LPSS_UART_CTS/RGI_RSP UART_RTS GND_42 G8
GND_43
5
DIR2.0 GPIO1.8V G9
<15> CNV_RF_RESET#
1 <15> PCM_SYNC RW234 1 DAR@ 2 0_0201_5% CNVi_RF_RESET#_R PCM_SYNC 58
PCM_SYSNC
GND_44 G10 M.2 CNVI MODES GPP_J6
P
B 4 CNV_RF_RESET#_R RW233 1 DAR@ 2 0_0201_5% CLKREQ_CNVi#_R 59 PCM_SYNC/I2S_WS GND_45 G11

O <15> PCM_IN PCM_IN PCM_OUT/I2S_SD_OUT GND_46
75K PD at PCH side 2 <15> PCM_OUT RW232 1 DAR@ 2 0_0201_5% PCM_OUT_R
PCM_OUT 60 PCM_IN G12
A PCM_CLK_R PCM_IN/I2S_SD_IN GND_47
G
<15> PCM_CLK RW231 1 DAR@ 2 0_0201_5% PCM_CLK 61

PCM_CLK/I2S_SCK PCM_OUT GND_48
A07
TC7SZ08FU_SSOP5 A26
PCM_CLK GND_49 GPP_J6/CNV_RGI_DT
3
A31
1 2 WLAN_WIGIG60GHZ_DIS#_R 28 GND_50 A50
<58> WLAN_WIGIG60GHZ_DIS#
63 W_DISABLE1#
W_DISABLE2#
GND_51 0 = INTEGRATED CNVI ENABLE
DN1
DVT2_07 : Change to level shift circuit to make sure GPIO A42 is 1.8V RB751S-40_SOD523-2 A11
Del SCS0000EU00 DE325 65 RESERVED_10 A12 1 = INTEGRATED CNVI DISABLE
SB000017N00 QH2 1 2 BT_RADIO_DIS#_R 64 LED1# RESERVED_11 A13 +1.8VALW
SD043100180 RW13 <58> BT_RADIO_DIS# LED2# RESERVED_12
SD043100280 RW88 A14
SD043100380 RW90 +1.8VALW DN2 RESERVED_13 A16
SD043100380 RW91 RB751S-40_SOD523-2 USB20_N14_R 69 RESERVED_14 A17
Net name "CNV_RF_RST" USB20_P14_R USB_D- RESERVED_15
70 A18 RW6 1 2 20K_0201_5%
UW3 2 @ 1 USB_D+ RESERVED_16 A27
<17> PCH_BT_RADIO_DIS# RESERVED_17 CNV_RGI_PTX_R_DRX
5
RH6903 A28 RW7 1 @ 2 4.7K_0201_5%

1 0_0201_5% 8 RESERVED_18 A29
<15> CLKREQ_CNV#
P
B 4 CLKREQ_CNV#_R DVT1.1_39: add RH6903 reserve BT_RADIO_DIS# contact to PCH control 9 ALERT# RESERVED_19 A30
2 O 10 I2C_CLK RESERVED_20 A46
75K PD at PCH side A I2C_DATA RESERVED_21
G
A47
TC7SZ08FU_SSOP5 RESERVED_22
CNV_RF_RESET#_R 2 0_0201_5% CNVi_RF_RESET#_R
3
RW2291 CNV@ A42

RF_RESET_B A08
CNVi
GPIO1.8V
CLKREQ_CNV#_R RW2301 CNV@ 2 0_0201_5% CLKREQ_CNVi#_R A43 A4WP_IRQ# A09
CLKIN_XTAL RW10 1 @ 2 0_0201_5% CLKIN_XTAL_R A44 CLKREQ0 A4WP_CLK A10
<14> CLKIN_XTAL REFCLK0 A4WP_DATA A15
LNA_EN A25 SUSCLK_R
DVT2_08:Add SA0000BJI00 UW2,UW3 to do level shift circuit CLKIN_XTAL for Jefferson Peak reserved C_P32K
B
A45 B
NC
A19 CLK_CNV_PTX_DRX_P <13>
WT_CLKP A20
WT_CLKN CLK_CNV_PTX_DRX_N <13>
A21 CNV_PTX_DRX_P0 <13>
WT_D0P A22
CLKIN_XTAL WT_D0N CNV_PTX_DRX_N0 <13>
A23 CNV_PTX_DRX_P1 <13>
WT_D1P A24
WT_D1N CNV_PTX_DRX_N1 <13>
2
RW11 A32 CLK_CNV_PRX_DTX_P <13>

10K_0201_5% @ WGR_CLKP A33
WGR_CLKN CLK_CNV_PRX_DTX_N <13>
A34 CNV_PRX_DTX_P0 <13>
WGR_D0P A35
CNV_BRI_PRX_R_DTX CNV_BRI_PRX_R_DTX_R WGR_D0N CNV_PRX_DTX_N0 <13>
1
RW14 1 2 0_0201_5% A36 CNV_PRX_DTX_P1 <13>

WGR_D1P A37
CNV_RGI_PTX_R_DRX CNV_RGI_PTX_R_DRX_R WGR_D1N CNV_PRX_DTX_N1 <13>
RW15 1 2 0_0201_5%
A38 CNV_BRI_PTX_R_DRX
BRI_DT CNV_BRI_PRX_R_DTX CNV_BRI_PTX_R_DRX <13>
GPIO1.8V A39 RW2 1 @ 2 22_0201_1% CNV_BRI_PRX_DTX <13>
BRI_RSP A40 CNV_RGI_PTX_R_DRX
CNVi&Darwin2.0 BOM opt i on

RGI_DT CNV_RGI_PRX_R_DTX CNV_RGI_PTX_R_DRX <13>
A41 RW3 1 @ 2 22_0201_1% CNV_RGI_PRX_DTX <13>
RGI_RSP
9560.D2WGE2_152P
+3VS_WLAN +1.8VS_AUDIO
1
CNVi&Darwin2.0 BOM opt i on

1
DAR@ RW153 RW150 DAR@

2
2.2K_0201_5%
3.3V 2.2K_0201_5%
G1
1.8V
2
6 1 WIFI_UART_RX
<40> WIFI_UART_RX_R
2
D1
S1
QW12A DAR@ RE71 RE72 RW2 RW3 RW123 RW124

+3VS_WLAN +1.8VS_AUDIO
100K_0201_5% 100K_0201_5% 22_0201_1% 22_0201_1% 22_0201_1% 22_0201_1%

1
DAR@ RW151 CNV@ CNV@ CNV@ CNV@ CNV@ CNV@

A
3.3V 2.2K_0201_5% RW154 DAR@ A
2.2K_0201_5% RE71 RE72 RW2 RW3 RW123 RW124
5
G2
1.8V
2
RW1521 DAR@ 2 0_0201_5% 3 4 WIFI_UART_TX

<40> WIFI_UART_TX_R
D2
S2
1K_0201_5% 1K_0201_5% 0_0201_5% 0_0201_5% 0_0201_5% 0_0201_5%

QW12B DAR@ DAR@ DAR@ DAR@ DAR@ DAR@ DAR@
Vinafix.com
P052-NGFF-WLAN/BT
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P053-Reserve
0.4(X03)
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P054-Reserve
0.4(X03)
5 4 3 2 1
5 4 3 2 1
Audio Jack + CardReader(RT35243)
I-PEX_20698-042E-01 Connector
Signal Pin -->300mA
D
Power Pin -->2A D
JIO1
1 2
3 1 2 4
5 3 4 6
7 5 6 8
CLK_PCIE_P4_R 9 7 8 10
CLK_PCIE_N4_R 11 9 10 12
13 11 12 14
15 13 14 16
<70> PCIE_PRX_C_DTX_P6 15 16 PCIE_PTX_C_DRX_P6 <70>
<70> PCIE_PRX_C_DTX_N6 17 18 PCIE_PTX_C_DRX_N6 <70>
19 17 18 20
21 19 20 22
<14> CLKREQ_PCIE#4 21 22
23 24 PCH_PLTRST#_EC <14,27,42,52,66,68,69,79>
25 23 24 26
<58> REM_DIODE4_P 25 26 MEDIACARD_IRQ# <17>
<58> REM_DIODE4_N 27 28 HP_PLUG# <56>
29 27 28 30
29 30 HOST_SD_W P# <13>
31 32
33 31 32 34
35 33 34 36
AGND 35 36 AGND
<56> HPOUT-L_L 37 38 HPOUT-R_L <56>
39 37 38 40
41 39 40 42
AGND 41 42 AGND
+3VS 43 44 +3VS
45 Power Power 46
C <56> SLEEVE Power Power RING2 <56> C
47 48
49 GND GND 50
51 GND GND 52
GND GND
53
55 GND
GND
GND
GND
54
56 Realtek Audio jack
RR75 1 @ 2 0_0201_5% 57
59 GND
GND
GND
GND
58
60 RING2 1A(40mil)
AGND 61
GND GND
62 AGND SLEEVE 1A(40mil)
RF@ 63 64
DLM0NSN900HY2D_4P PTH PTH
<14> CLK_PCIE_N4 4
4 3
3 CLK_PCIE_N4_R AGND 65
67 PTH
PTH
PTH
PTH
66
68
AGND Realtek codec inner class D(By Clark feedback)
CLK_PCIE_P4_R
RTS5243 2A+2.375mA
1 2 I-PEX_20698-042E-01
<14> CLK_PCIE_P4 1 2 CONN@
LN3
RR76 1 @ 2 0_0201_5%
B B
A A
P055-Reserve
0.4(X03)
5 4 3 2 1
5 4 3 2 1
HPOUT-L RA153 1 2 20_0201_1% RA22 1 2 0_0201_5%

Beep sound HPOUT-L_L <55>
HPOUT-R RA154 1 2 20_0201_1%
HPOUT-R_L <55>
CA78 1
@EMI@
2 0.1U_0201_10VX7SK
TOP Codec AVDD ( Placement near Audio Codec)
Close
RC filter for PWM square to sine-wave
RA8 CA14 LINE2-L CA92 1 2 10U_0402_6.3V6M +AVDD1 ANALOG DIGITAL +5VS_AUDIO

<58> BEEP
1 2 1 2 MONO_IN
1 2 10U_0402_6.3V6M
RA23 1 2 0_0201_5% Audio jack
BOT
LINE2-R CA247
0.1U_0201_10V6K @EMI@ LA1 1 2 HCB2012KF-600T30
1K_0201_5% use X5R for better performance CA79 1 2 0.1U_0201_10VX7SK
1
1
DA11
1 2 2.2K_0201_5%
Close Codec
MIC2-VREFO-L RA7 CA19 AZ5125-01H.R7G_SOD523-2
RA25 1 2 0_0201_5% 10U_0402_10V6M
MIC2-VREFO-R RA152 1 2 2.2K_0201_5% 2 EMI@
D CA80 1
@EMI@
2 0.1U_0201_10VX7SK
Moat D
Place on
AGND
40mil
2
SLEEVE
RA9 SLEEVE <55>
@EMI@
<15,58> SPKR
1 2 RING2
RING2 <55>
CA81 1 2 0.1U_0201_10VX7SK Codec to In order to prevent the built-in LDO damaged from
Audio Jack
1
1K_0201_5% 1 40mil @EMI@ over-voltage on +5VD or Standby power line, we
CA83 1 2 0.1U_0201_10VX7SK
330P_0201_50V7K
330P_0201_50V7K
RA30 CA13
suggested using this Voltage suppressing device.
Path
1 1
CA90
CA246
1K_0201_5% @ 100P_0201_25V7K
Close to UA1 Pin32 2
@ @ @EMI@
CA82 1 2 0.1U_0201_10VX7SK
2
2 2
LINE2-L
Moat
LINE2-R GND AGND
AGND AGND
+AVDD1
Don't short this pad to USB digital ground,
SLEEVE
AGND and should be far away from any power traces.
RING2
MIC2-VREFO-R
210K_0201_5%
10U_0402_10V6M
MIC2-VREFO-L
Place near UA1 pin26/27
HPOUT-L HPOUT-R HPOUT-L
2 HPOUT-R
200 mA 1 1
MONO_IN
330P_0201_50V7K
330P_0201_50V7K
@ @
+AVDD1 1
CA9
CA11
1
CPVEE CA34 1 2 2.2U_0603_25V6K 2 2
AGND
RA64
CA15
Powered by AVDD1
Place next to CODEC
3.3V level change 1.8V UA1
AGND AGND
31
30
29
28
33
27
26
36
35
34
32
25
10U_0402_10V6M
0.1U_0201_10V6K
1 1 Powered by CPVDD/AVDD2
CA17 1 2
CA22
CA23
AGND
MIC2-R/SLEEVE
MIC2-VREFO-L
AUX MODE
MIC_CAP
MIC2-L/RING2
LINE2-L
MIC2-VREFO-R
HP-OUT-L
PCBEEP
CPVEE
LINE2-R
HP-OUT-R
2.2U_0201_10V6K
C 2 2 C
10 mA 1 RA10 2
AGND
37
AVSS1 AGND CBN
24 CBN 1.8V power rail should be supplied by linear regulator,
not switching regulator. if switching regulator is
+1.8VS_AUDIO
100K_0201_5% 38
VREF
DGND CBP
23 CBP CA21 1 2 2.2U_0603_25V6K
unavoidable, Please make sure that switching
frequency operates at out- band(over 20KHz).
10U_0402_6.3V6M
0.1U_0201_10V6K
1
1
CA20 1 2 39 22 +1.8VS_AUDIO
50 mA
CA39
CA33
AGND LDO1_CAP AVSS2 AGND

AGND
40 21 LDO2_CAP CA51 1 2 10U_0402_10V6M
3A
4.7U_0402_10V6M AGND
AVDD1 LDO2_CAP
2
2
+5VS_AUDIO
LA2 1 2 HCB1608KF-121T30_0603
1.5A
+PVDD Powered by PVDD 41
42
PVDD1 ALC3281-CG CPVDD/AVDD2
20
19 LDO3_CAP CA32 1
Near Codec
2 10U_0402_10V6M
Near Codec
0.1U_0201_10V6K
10U_0402_10V6M
<57> SPK_-OUT-L+ SPK-L+ LDO3_CAP
10U_0402_10V6M
0.1U_0201_10V6K
CA53
10U_0402_10V6M
0.1U_0201_10V6K
CA26
CA24
CA29
1 1 1 1 Powered by DVDD-IO 1 1
QFN48(6*6)
43 18
CA102
CA103
<57> SPK_-OUT-L- SPK-L- DVDD_IO +1.8VS_AUDIO

44 17
2 2 2 2 <57> SPK_-OUT-R- SPK-R- SDATA_OUT HDA_SDOUT_AUDIO <15> 2 2
CA39, CA33 close <57> SPK_-OUT-R+
45
SPK-R+ Thermal pad=DGND SDATA_IN
16 HDA_SDIN0_L1
RA17
2
0_0201_5%
HDA_SDIN0_AUDIO <15>
with UA1 Pin3
OE
GPIO0/DMIC-DATA-12
+PVDD 46 15
PVDD2 SYNC HDA_SYNC_AUDIO <15>
1.5A
CA26 close to UA1 pin41
GPIO1/DMIC-CLK
DMIC-DATA-34/I2S
47 14 RA21 1 2 0_0201_5% AGND
JD2 BCLK HDA_BITCLK_AUDIO <15>
GPIO2/SPDIFO
5 mA JACK_PLUG# 48 13 CA37 1 @ 2 22P_0201_25V8
I2S_LRCLK
JD1 DC_DET/EAPD
I2S_DOUT
I2S_MCLK
I2S_SCLK
+1.8VS_AUDIO
I2C_SDA
I2C_SCL
I2S_DIN
49
10U_0402_10V6M
0.1U_0201_10V6K
CA30
1 1 GND
DVDD
10U_0402_6.3V6M
0.1U_0201_10V6K
CA104
PDB
1
CA38
CA36
2 2
2
10
11
12
2
RA6 1 @ 2 2.2K_0201_5%
+1.8VS_AUDIO
CA30 close to UA1 pin46 Powered by DVDD
AMP_I2S_LRCK_R RA61 1 2 33_0201_1%

+1.8VS_AUDIO AMP_I2S_LRCK <57>
0.1U_0201_10V6K
1 AMP_I2S_BCLK_R RA66 1 2 33_0201_1%
10mA
CA54
100K Necessary AMP_I2S_BCLK <57>
CA38,CA36close AMP_I2S_OUT_R RA67 1
RA57 1 2 2 33_0201_1%
with UA1 Pin18 +1.8VS_AUDIO
100K_0201_5% 2 AMP_I2S_OUT <57>
B B
AMP_I2S_IN_R RA60 1 2 0_0201_5%
CODEC_MUTE# AMP_I2S_IN <57>
DMIC_DATA12_R
CA62
CA63
CA66
CA68
33P_0201_50V8J
33P_0201_50V8J
33P_0201_50V8J
33P_0201_50V8J
2 2 2 2
DMIC_CLK12_R
1
@ CA101
1U_0201_6.3V6M 1 1 1 1
JACK DETECTION NETWORK 2
+1.8VS_AUDIO +1.8VS_AUDIO
RA58 1 2 0_0201_5%
<38> DMIC_DAT_CODEC
2
RA62 1 2 22_0201_5%
<38> DMIC_CLK_CODEC AMP_I2C_CLK
RA13
AMP_I2C_DAT AMP_I2C_CLK <57>
100K_0201_1% 1 1 AMP_I2C_DAT <57>
CA57 CA64 @EMI@ AMP_I2C_CLK RA72 1 2 2.2K_0402_5%
1
10P_0201_50V8J 33P_0201_50V8J
EMI@ 2 2 AMP_I2C_DAT RA73 1 2 2.2K_0402_5%
JACK_PLUG#
Near Codec pin5
1
1
RA14 CA40 @
470P_0201_25V7K
470P_0201_25V7K
200K _0201_1% 0.1U_0201_10V6K
2 @ @
1 1
CA249
CA248
2
<55> HP_PLUG#
2 2
(Power Rail) Voltage Current (max)

Internal pull high to +DVDD
PVDD1(+5VS_AUDIO) 5V >1.5A
PVDD2(+5VS_AUDIO) 5V >1.5A
AVDD1(+5VS_AUDIO) 5V 200mA
AVDD2+CPVDD(+1.8VS_AUDIO) 1.8V 50mA
A
0_0201_5% 2 @ 1 RA150
DVDD(+1.8VS_AUDIO) 1.8V/3.3V 10mA A
<58> NB_MUTE#
1 2
DA150
CODEC_MUTE# DVDD-IO(+1.8VS_AUDIO) 1.8V/3.3V 5mA
Realtek codec inner class D 2W/4ohm speaker estimation
RB751S-40 SOD-523
(By Clark feedback)
1
DVT2_15 : @
change DA150 from SC100000S00 to SCS00006300
RA151
1K_0201_5%
2

Size
P056 - Audio ALC3281
Document Number Rev
0.4(X03)
5 4 3 2 1
5 4 3 2 1
+1.8VALW To +1.8VS_AUDIO
+1.8VALW +1.8VALW
UA3
BreakDown@
+1.8VS_AUDIO_R
1 8 RA78 1 2 0.01_0603_1%
+1.8VS_AUDIO
1U_0201_6.3V6M
2 VIN VOUT 7
1 VIN VOUT
3 6 CZ104 1 2
CA121
<58,77,78> RUN_ON_EC
1U_0201_6.3V6M
EN CT @
2 1
+3VALW 4 5 2200P_0402_25V7K
VBIAS GND 9
CA122
GND
2
G5029ARC1D TDFN2X2
DVT1.1_ 29: change UA3 from SA00006U600 to SA0000BMB00
+5VS To +5VS_AUDIO
D D
+5VS +5VS_AUDIO
BreakDown@
RA83 1 2 0.01_0603_1%
SMART AMP TAS2770

TAS2770 moment I =(15.4W/0.85)/12.6V=1.43A(Single)
B+_AMP Continuous power I=(2W/0.85)/12.6V = 0.17A
+1.8VS_AUDIO=12.6mA
B+ B+_AMP
RAP5 1BreakDown@2 0.01_0603_1%
AMP_SDIN
RAP1 1 2 0_0201_5%
<56> AMP_I2S_OUT AMP_SDOUT
C RAP2 1 2 33_0201_1% C
<56> AMP_I2S_IN AMP_SBCLK
RAP3 1 2 0_0201_5%
<56> AMP_I2S_BCLK AMP_FSYNC
RAP4 1 2 0_0201_5%
<56> AMP_I2S_LRCK
+1.8VS_AUDIO
TI_AMP_PD#
RAP99 1 2 4.7K_0201_5% X00:TI FB:SD# need pull high 1.8V
B+_AMP B+_AMP
close UAP1 PIN25
+1.8VS_AUDIO close UAP2 PIN25 +1.8VS_AUDIO

DVT1.1_30 : change CAP62 pop and CAP24 un pop for ME interference
1 1
1 CAP10 CAP31 CAP27

10U_0603_25V6M
10U_0603_25V6M
1
1 CAP13 1 CAP1 1 CAP14 1 CAP5
0.1U_0201_25V6K
CAP7
CAP77
22U_0805_25V6M
0.1U_0201_25V6K
1 1 1 1 1 2 2
CAP62 @ CAP21 @ CAP24 CAP22
2.2U_0201_10V6K
0.1U_0201_10V6K
1U_0201_10V6M
0.1U_0201_10V6K
2.2U_0201_10V6K
0.1U_0201_10V6K
1U_0201_10V6M
1U_0201_10V6M
2 2
2 2 2 2 2 2 2 2 2
UAP1
UAP2
9 25
9 25 8 AVDD VBAT
8 AVDD VBAT IOVDD 4 BSTR2+ CAP28 1 2 0.1U_0201_25V6K
IOVDD 4 BSTL1+ CAP11 1 2 0.1U_0201_25V6K close UAP1 PIN9 close UAP1PIN8 BST_P
close UAP2 PIN9 close UAP2 PIN8 BST_P 3 OUTR2+
AMP_PDMCKR2 OUT_P AMP_OUT_R+SPK
3 OUTL1+ TP66 1 TP@ PAD~D 17 5
AMP_PDMCKL1 OUT_P AMP_OUT_L+SPK AMP_PDMDR2 PDMCK VSNS_P
TP67 1 TP@ PAD~D 17 5 TP69 1 TP@ PAD~D 18
AMP_PDMDL1 PDMCK VSNS_P PDMD
TP68 1 TP@ PAD~D 18
PDMD
AMP_OUT_R-SPK
6
AMP_OUT_L-SPK AMP_SDIN VSNS_N
6 11 26 OUTR2-
AMP_SDIN VSNS_N AMP_SDOUT SDIN OUT_N
11 26 OUTL1- 12
AMP_SDOUT SDIN OUT_N AMP_SBCLK SDOUT
12 13
AMP_SBCLK SDOUT AMP_FSYNC SBCLK
13 14 1 BSTR2- CAP26 1 2
AMP_FSYNC SBCLK FSYNC BST_N
14 1 BSTR1- CAP8 1 2 0.1U_0201_25V6K 0.1U_0201_25V6K
FSYNC BST_N
AMP_I2C_CLK
23 7 DREGR2
AMP_I2C_CLK AMP_I2C_DAT SCL DREG
23 7 DREGL1 22 24 AREGR2
<56> AMP_I2C_CLK AMP_I2C_DAT SCL DREG SDA AREG
22 24 AREGL1
<56> AMP_I2C_DAT SDA AREG
TI_AMP_PD# 1 1 1 1
1 CAP3 1 CAP2 1 CAP6 1 CAP9 21 CAP45 CAP25 CAP23 CAP29
TI_AMP_PD# SD
21 +1.8VS_AUDIO RAP40 1 2 4.7K_0201_5% 20 16
RAP39 1 2 4.7K_0201_5% 20 SD 16 IRQ GND 15
0.1U_0201_25V6K
1U_0201_10V6M
0.1U_0201_25V6K
1U_0201_10V6M
1U_0201_10V6M
1U_0201_10V6M
0.1U_0201_25V6K
0.1U_0201_25V6K
+1.8VS_AUDIO IRQ GND GND 2 2 2 2
15 10
GND 10 2 2 2 2 19 GND 2
GND MODE PGND
1
19 2
MODE PGND RAP77
470_0201_1%
TAS2770RJQR_VQFN-HR26_4X3P5
TAS2770RJQR_VQFN-HR26_4X3P5
2
ADDRESS = 0x84
B
ADDRESS = 0x82 B
TI AMP Speaker Conn.
AMP_OUT_L-SPK
OUTL1- LA99 1 2 0_0603_5%
AMP_OUT_L+SPK
OUTL1+ LA98 1 2 0_0603_5%
AMP_OUT_R-SPK
OUTR2- LA97 1 2 0_0603_5%
AMP_OUT_R+SPK
OUTR2+ LA96 1 2 0_0603_5%
AMP_OUT_L+SPK AMP_OUT_R+SPK
AMP_OUT_L-SPK AMP_OUT_R-SPK
470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K
470P_0402_50V7K
1 @ 1 @ 1 @ 1 @
CA44
CA48
CA45
CA97
EMC@ DA111
ESD203-B1-02EL_TSLP-2-20-2
EMC@ DA123
ESD203-B1-02EL_TSLP-2-20-2
EMC@ DA124
ESD203-B1-02EL_TSLP-2-20-2
EMC@
ESD203-B1-02EL_TSLP-2-20-2
1
2 2 2 2
DA125
2
JSPK12
Realtek Codec Speaker Conn.

SPK_OUT_R-SPK
1
SPK_OUT_R+SPK 1
2
SPK_OUT_L-SPK 2
3
SPK_OUT_L+SPK 3
4
AMP_OUT_R-SPK 4
Use 120 ohm bead 5
AMP_OUT_R+SPK 5
(SM01000L300, MURATA BLM15PX121SN1D) 6
AMP_OUT_L-SPK 6
7
AMP_OUT_L+SPK 7
EMC@ LA6 BLM15PX121SN1D_2P 8
SPK_OUT_P_L- SPK_OUT_L-SPK 8
1 2 RA104 1 2 0_0603_5%
<56> SPK_-OUT-L-
EMC@ LA7 BLM15PX121SN1D_2P 9
SPK_OUT_P_L+ SPK_OUT_L+SPK GND
1 2 RA106 1 2 0_0603_5% 10
<56> SPK_-OUT-L+ GND
EMC@ LA8 BLM15PX121SN1D_2P
SPK_OUT_P_R- SPK_OUT_R-SPK
1 2 RA105 1 2 0_0603_5% ACES_50208-00801-003
<56> SPK_-OUT-R-
EMC@ LA9 BLM15PX121SN1D_2P CONN@
SPK_OUT_P_R+ SPK_OUT_R+SPK
1 2 RA107 1 2 0_0603_5%
<56> SPK_-OUT-R+
Follow Centenario SPK_OUT_L+SPK SPK_OUT_R+SPK
A A
680P_0402_50V7K~D
680P_0402_50V7K~D
680P_0402_50V7K~D
680P_0402_50V7K~D
1 1 1 1 SPK_OUT_L-SPK SPK_OUT_R-SPK
CA109
CA110
CA111
CA112
2 2 2 2
EMC@ DA129
ESD203-B1-02EL_TSLP-2-20-2
EMC@ DA128
ESD203-B1-02EL_TSLP-2-20-2
EMC@ DA127
ESD203-B1-02EL_TSLP-2-20-2
EMC@ DA126
ESD203-B1-02EL_TSLP-2-20-2
1
1
2
Vinafix.com
P057-Audio_Jack/SmartAMP/DB Board
0.4(X03)
LA-J191P
5 4 3 2 1
A B C D E F G H
+RTCVCC_R
+3VALW
RE16 2BreakDown@1 0_0402_5%
BAT2_LED#
RE23601 2 100K_0201_5%
0.1U_0201_10V6K
1 BAT1_LED#
RE23581 2 100K_0201_5%
CE17
+3VALW_5105
+3VALW +3VALW_5105 2
CCG5_SMBDAT
RE23561 2 2.2K_0201_5%
CCG5_SMBCLK
RZ1136 1BreakDown@2 0.01_0402_1% TAP_FW_RDY#
RE23571 2 2.2K_0201_5%
BC_DAT_ECE1117 RE493 1 @ 2 10K_0201_5%
1U_0201_6.3V6M
RE392 1 2 100K_0201_5%
10U_0402_6.3V6M
IRCAM_EN SSD_SCP#
1 2 100K_0201_5% RE307 1 2 100K_0201_5%
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
RE324 DVT2_20 : change RE493 to unpop bcs DB no use @
1 1 1 1 1 1
RH5884 1 2 1M_0201_5%
CE22
CE24
ALWON
CE23
CE25
CE26
CE27
+RTC_CELL_VBAT
DVT2.1_09:RE33 change from SD043100480 to SD043100380 for Align EE schematic resistor value FPR_DET#
LCD_TST FPR_SCAN# RE284 1 2 10K_0201_5%
RE32 1 2 100K_0201_5% 2 2 2 2 2 2 RE283 1 2 10K_0201_5%
SYS_PWROK UE3 DAR_INT#
RE33 1 2 100K_0201_5% RE385 1 2 10K_0201_5%
PCIE_WAKE#_R
CE123 1 @ 2 4.7U_0201_6.3V6M ALWON D3 CPU_RC_ID <59> RE19 1 2 10K_0201_5%
+RTC_CELL_VBAT GPIO033/RC_ID0 PSEN_INT#
F5 K14 GPU_ID <59> RE900 1 2 2.2K_0201_5%
+3VALW_5105 +3VALW_5105_VTR_PLL VBAT GPIO034/RC_ID1/SPI0_CLK J12
GPIO036/RC_ID2/SPI0_MISO IMVP_SMBDAT BOARD_ID <59> PBAT_CHARGER_SMBDAT
F9 C4 IMVP_SMBDAT <88> RE22 1 2 10K_0201_5%
VTR_ANALOG GPIO003/SMB00_DATA/SPI0_CS# IMVP_SMBCLK PBAT_CHARGER_SMBCLK
RH5861 2 1 0_0402_5% B3 IMVP_SMBCLK <88> RE23 1 2 10K_0201_5%
J3 GPIO004/SMB00_CLK/SPI0_MOSI THERMTRIP1# RE25 1 2 10K_0201_5%
+3VALW_5105 VREF_ADC CCG5_I2C_INT2#
C1 1 2
0.1U_0201_10V6K
1 +3VALW_5105 RUNPWROK RE94 2.2K_0201_5%
GPIO057/VCC_PWRGD CCG5_I2C_INT1#
D1 E2 EDP_HPD <13,38> CCG5C_SMBDAT RE95 1 2 2.2K_0201_5%
1 VTR_PLL GPIO060/KBRST/48MHZ_OUT C13 1 2 1
CE18
RE293 2.2K_0201_5%
0.1U_0201_10V6K
1 GPIO104/UART0_TX ME_FWP_R HOST_DEBUG_TX <79> CCG5C_SMBCLK
WLAN_WIGIG60GHZ_DIS#
H5 G14 ME_FWP_R <59> GPU_SMBDAT
RE294 1 2 2.2K_0201_5%
RE71 1 @ 2 100K_0201_5% 2 VTR_REG GPIO105/UART0_RX C12 RE295 1 2 5.1K_0402_5%
CE20
BT_RADIO_DIS# GPIO127/A20M/UART0_CTS# CCG5_I2C_INT1# RTCRST_ON_POWER <64> GPU_SMBCLK
RE72 1 @ 2 100K_0201_5% F6 E10 1 2
RE300 1 @ 2 100K_0201_5%
SIO_SLP_SUS#_R
2 J8 VTR1 GPIO225/UART0_RTS# CCG5_I2C_INT1# <44> GGC5 Dual port INT1 IMVP_SMBDAT
RE296
RE856 1 2
5.1K_0402_5%
10K_0201_5%
+3VALW_5105 VTR2 PCIE_WAKE#_R IMVP_SMBCLK
+1.8V_3.3V_ALW_VTR3
VTR3 (+1 .8 V) J6 L10 RE857 1 2 10K_0201_5%
VTR3 GPIO025/TIN0/nEM_INT/UART_CLK P14
GPIO026/TIN1 PTP_DIS# <59>
<15> PCH_DPWROK_EC
P1 N14 MSDATA RE27 1 2 10K_0201_5%
RUN_ON_EC GPIO020 GPIO027/TIN2 TP_PWR_EN CTRL3_R <40> SUS_ON_EC
<57,77,78> RUN_ON_EC SSD_SCP#
A8 L12 TP_PWR_EN <59> TBT_RESET_N_EC
RE30 1 2 100K_0201_5%
M12 GPIO045 GPIO030/TIN3 RZ41 1 2 100K_0201_5%
<68,69> SSD_SCP# BT_RADIO_DIS# GPIO120 VGA_IDENTIFY IMVP_VR_ON
A1 N10 RE112 1 2 0_0201_5% BID_DIS <14,17> RE855 1 2 100K_0201_5%
<52> BT_RADIO_DIS# PBAT_PRES# GPIO166 GPIO017/GPTP-IN5 PCH_RSMRST#_EC_R
POWER SW SIO_SLP_SUS#_R
F10 M10 EDP_FLAG <77> RE999 1 2 10K_0201_5%
RE111 2 @ 1 0_0201_5% M8 GPIO175 GPIO151/ICT4 N11
<15,56> SPKR GPIO230 GPIO152/GPTP-OUT3 3VS_Hinge_FLAG <77>
<39> PANEL_MONITOR K9 DVT2_10 : Change re999 from SD043100380 to SD043100280 follow Olympic sc hematic
I_BATT_R
P7 GPIO231 E11 C3320 1 2 2200P_0402_50V7K
<15> AC_PRESENT GPIO233 GPIO156/LED0 BAT1_LED# BREATH_LED# <79> I_SYS_R
D10 BAT1_LED# <59> Amber C3321 1 2 2200P_0402_50V7K
GPIO157/LED1 BAT2_LED# PECI_EC_R
+RTC_CELL_VBAT <15> SML1_SMBDAT C10 D11 BAT2_LED# <59> White Place near UE3 CE39 1 @ 2 47P_0402_50V8J
E8 GPIO007/SMB03_DATA/PS2_CLK0B GPIO153/LED2 B1
Connect PCH SMB03 <15> SML1_SMBCLK
L14 GPIO010/SMB03_CLK/PS2_DAT0B GPIO226/LED3 LCD_VCC_TEST_EN <77> TP_PWR_EN
RZ32 1 2 100K_0201_5%
<59> BATT_LED#_LV5 GPIO110/PS2_CLK2 DAR_INT#
1
WLAN_WIGIG60GHZ_DIS#
M13 A3 PSEN_INT# DAR_INT# <40>
RE34 HDA_I2S_SEL = Low ; HDA Mode K11 GPIO111/PS2_DAT2 GPIO005/SMB01_DATA/GPTP-OUT4 B4
<52> WLAN_WIGIG60GHZ_DIS# GPIO112/PS2_CLK1A GPIO006/SMB01_CLK/GPTP-OUT7 PSEN_INT# <40>
100K_0201_5% HDA_I2S_SEL = High ; I2S Mode <15,79> SIO_PWRBTN# SLP_WLAN#_GATE_R
M14 L1 VCCDSW_EN <15>
0_0201_5% 2 1 RE305 K10 GPIO113/PS2_DAT1A GPIO012/SMB07_DATA/TOUT3 K7
<77> SLP_WLAN#_GATE LID_CL_SIO# GPIO114/PS2_CLK0A/nEC_SCI GPIO013/SMB07_CLK/TOUT2 PBAT_CHARGER_SMBDAT DGPU_PWROK <15,27,37,96>
M11 N1
CLK_TP_SIO GPIO115/PS2_DAT0A GPIO130/SMB10_DATA/TOUT1 PBAT_CHARGER_SMBCLK PBAT_CHARGER_SMBDAT <81,82> PBAT and Charger SMB10
2
POWER_SW_IN# <59> CLK_TP_SIO DAT_TP_SIO

E9 M1 CCG5_SMBDAT PBAT_CHARGER_SMBCLK <81,82>
2 1 RE36 C9 GPIO154/SMB02_DATA/PS2_CLK1B GPIO131/SMB10_CLK/TOUT0 P13
<66,79> PBTN_SW#
1K_0201_5%
POWER_SW_IN# <58,59> Touch Pad SMB02 <59> DAT_TP_SIO GPIO155/SMB02_CLK/PS2_DAT1B GPIO132/SMB06_DATA P11
CCG5_SMBCLK CCG5_SMBDAT <44,59> CCG5_DP / mcube
GPIO140/SMB06_CLK/ICT5 GPU_SMBDAT CCG5_SMBCLK <44,59>
<79> JTAG_TDI
B6 A5 GPU_SMBDAT <27,66> +RTC_CELL_VBAT
GPIO145/SMB09_DATA/JTAG_TDI GPIO141/SMB05_DATA/SPI1_CLK/UART0_DCD#/TRACEDAT0 GPU_SMBCLK
E7 B5
1 <79> JTAG_TDO
B8 GPIO146/SMB09_CLK/JTAG_TDO GPIO142/SMB05_CLK/SPI1_MOSI/UART0_DSR#/TRACEDAT1 C5
CCG5C_SMBDAT GPU_SMBCLK <27,66> GPU SMB05
1 <79> JTAG_CLK GPIO147/SMB08_DATA/JTAG_CLK GPIO143/SMB04_DATA/SPI1_MISO/UART0_DTR#/TRACEDAT2 CCG5C_SMBCLK CCG5C_SMBDAT <40,48>
@ CE30 C7 C6 BATBTN# RE390 1 2 100K_0201_5%
CE29 2.2U_0201_6.3V6M
<79> JTAG_TMS JTAG_RST#
H9 GPIO150/SMB08_CLK/JTAG_TMS GPIO144/SMB04_CLK/SPI1_CS#/UART0_RI#/TRACEDAT3 CCG5C_SMBCLK <40,48> GGC5_SP / Darwin 2.0
2 JTAG_RST# I_BATT_R LID_POWER_ON#
1U_0201_6.3V6M G5 RE55 1 2 300_0402_5% I_BATT <82> RE23551 2 100K_0201_5%
2 GPIO200/ADC00 I_SYS_R
<64> TACH_FAN1 F1 J5 TBT_RESET_N_EC
RE126 1 2 300_0402_5% P_SYS <82,88> VCI_IN3#
F2 GPIO050/FAN_TACH0/GTACH0 GPIO201/ADC01 G3 RE899 1 2 100K_0201_5%
<64> TACH_FAN2 LCD_TST GPIO051/FAN_TACH1/GTACH1 GPIO202/ADC02 TBT_RESET_N_EC <42>
<38> LCD_TST
K8 J1 PTP_INT# <14,59>
GPIO052/FAN_TACH2/LRESET# GPIO203/ADC03 IR_CAM_EN
<64> PWM_FAN1 N13 K2 CNV_DET#_EC
RE285 1 2 0_0201_5% IRCAM_EN <38>
L11 GPIO053/PWM0/GPWM0 GPIO204/ADC04 K4
<64> PWM_FAN2 GPIO054/PWM1/GPWM1 GPIO205/ADC05 DVT2_07 : Del RE599 no use
<14> SHD_CS0# P5 L3 VBUS3_ECOK <81>
N7 GPIO055/PWM2/SHD_CS#/(RSMRST#) GPIO206/ADC06 L4
<14> SHD_CLK GPIO056/PWM3/SHD_CLK GPIO207/ADC07 TAP_RESET_R# <59>
<38> BIA_PWM_EC
N9 H3 AUX_EN_WOWL <77>
FPR_SCAN# GPIO001/PWM4 GPIO210/ADC08 SUS_ON_EC
<66> FPR_SCAN# P8 G2 SUS_ON_EC <78>
P9 GPIO002/PWM5 GPIO211/ADC09 J2
<38> SOLC GPIO014/PWM6/GPTP-IN6 GPIO212/ADC10 TAP_FW_RDY# BC_INT#_ECE1117 <59>
<38> PANEL_BKEN_EC M9 H2 CCG5_I2C_INT2# TAP_FW_RDY# <59> G3 mode use HW Strap pin control WLAN
D14 GPIO015/PWM7 GPIO213/ADC11 H1 CNV_DET#_EC(GPIO205) : HIGH PCIE WLAN
<56> BEEP FPR_DET#
C11 GPIO035/PWM8/CTOUT1 GPIO214/ADC12 K1 CCG5_I2C_INT2# <48> GGC5 Single port INT2 CNV_DET#_EC(GPIO205) : LOW CNVi WLAN
<66> FPR_DET# GPIO133/PWM9 GPIO215/ADC13 DCIN2_EN <81>
<82> AC_DIS C14 L2 PCH_PCIE_WAKE# <15,58>
H10 GPIO134/PWM10/UART1_RTS# GPIO216/ADC14 K5
<59> BATT_LED#_LV2 MSCLK_R GPIO135/UART1_CTS# GPIO217/ADC15 LAN_WAKE# <15>
<79> MSCLK RE288 1 2 0_0201_5% MSDATA_R J9 +3VALW_5105
RE287 1 2 0_0201_5% H13 GPIO170/TFDP_CLK/UART1_TX M6
<79> MSDATA GPIO171/TFDP_DATA/UART1_RX GPIO222/SER_IRQ DCIN3_EN <81>
+3VALW_5105 P6 SHD_IO0 <14>
E3 GPIO223/SHD_IO0 M7
<56> NB_MUTE# GPIO022/GPTP-IN0 GPIO224/GPTP-IN4/SHD_IO1 SHD_IO1 <14> CNV_DET#_EC
<38> EN_INVPWR
C2 N6 SHD_IO2 <14> RE966 1 DAR@ 2 100K_0201_5%
RESET_IN# GPIO023/GPTP-IN1 GPIO227/SHD_IO2
RE145 1 2 100K_0201_5% IMVP_VR_ON
F3 N5 SHD_IO3 <14>
N12 GPIO024(RESETI#)/GPTP-IN2 GPIO016/GPTP-IN7/SHD_IO3/ICT3 RE967 1 CNV@ 2 100K_0201_5%
<78> IMVP_VR_ON GPIO031/GPTP-OUT1
P10 D5 T4948 PAD~D TP@
<40> CTRL1_R GPIO032/GPTP-OUT0 BGPO0
<59> M_BIST P12 B7 ALWON_R ACAV_IN <82>
GPI0040/GPTP-OUT2 GPIO164/VCI_OVRD_IN E6 RE1234 1 2 0_0201_5% ALWON
VCI_OUT POWER_SW_IN# ALWON <83,100>
<42> RTD3_SELECT H12 A6 POWER_SW_IN# <58,59>
G12 GPIO121/PVT_IO0 GPIO163/VCI_IN0# A7 BATBTN#
<81> AC_DISC# GPIO124/GPTP-OUT6/PVT_CS# GPIO162/VCI_IN1# LID_POWER_ON#
E12 E4
GPIO125/GPTP-OUT5/PVT_CLK GPIO161/VCI_IN2# VCI_IN3#
<27> GPU_PWR_LEVEL E13 E5
+3VLP GPIO126/PVT_IO3 GPIO000/VCI_IN3#
<64> RTCRST_ON F12
G13 GPIO122/BCM0_DAT/PVT_IO1 C8
<59> BATT_LED#_LV1 BC_DAT_ECE1117 GPIO123/BCM0_CLK/PVT_IO2 GPIO165/32KHZ_IN/CTOUT0/TRACECLK BATT_LED#_LV3 <59>
1
<59> BC_DAT_ECE1117
G10
BC_CLK_ECE1117 GPIO046/BCM1_DAT 32KHZ_OUT
RE43 <59> BC_CLK_ECE1117 D12 D2 CE1501 10P_0402_50V8J
@ GPIO047/BCM1_CLK GPIO221/GPTP-IN3/32KHZ_OUT
1K_0201_5%
SYSPWR_PRES
E1 +PECI_VREF
2 D4 GPIO041/SYS_SHDN# H14 0_0201_5% 2 1 RE292 2
SYSPWR_PRES GPIO044/VREF_VTT PECI_EC_R +VCCST
2
TP@ PAD~D T6000 GPIO011 VTR3 (+1 .8 V) K6 K12 RE48 1 2 33_0402_1%

GPIO011/nSMI GPIO042/PECI_DAT/SB-TSI_DAT H_PECI <8,13>
<81> VBUS1_ECOK N8 K13 REM_DIODE1_N RE292/CE34 close to UE3
GPIO021/LPCPD# GPIO043/SB-TSI_CLK BATT_LED#_LV4 <59>
VTR3 (+1 .8 V) M4 B9 1 2 2200P_0201_25V7K
0.1U_0201_10V6K
RE44 CE32 1
<16> ESPI_RESET# GPIO061/LPCPD#/ESPI_RESET# DN1_DP1A REM_DIODE1_P pin J11 (GPIO044/VREF_VTT)
1
VTR3 (+1 .8 V) M5 A9
CE34
100K_0201_5% <16> ESPI_ALERT# PCH_PLTRST#_5105 REM_DIODE2_N
TP@ PAD~D T6001 VTR3 (+1 .8 V) M2 GPIO063/SER_IRQ/ESPI_ALERT# DP1_DN1A B12 CE33 1 2 2200P_0201_25V7K at least 250mils
GPIO064/LRESET# DN2_DP2A REM_DIODE2_P
<16,79> ESPI_CLK_1P8
VTR3 (+1 .8 V) P2 A12
GPIO065/PCI_CLK/ESPI_CLK DP2_DN2A REM_DIODE3_N 2
+3VALW_5105 <16,79> ESPI_CS#_1P8
VTR3 (+1 .8 V) N2 B11 REM_DIODE3_P
CE35 1 2 2200P_0201_25V7K
VTR3 (+1 .8 V) N3 GPIO066/LFRAME#/ESPI_CS# DN3_DP3A A11
<16,79> ESPI_IO0_1P8 GPIO070/LAD0/ESPI_IO0 DP3_DN3A REM_DIODE4_N
2
<16,79> ESPI_IO1_1P8
VTR3 (+1 .8 V) P3 B10 REM_DIODE4_P
CE36 1 2 2200P_0201_25V7K
GPIO071/LAD1/ESPI_IO1 DN4_DP4A
2
<16,79> ESPI_IO2_1P8
VTR3 (+1 .8 V) N4 A10 +VR_CAP +3VALW_5105
RE59 VTR3 (+1 .8 V) P4 GPIO072/LAD2/ESPI_IO2 DP4_DN4A A14
<16,79> ESPI_IO3_1P8 GPIO073/LAD3/ESPI_IO3 VIN VSET_5107
100K_0201_5% VTR3 (+1 .8 V) M3 A13
VTR3 (+1 .8 V) L5 GPIO067/CLKRUN# VSET B14
<77> SSD_SCP_PWR_EN RESET_OUT GPIO100/nEC_SCI VCP I_ADP <82>
2
Place to BOT <15,79> SYS_PWROK 0_0201_5% 2 1 RE303 B2 G9 THERMTRIP2#
GPIO106/PWROK GPIO103/THERMTRIP2#
1
<81> DCIN1_EN
L13 B13 THERMTRIP1#
H_PROCHOT#_EC THERMTRIP1# <27> RE266
GPIO107/nSMI THERMTRIP1# D13 RE96 2 1 100_0201_5%
JTAG_RST# MEC_XTAL1 H_PROCHOT# <8,82,85,88> 100K_0201_5%
A4 GPIO160/PWM11/PROCHOT#
MEC_XTAL2 MEC_XTAL2_R XTAL1
2 1 A2 Pin F13 GPIO074[BSS_STRAP]
VSS_ANALOG
XTAL2
1
0_0201_5% RE51
ESPI_SHARE_BOOT_SELECT
1
C3
VSS_ADC
GPIO062(RESETO#) ESPI_SHARE_BOOT_SELECT (G3) 1=Use the Shared SPI pins for Boot
VR_CAP
J13 F13
1U_0201_6.3V6M
PCH_RSMRST#_EC_R
1
GPIO116 GPIO074[BSS_STRAP] @
2
F14 J14 2 1 RE800

@SHORT PADS~D
JTAG1 @
0_0201_5%
VSS1
VSS2
VSS3
1 <81> VBUS2_ECOK PRIM_PWRG_R PCH_RSMRST#_EC <79>
VSS
RE61 J10 GPIO117 GPIO075(RSMRST#) E14
GPIO240 GPIO076(PRIM_PWRGD) (MAF) 0=Use the eSPI Flash Channel for Boot
2
CE44
@ 100_0201_5% PCH_RSMRST#_EC_R <15>

RE267
F7
G6
G1
H6
J7
K3
F8
2 MEC5107K-D3-LJ-TR_WFBGA176-NH @
100K_0201_5%
1
@
2
1
+VR_CAP
2
PCIE_WAKE# <42,52,68,69> CE40

1U_0201_6.3V6M
+3VALW 2
PCIE_WAKE#_R PCH_PCIE_WAKE#
0_0201_5% 2 1 RE323 0_0201_5% 2 @ 1 RE322 PCH_PCIE_WAKE# <15,58>
1
100K_0201_5%
RE521
PBAT_PRES#
2
+3.3V_BAT_LDO
+3V_PCH +3VALW_5105
1
D
2
G QE24 +3VALW PRIM_PWRGD
1
+3VS
Hinge_Flag(GPIO151)
S L2N7002WT1G_SC-70-3
3
1
RE932 RE66
PG_OK-->RUNPWROK(GPIO057)
RE520 100K_0201_5% 8.2K_0201_5%
1
100K_0201_5%
2
Enable Pin PCH_PRIM_EN
2
DVT2_04:C hange RE520 from SD000020A00(10M) to SD043100380(100k) for RTC battery life RE605 RE2361 RE938
2
100K_0201_5% 100K_0201_5% 10K_0201_5% RT5839 1 2 0_0201_5% 1.8V_PRIM_PWRGD <95>

THERMTRIP2#
PRIM_PWRG_R PRIM_PWRG
2
RE931 1 2 0_0201_5% RT5840 1 2 0_0201_5% +1VALW_PG <84>

EDP_FLAG
1
0_0201_5% 2 1 RV133 +VCCST

BL_PG <38> ALLSYS_PWRGD
<15> RUNPWROK RUNPWROK 1 2 RE959 1 @ 2 0_0201_5% +2.5V_MEM_PG <86>
1
RE957 0_0201_5% SUS_ON_EN C
RE69 1 2 2.2K_0201_5% 2
ENABLE_DS#
0.1U_0201_10V6K
1
B
1 2 0_0201_5%
CE52
RE958 @ +1.2V_PG <85>
E
3
3VS_Hinge_FLAG SUS_ON_EN QE10
2
0_0201_5% 2 1 R5870 MMBT3904WH_SOT323-3
Deep Sleep suppot 0 B+_CAM_PG <38>
@
3 3
2 1 DE127 +0.95VS_PG <87> <8,13> H_THERMTRIP#_R
RUN_ON_P
non Deep Sleep 1 RB520SM-30T2R_EMD2-2
0602 review D net name THSEL_STRAP
32 KHz Clock +1.8VALW +1.8V_3.3V_ALW_VTR3
YE1 1: Channel 1 will provide Thermistor Readings

REM_DIODE1_P
MEC_XTAL1
1 2
MEC_XTAL2
2BreakDown@1 0_0402_5%
0: Channel 1 will provide Diode Readings
RZ1148
1 2 QE7
0.1U_0201_10V6K
100P_0402_50V8J
1
MMBT3904WH_SOT323-3
100P_0402_50V8J
E
C
1 1 1
2
2 2
C3319
@ CE45
32.768KHZ_9PF_9H03200033
B
@ CE69
CE42 CE43 B
1
12P_0201_50V8J MMBT3904WH_SOT323-3
C
10P_0201_50V8J E
3
2 2 2 QE5 REM_DIODE1_N VSET_5107
0.1U_0402_25V6
Place QE7 For FAN1 Place QE5 For OTP
1
1
PLTRST# is virtual wire REM_DIODE2_P
RE58
CE41
1.69K_0402_1%
QE15
2
100P_0402_50V8J
2
1
1
MMBT3904WH_SOT323-3
@ CE46
100P_0402_50V8J
E
C
1
2 2
@ CE68
B
B
2
MMBT3904WH_SOT323-3
C
E
3
QE11 REM_DIODE2_N
Place QE15 close to BOT Place QE11 close to Alpine Rest=1.69K , Tp=97 degree C
+3VLP Skin1 Ridge
S5 LID OPEN POWER ON NB LID
REM_DIODE3_P
1 2 +3VALW
RE411 0.01_0402_1%
+3V_NB_LID_R
QE8 QE12
1
100P_0402_50V8J
LID_CL_SIO#
1
1
1 2 100K_0201_5% MMBT3904WH_SOT323-3 MMBT3904WH_SOT323-3
@ CE49
100P_0402_50V8J
RE479 RE122 C
E
1
2 2
@ CE72
UE9 390K_0402_1%
B
100K_0201_1% SN74LVC1G123DCUR_VSSOP8 B
2
RE478 1 8 +3VS
C
E
A# VCC LID_POWER_ON#
2
3
Setting for Thermal Design
LID_SW_IN# REM_DIODE3_N
2
2 7 LID_CL_TS_FP#
B R/CEXT RE237 1 2 100K_0201_5%
3 6 Place QE8 close to Place QE12 For SSD
CLR# CEXT D
1
4 5 2 Connect to LID IC
JDIMM
REM_DIODE4_P
Thermal diode mapping
GND Q QE23 DE1
G Connect to EC LID_CL_SIO#
2 1
LID_SW_IN# REM_DIODE4_P <55>
100P_0402_50V8J
L2N7002WT1G_SC-70-3
S LID_SW_IN# <63> QE9 5107 Channel Locat i on 5107 Channel Locat i on
3
MMBT3904WH_SOT323-3
@CE50
E
1
10U_0402_10V6M
1
2
DP1A/DN1A FAN1 DP1/DN1 OTP
B
1M_0201_1%
DE10
Connect to FPR
CE109
RE480
LID_CL_TS_FP#
1
2 1
C
<66> LID_CL_TS_FP#
1
2
DVT2.1_17:UE9 change from SA00003WY00 to SA0000AFC00 for ESD HBM improve (>500V)
REM_DIODE4_N
REM_DIODE4_N <55>
DP2A/DN2A Skin1 DP2/DN2 AR
2
Place QE9 close to DP3A/DN3A JDIMM DP3/DN3 SSD

FAN2
+1.8VALW DP4A/DN4A FAN2 DP4/DN4 skin2
4
ADM1032 Channel Locat i on 4
5
UH6 ME_FWP_R
1
P
4 B
<79> ME_FWP Y 2 DP5/DN5 GPU VR
A
G
TC7SH08FU_SSOP5
3

2019/11/30
Compal Secret Data
2027/06/21 Title
P058-EC_MEC 5105
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
Date : Friday, November 22, 2019 Sheet 58 of 100
A B C D E F G H
5 4 3 2 1
Keyboard Controller board +

TAP Sensor +5VALW
JKB2
+5VALW
+3VALW 1 2
3 1 2 4 +3VALW
5 3 4 6
7 5 6 8 +3VS
9 7 8 10
11 9 10 12
13 11 12 14
<58> TP_PWR_EN 13 14 KB_DET# <15>
D 15 16 D
<58> TAP_FW_RDY# BC_CLK_ECE1117 15 16 BC_INT#_ECE1117 <58>
17 18
<58> BC_CLK_ECE1117 BC_DAT_ECE1117 17 18 TAP_RESET_R# <58>
19 20
<58> BC_DAT_ECE1117 19 20
21 22
23 21 22 24 ISH_I2C1_SDA <17,38>
23 24 ISH_I2C1_SCL <17,38>
25 26
<17> ISH_ACC_INT# 27 25 26 28
<58> DAT_TP_SIO 27 28 BAT1_LED# <58>
29 30
<58> CLK_TP_SIO 29 30 BATT_LED#_LV1 <58>
31 32
<17> I2C1_SDA_TP 31 32 BATT_LED#_LV2 <58>
33 34
<17> I2C1_SCK_TP 33 34 BATT_LED#_LV3 <58>
35 36
<14,58> PTP_INT# 35 36 BATT_LED#_LV4 <58>
37 38
<58> BAT2_LED# 37 38 BATT_LED#_LV5 <58>
+3VALW 39 40
39 40 TAP_SMBCLK_R POWER_SW_IN# <58>
41 42
43 41 42 44 TAP_SMBDAT_R
<58> PTP_DIS# 43 44
2
@ QE22A 45
<58> M_BIST 45
G1
1 6 TAP_SMBCLK_R 46 47
<44,58> CCG5_SMBDAT GND1 GND2
S1
D1 HRS_FH35C-45S-0P3SHW(50)
2 @ 1
CONN@
0_0201_5% RE235
+3VALW
BC_DAT_ECE1117
BC_CLK_ECE1117
5
@ QE22B
G2
HRS_FH35C-45S-0P3SHW(50) series withstand current 0.2A
4.7P_0402_50V8C
@
4.7P_0402_50V8C
@
C C
4 3 TAP_SMBDAT_R
<44,58> CCG5_SMBCLK
S2
D2
Latch-up current at Top = 25 0C 200mA
1
2 1 +5VALW=1.2A +3VALW=1A
CE81
CE82
@
0_0201_5% RE2354
2
DVT2_20 :change QE22A,QE22B to unpop bcs DB no use
EC Strap RE336CE3326 CONFIG

RE67 CE51 REV PHASE RE301CE3319 CONFIG
240K 4700p
240K 4700p M00 PRE EVT 240K 4700p 130K 4700p 3PHASE-I5
130K 4700p X00 EVT 130K 4700p UMA 62K 4700p
62K 4700p X00 DVT1 62K 4700p N18P-G0 33K 4700p
33K 4700p X01 DVT1.1 33K 4700p 8.2K 4700p 4PHASE-6+2
B 8.2K 4700p X02 DVT2 8.2K 4700p N19P-Q1 4.3K 4700p B
4.3K 4700p X03 DVT2.1 4.3K 4700p N19P-Q3 MAXQ 2K 4700p

2K 4700p 2K 4700p 1K 4700p 4PHASE-8+2
1K 4700p A00 PVT 1K 4700p
+3VALW_5105
+3VALW_5105
BOARD_ID rise time is measured from 5%~68%. +3VALW_5105
1
RE336
1
1
@ 10K_0402_5%
RE68 RE301
@ 10K_0402_5% @ 10K_0402_5%
2
+3VALW_5105
<58> CPU_RC_ID
2
2
<58> ME_FWP_R <58> GPU_ID 1
2
1 CE3326
2
RE67 4700P_0201_25V6K
@ CE3319 2
8.2K_0402_5%
@ RE70 4700P_0201_25V6K
10K_0402_5% 2
1
<58> BOARD_ID
1
A A
1
CE51
4700P_0201_25V6K
2 DELL CONFIDENTIAL/PROPRIETARY
P059-KBC Board

5 4 3 2 1
Vinafix.com
5 4 3 2 1
D D
C C
B B
A A
P060-Reserve
0.4(X03)
5 4 3 2 1
5 4 3 2 1
1K 1K
SMBUS Address [0x9a]
+3V_PCH +3VS
1K 1K
+3VS JDIMM1
BE26 MEM_SMBCLK PCH_SMBCLK
DMN65D8
BF26 MEM_SMBDATA PCH_SMBDATA DIMMA
DMN65D8
D
499 QH4 JDIMM2 D
DIMMB
+3VS_TS
499
JTS1 JXDP
0 ohm
PCH BC22 I2C0_SCK_TS I2C0_SCK_TS_R
Touch Screen XDP
BF23 I2C0_SDA_TS I2C0_SDA_TS_R
0 ohm
JTP
2.4K
+3VS_TP
2.4K
BE21 I2C1_SCK_TP I2C1_SCK_TP_C
TP
BF21 I2C1_SDA_TP
I2C1_SDA_TP_C
BE27 BF27
1K
SML1_SMBCLK
+3V_PCH Connect PCH SMB03

SML1_SMBDAT 1K
10K PBAT_CHARGER_SMBDAT 21
C C10 E8 PBAT_CHARGER_SMBCLK 22
CHARGER 0x13H Read C
+3VALW_5105
0x12H Write
SMB03 10K
M3 PBAT_CHARGER_SMBDAT 100 ohm PBAT_SMBDAT 6
SMB10 N2 PBAT_CHARGER_SMBCLK 100 ohm
PBAT_SMBCLK 5
BATT 0x16
2.2K
+3VALW_5105
2.2K
P13 CCG5_SMBDAT
0 ohm
SMB06 P11 CCG5_SMBCLK 0 ohm
CGG5_DP Dual CCG5 I2C address:0x40
mcube
2.2K
1.8K
MEC5107
B B
+3VALW_5105 +1.8V_GFX_AON
2.2K
DGPU_PEX_RST# 1.8K
B5 GPU_SMBCLK DMN65D8 EC_SMB_CK2_PX T4
SMB05 A5 GPU_SMBDAT DMN65D8 EC_SMB_DA2_PX T3
GPU 0x9E GPU SMB05
QV21
10k
+3V_THM
10k
+3VS
GPU_SMBCLK DMN65D8 THM_SMBCLK 8
GPU_SMBDAT THM_SMBDAT 7 Thermal Sensor 0x98
2.2K DMN65D8
Thermal Sensor SMB05
QE19
+3VALW_5105
2.2K
C6 CCG5C_SMBCLK Single CCG5 I2C address:0x42

SMB04 C5 CCG5C_SMBDAT
CGG5_SP
4.7K
A
I2C 0x08 A
+3VS_TP Darwin 2.0
4.7K
JTP
E9 CLK_TP_SIO
SMB02 C9 DAT_TP_SIO Touch PAD Touch Pad SMB02
P061-SMBus block diagram
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P062-Reserve
0.4(X03)
5 4 3 2 1
5 4 3 2 1
D D
Power Button and LED

Lid Switch
+3VLP
C C
UE2
APX8132AI-TRG SOT-23 3P
2 3
LID_SW_IN# <58>
GND
VDD VOUT
1 1
1
CE15 CE16
0.1U_0201_10V6K 10P_0201_50V8J
2 2
Touch pad
B B
A A
Fingerprint Reader CONN

P063-BAT LED/TP/SW
C 0.4(X03)
5 4 3 2 1
5 4 3 2 1
PWM FAN
+1.2V_DDR
B+
1.2V DDR dischager
2
R5843
33_0402_1% +3VS +5VS +5VS +3VS
1
R5842
200K_0402_1%
1
RE100
2
10K_0201_5%
Q5B RE81 RE82
2
5 L2N7002DW1T1G_SC88-6 100K_0201_5% 10K_0201_5% JFAN1
1
<58> PWM_FAN1 +5VS_FAN1 1
2
D RE104 1BreakDown@
2 0.01_0603_1% 2 D
2
6
2 1 3
<58> TACH_FAN1 3
4
DE7 RB751S-40_SOD523-2 4
5 4
1 G1
2 CE66 6
<78,86> SUS_ON_EC_P G2
Q5A 0.01U_0402_16V7K
L2N7002DW1T1G_SC88-6 ACES_50224-00401-001
2
CONN@
1 +VCCIO
B+
VCCIO dischager
2
R5872
33_0402_1% +3VS +5VS +5VS +3VS
1
1
R5871
200K_0402_1% 3
1
RE101
2
10K_0201_5%
Q13B RE83 RE84
2
5 L2N7002DW1T1G_SC88-6 100K_0201_5% 10K_0201_5% JFAN2
1
<58> PWM_FAN2 +5VS_FAN2 1
2
RE105 1BreakDown@
2 0.01_0603_1% 2
2
6
2 1 3
<58> TACH_FAN2 3
4
DE8 RB751S-40_SOD523-2 4
5 4
1 G1
<78,87> RUN_ON_P 2 CE67 6
Q13A G2
0.01U_0402_16V7K
L2N7002DW1T1G_SC88-6 ACES_50224-00401-001
2
CONN@
1
C C
RTC Battery With Charge

Function
+3.3V_BAT_LDO B+
+3.3V_BAT_LDO +3.3V_BAT_LDO
Battery switch
1
2
R1239
R1237 100_0201_1%
100K_0402_5%~D
+3.3V_BAT_LDO +3VLP
2 2
2
R1238
2.2K_0201_5%
2.2K_0201_5%
1
2M_0402_5%
RT1234
RT1235
LED5
LBAT54HT1G_SOD323-2
W=20mils W=20mils HT-191UD5_AMBER
1
2
A
RTCD2
RTCD3
3 1
6
D
1
1
QC1A QC1B
L2N7002DW1T1G_SC88-6 L2N7002DW1T1G_SC88-6 2 Q12
From ship mode IC 2 5 G L2N7002WT1G_SC-70-3
S
SW5
3
<81> SYS_PRES# 1
A
4
2
+RTCVCC_R <100> SYS_PRES_SHIP#
3 B
W=20mils C
1 4
5 G1
CH44 G2
1U_0201_6.3V6M SSAJ120100_3P
2 BATT_ON: PIN1,PIN2 connect
To Battery BATT_OFF: PIN2,PIN3 connect
B B
follow Intel Keep old RTC

Default: OD EC drives GPIOs to LOW to turn ON power to VCCRTC.
X9&X8 RTC discharge schematic
<15,79> PCH_RTCRST# RT1133 1 2 0_0402_5% PCH_RTCRST#_R
+RTCVCC +RTCVCC_R
D
1
2 RTCRST_ON
QRTC RTCRST_ON <58>
G
NTK3139PT1G_SOT723-3
S 2N7002KW_SOT323-3
3
2
1 3 QR104
D
RE143
1
1U_0201_6.3V6M
1 100K_0402_5%
R276
G
2
10K_0201_5% D321
C3
RB751S-40_SOD523-2
2 2 1 DVT2.1_03 : Change QH1,QRTC from SB00000T900 to SB00000SS00 for ESD improve
2
D R3
1
QRTC1 2 RTCRST_ON_R 1 2 RTCRST_ON_POWER <58>

2N7002KW_SOT323-3 G
1M_0402_5%~D
0.1U_0201_10V6K
S
3
1
22P_0201_25V8
100K_0201_1%
1
1
R277
C4
C2
2
2
@
A
2

Issued Date 2019/11/30 2027/06/21 Title
Vinafix.com
Deciphered Date
P064-LId/RTC/FAN
0.4(X03)
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P065-Reserve
0.4(X03)
5 4 3 2 1
5 4 3 2 1
Thermal Sensor +3V_THM +3V_THM
Address : 0X98
0.1U_0201_25V6K
1
CE3325
+3VS +3V_THM UE8
RE332 RE333 REM_DIODE5_P 2 1 DIS@
DXP+ VCC 2
2
QE19A 5.1K_0402_5% 5.1K_0402_5%
REM_DIODE5_N 3 6 THM_SENSOR_ALERT#
G1
RE330 1BreakDown@
2 0.01_0603_1% DIS@ DIS@ DIS@
DXN- ALERT#
GPU_SMBDAT
2
6 1 THM_SMBDAT THM_SMBCLK 8 4 THM_SENSOR#
<27,58> GPU_SMBDAT SCLK THERM#
D1
S1
THM_SMBDAT
5
DIS@ 7 5
SDATA GND
G2
QE19B
D From EC PMDXB600UNE_DFN1010B-6
D
GPU_SMBCLK 3 4 THM_SMBCLK G781P8F_MSOP8
+3V_THM <27,58> GPU_SMBCLK
D2
S2
DIS@
RE335 1 @ 2 0_0402_5% REM_DIODE5_P
10K_0402_5% 2 DIS@ 1 RE328 THM_SENSOR# DIS@
RE334 1 @ 2 0_0402_5% 1
1 RE326 THM_SENSOR_ALERT#
1
10K_0402_5% 2 DIS@
Locat i on
C
MMBT3904WH_SOT323-3
QE16 2 CE3324 DIS@
ADM1032 Channel
B 2200P_0402_25V7K
2
DP5/DN5 GPU VR
E
3
REM_DIODE5_N
Place QE16 For GPU VR
Finger Print circuit ST TPM

( Fingerprint Reader )
Current capability: 3.3V 150mA +3V_PCH
PBTN_SW# RE1235 1 2 0_0201_5% PBTN_SW#_R

<58,79> PBTN_SW# 1 2 TPM_PIRQ#
RE86 10K_0201_5% +3V_PCH +3.3V_VPS_TPM
C 1BreakDown@
2 +3.3V_VPS_TPM C
RE129 0.01_0603_1%
+3VALW
+3VS_FP_R R281 +3VS_FP

RE130 2 @ 1 0_0402_5%
RZ1960 1BreakDown@
2 0.01_0603_1% 2 1
+3VALW
0.1U_0201_10V6K
1
2.2U_0402_6.3V6M
C1079
0438.500WR 0.5A 32V UL/CSA 1

C1080
RE1238 1 @ 2 0_0402_5% 2
+3VLP 2
+3.3V_VPS_TPM
U32
17 22 +3.3V_VPS_TPM
<14,27,42,52,55,68,69,79> PCH_PLTRST#_EC RST# VPS 14
ML17 TPM_PIRQ# 18 NC11
USB20_P10_R <17> TPM_PIRQ# PIRQ#
1 2 1
0.1U_0201_10V6K
10U_0402_6.3V6M
<16> USB20_P10 1 2 PCH_SPI_CLK_TPM_R 19 NC1 1 1
1 2 33_0201_1%
CE11
CE83
RE115
<14,79> CPU_SPI_CLK SCLK 8
4 3 USB20_N10_R RE133 1 2 0_0201_5% PCH_SPI_CS#2_TPM 20 NC5
<16> USB20_N10 4 3 <14> CPU_SPI_0_CS#2 CS# 2 2
3
DLM0NSN900HY2D_4P RE114 1 2 33_0201_1% PCH_SPI_SI_TPM_R 21 NC2 4
EMC@ <14,79> CPU_SPI_D0 MOSI NC3 5
RE113 1 2 33_0201_1% PCH_SPI_SO_TPM_R 24 NC4 10
<14,79> CPU_SPI_D1 MISO NC7 11
RE166 1 2 0_0201_5% TPM_GPIO0 6 NC8 12
B <15,78,79,88> SIO_SLP_S0# 29 GPIO NC9 13 B
7 NC19 NC10 15
R808 2 1 0_0201_5% LID_FPR# +3VS 9 PP NC12 25
<58> LID_CL_TS_FP# NC6 NC15
1 @ 2 16 26
RE125 10K_0201_5% 23 NC13 NC16 27
FPR_GPIO_DET# 32 NC14 NC17 28
FPR_GPIO_SCAN# 2 NC22 NC18 30
JFP 33 GND NC20 31
AZ5B75-01B.R7G_CSP0603P2Y2
+3VS_FP 10 PAD NC21

GND 9
GND
1
8
EMC@ MD3
EMC@ MD4
ST33HTPH2X32AHD4 VQFN 32P TPM

PBTN_SW#_R 7 8
USB20_N10_R 6 7
USB20_P10_R 6 DVT2.1_04 :
5 change U32 from SA0000CYO00 to SA0000CYO10 for upgrade TPM FW
RE255 1 2 0_0402_5% FGND 4 5
LID_FPR# 3 4 +3.3V_VPS_TPM
RE273 1 2 0_0201_5% FPR_GPIO_SCAN# 2 3
<58> FPR_SCAN# FPR_GPIO_DET# 2
RE274 1 2 0_0201_5% 1
<58> FPR_DET# 1
2
PCH_SPI_CLK_TPM_R
TWVM_FPC0510-08RC-TAGHA
2
CONN@
33_0201_5%
RE168 @EMI@ C135 @EMI@
1 1
12P_0201_50V8J
CE96 RF@
68P_0201_50V8J
CE97 RF@
1
PBTN_SW#_R
USB20_P10_R 2 2
LID_FPR#
22P_0201_25V8
USB20_N10_R 2
A 1 A
1
1
EMC@ DI13
EMC@ DI17
D329
D324
EMC@
EMC@

2

2
P066-TPM/FP/THM Senso
Close to JFP AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number
Custom LA-J191P
R ev
0.4(X03)
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P067-HDD / FFS
C LA-J191P 0.4(X03)

5 4 3 2 1
5 4 3 2 1
M.2 Slot-C Key-M (SSD)
D D
+3.3VDX_SSD2
RF Reserved.
DVT2.1_15:Name change from JNGFF2 to JNGFF1
JNGFF1
1 2
4.7U_0201_6.3V6M
0.1U_0201_10V6K
0.01U_0201_10V6K
1 2 1 1 1 1 EMC@ 1 EMC@
3 4
CD36
CD38
CD39
47P_0201_50V8J
CD40
15P_0201_50V8J
CD41
5 3 4 6
<13> PCIE_PRX_DTX_N09 5 6 SSD_SCP#_R_1
7 8 RD101 1 2 0_0201_5%
<13> PCIE_PRX_DTX_P09 7 8 SSD_SCP# <58,69> 2 2 2 2 2
9 10
CD43 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N09 11 9 10 12
<13> PCIE_PTX_DRX_N09 PCIE_PTX_C_DRX_P09 11 12
CD44 1 2 0.22U_0201_6.3V6K 13 14
<13> PCIE_PTX_DRX_P09 13 14
15 16
17 15 16 18
<13> PCIE_PRX_DTX_N10 17 18
<13> PCIE_PRX_DTX_P10 19 20
21 19 20 22
PCIe SSD CD45 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N10 23 21 22 24
<13> PCIE_PTX_DRX_P10 CD46 1 2 0.22U_0201_6.3V6K 25 26
27 25 26 28
29 27 28 30
31 32
33 34
CD53 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N11 35 33 34 36 RD7 1 @ 2 10K_0201_5%
<13> PCIE_PTX_DRX_N11 PCIE_PTX_C_DRX_P11 35 36 +3.3VDX_SSD2
CD51 1 2 0.22U_0201_6.3V6K 37 38
<13> PCIE_PTX_DRX_P11 37 38 M2280A_DEVSLP <16>
39 40
41 39 40 42
<13> SATA_PRX_DTX_P1A 41 42
43 44
<13> SATA_PRX_DTX_N1A 43 44
C SATA SSD 1A CD37 1 2 0.22U_0201_6.3V6K SATA_PTX_C_DRX_N1A
45
47 45 46
46
48
C
<13> SATA_PTX_DRX_N1A SATA_PTX_C_DRX_P1A 47 48
<13> SATA_PTX_DRX_P1A CD42 1 2 0.22U_0201_6.3V6K 49 50 PCH_PLTRST#_EC <14,27,42,52,55,66,69,79>
51 49 50 52
51 52 SSD_PCIE_WAKE#_1 CLKREQ_PCIE#3 <14>
53 54 RD59 1 @ 2 0_0201_5%
<14> CLK_PCIE_N3 53 54 PCIE_WAKE# <42,52,58,69>
<14> CLK_PCIE_P3 55 56
57 55 56 58 RD8 1 2 10K_0201_5%
57 58 +3.3VDX_SSD2
59 60
RD10 1 @ 2 10K_0201_5% 61 59 60 62
+3VS 61 62 +3.3VDX_SSD2
63 64
65 63 64 66
67 65 66
67
68 69
GND GND
BELLW_80159-3221
CONN@
<13> M2280_PCIE_SATA#1 RD58 1 2 0_0201_5%
SATA -> GND

PCIe -> OPEN
B B
A A

P068-NGFF-SSD
C LA-J191P 0.4(X03)
5 4 3 2 1
5 4 3 2 1
M.2 Slot-C Key-M (SSD)
D D
+3.3VDX_SSD
RF Reserved.
DVT2.1_15:Name change from JNGFF3 to JNGFF2
JNGFF2
1 2
4.7U_0402_6.3V6M
0.1U_0201_10V6K
0.01U_0201_10V6K
1 2 1 1 1 1 EMC@ 1 EMC@
3 4
CD100
CD93
CD97
47P_0201_50V8J
CD103
15P_0201_50V8J
CD95
5 3 4 6
<13> PCIE_PRX_DTX_N20 5 6 SSD_SCP#_R_2
<13> PCIE_PRX_DTX_P20 7 8 RD13 1 2 0_0201_5%
9 7 8 10 SSD_SCP# <58,68> 2 2 2 2 2
CD92 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N20 11 9 10 12
CD99 1 2 0.22U_0201_6.3V6K 13 14
15 16
17 15 16 18
19 20
PCIe SSD CD96 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N19
21
23 21 22
22
24
CD91 1 2 0.22U_0201_6.3V6K 25 26
27 28
29 27 28 30
33 31 32 34
CD102 1 2 0.22U_0201_6.3V6K PCIE_PTX_C_DRX_N18 35 33 34 36 RD89 1 @ 2 10K_0201_5%
<13> PCIE_PTX_DRX_N18 PCIE_PTX_C_DRX_P18 35 36 +3.3VDX_SSD
C <13> PCIE_PTX_DRX_P18 CD98 1 2 0.22U_0201_6.3V6K 37 38 C
39 37 38 40 M2280B_DEVSLP <16>
41 39 40 42
<13> SATA_PRX_DTX_P4A 41 42
43 44
<13> SATA_PRX_DTX_N4A 43 44
45 46
SATA SSD 4A CD101 1 2 0.22U_0201_6.3V6K SATA_PTX_C_DRX_N4A 47 45 46 48
<13> SATA_PTX_DRX_N4A SATA_PTX_C_DRX_P4A 47 48
CD94 1 2 0.22U_0201_6.3V6K 49 50
<13> SATA_PTX_DRX_P4A 49 50 PCH_PLTRST#_EC <14,27,42,52,55,66,68,79>
51 52 CLKREQ_PCIE#1 <14>
53 51 52 54 SSD_PCIE_WAKE#_2 RD17 1 @ 2 0_0201_5%
<14> CLK_PCIE_N1 53 54 PCIE_WAKE# <42,52,58,68>
55 56
<14> CLK_PCIE_P1 55 56
57 58 RD14 1 2 10K_0201_5% +3.3VDX_SSD
57 58
59 60
RD12 1 @ 2 10K_0201_5% 61 59 60 62
+3VS 61 62 +3.3VDX_SSD
63 64
65 63 64 66
67 65 66
67
68 69
GND GND
BELLW_80159-3221
CONN@
<13> M2280_PCIE_SATA#2 RD11 1 2 0_0201_5%
SATA -> GND

PCIe -> OPEN
B B
A A

P069-Reserve

5 4 3 2 1
5 4 3 2 1
+3.3V_PI3E
Card reader PCIE Redirver

D D
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1 1 1 1 1
10U_0402_6.3VAM
CR10
CR11
CR12
CR13
CR14
2 2 2 2 2
+3VS +3.3V_PI3E
RR51 1 2 0.01_0603_1%
+3.3V_PI3E
10
16
25
1
U300
VDD
VDD
VDD
VDD
0.22U_0201_6.3V6K 1 2 CR15 PCIE_PTX_C_RD_DRX_P6 2 24 PCIE_PTX_RD_DRX_P6 CR19 2 1 0.22U_0201_6.3V6K
<16> PCIE_PTX_DRX_P6 AIP AOP PCIE_PTX_C_DRX_P6 <55>
TX 0.22U_0201_6.3V6K 1 2 CR16 PCIE_PTX_C_RD_DRX_N6 3 23 PCIE_PTX_RD_DRX_N6 CR20 2 1 0.22U_0201_6.3V6K RX
<16> PCIE_PTX_DRX_N6 AIN AON PCIE_PTX_C_DRX_N6 <55>
FGA 27 Connector
PCH FGA 17 PCIE_PRX_RD_DTX_P6 CR21 2 1 0.22U_0201_6.3V6K
BIP PCIE_PRX_C_DTX_P6 <55>
C SWA 29 C
SWA 18 PCIE_PRX_RD_DTX_N6 CR22 2 1 0.22U_0201_6.3V6K TX
BIN PCIE_PRX_C_DTX_N6 <55>
0.22U_0201_6.3V6K 1 2 CR17 PCIE_PRX_C_RD_DTX_P6 9 14 FGB
<16> PCIE_PRX_DTX_P6 BOP FGB
RX 0.22U_0201_6.3V6K 1 2 CR18 PCIE_PRX_C_RD_DTX_N6 8 12 SWB
<16> PCIE_PRX_DTX_N6 BON SWB
EQA0 21
EQA0 5 TEST#
EQA1 26 TEST#
EQA1 11 EN#
EQB0 20 EN#
EQB0 30 MODE
GND
GND
GND
GND
GND
GND
GND
PAD
+3.3V_PI3E EQB1 15 MODE
EQB1
13
19
22
28
31
PI3EQX12902AZLE_TQFN30_2P5X4P5
RR52 1 @ 2 1K_0201_5% EQA0

RR53 1 @ 2 1K_0201_5% EQA1
RR54
RR55
1
1
@
@
2
2
1K_0201_5%
1K_0201_5%
EQB0
EQB1
SA0000BS40T, S IC PI3EQX12902AZLEX TQFN PCIE RE-DRIVE
SA0000BS400, S IC PI3EQX12902AZLEX TQFN PCIE RE-DRIVE
RR56 1 @ 2 1K_0201_5% FGA
RR57 1 @ 2 1K_0201_5% FGB
RR58 1 @ 2 1K_0201_5% SWA

RR59 1 @ 2 1K_0201_5% SWB
RR60
RR61
1
1 @
2 4.7K_0201_5%
2 4.7K_0201_5%
TEST#
EN#
Operation MODE pin.
RR62 1 2 4.7K_0201_5% MODE “ High” – For PCIe application
s
.
“ Low” – For SATA applicatio
n
s
RR63 1 @ 2 1K_0201_5% EQA0
B B
RR64 1 @ 2 1K_0201_5% EQA1
1 2
RR65
RR66 1
@
@ 2
1K_0201_5%
1K_0201_5%
EQB0
EQB1
Test mode Enable pin. With internal 300kΩ pull-up resistor.
"High" – Test mode disabled.
RR67 1 @ 2 1K_0201_5% FGA "Low" – Test mode enabled.
RR68 1 @ 2 1K_0201_5% FGB
Channel Enable pin. With internal 300kΩ pull down resistor.
RR69
RR70
1
1
@
@
2 1K_0201_5%
2 1K_0201_5%
SWA
SWB
“ High” – Channel is in power down mod .
e
“ Low” – Channel is in normal operatio .
n
RR71 1 @ 2 4.7K_0201_5% TEST#
RR72 1 2 4.7K_0201_5% EN#
A A

P070-Card Reader
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P058-EC_MEC 5105
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A

P072-USB3.1 retimer
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
Place close to JUSB1

P073-USB3.1/USB2.0 conn

5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P074-Reserve
0.4(X03)
5 4 3 2 1
5 4 3 2 1
D D
C C
B B
A A
P075-Reserve
0.4(X03)
5 4 3 2 1
5 4 3 2 1
D D
Screw Hole
@ H5 @ H9
@ H1 @ H2 H_2P5 H_2P5 @ H43 @ H40
H_3P9 H_3P9 H_2P5 H_2P5 H_0P9X1P9N H_1P9X2P5N
1
H_3P9 H_3P9 H_0P9X1P9N H_1P9X2P5N
1
1
@ H6 @ H10 @ H14
H_2P5 H_2P5 H_2P5
@ H3 @ H4 H_2P5 H_2P5 H_2P5
1
1
H_3P9 H_3P9
C H_3P9 H_3P9 C
1
@ H11 @ H15 @ H41 @ H42

H_2P5 H_2P5 H_2P0 CLIP_C5P6-PM
H1~H4: 3.9mm H_2P5 H_2P5 H_2P0 CLIP_C5P6-PM
1
CPU x 4
@ H8 @ H16
H_2P5 H_2P5
H_2P5 H_2P5
1
1
@ H18
@ H19
CLIP_C5P5-PM H_3P9 H5,H6,H8,H9,H10,H11,
CLIP_C5P5-PM H_3P9 H14,H15,H16: 2.5mm
1
1
other x 9
DVT2.1_01 :
Change H18 from CLIP_C5P5-PM to H_3P9 FD1 FD2 FD3 FD4
H31~H37 @ FIDUCAL @ FIDUCIAL @ FIDUCAL @ FIDUCIAL
H18~H19: 5.5mm
1
FAN x 2 EMIST_SUL-15A3M_1P EMIST_SUL-15A3M_1P EMIST_SUL-15A3M_1P
Type-C
@ H34 @ H35 @ H37 FD5 FD6
15A3M @ FIDUCAL @ FIDUCAL
1
1
@ H12 @ H17
CLIP_C6P1-PM CLIP_C6P1-PM
CLIP_C6P1-PM CLIP_C6P1-PM
1
EMIST_SUL-15A3M_1P
@ H31
EMIST_SUL-15A3M_1P EMIST_SUL-15A3M_1P
@ H32 @ H33
Non-TBT Type-C
15A3M
1
B B
H12 H17: 6.1mm EMIST_SUL-35A2M_1P-T

NGFF x 2 @ H36
CPU CLIP_Thermal plate
35A2M
1
@ H7 @ H38 @ H39
H_1P2 H_1P2 H_1P2 CLIP1
H_1P2 H_1P2 H_1P2
1
1
WLAN CLIP
1
EMI_Spring
CONN@
DVT2_09:change H7 ,H38,H39 from clip to H_1P2
H17 H38 H39 :1.2mm

eDP&TS x 3
@ H13
H_2P6
H_2P6
1
@ H55
CLIP_C6P5-PM
@ H56
CLIP_C6P5-PM
H13: 2.6mm
CLIP_C6P5-PM CLIP_C6P5-PM TOP side WLAN NGFF
1
@ H99 @ H98
H_2P3X1P7N H_1P7N
A
H55 H56: 6.5mm H_2P3X1P7N H_1P7N A
1
PCH x 2

P076-Screws
5 4 3 2 1
A B C D E
+3VALW
+5VALW to +5VS WLAN Load Switch UN3
+3VS_WLAN_R +3VS_WLAN +3VS_WLAN +3VS_WLAN
C267
+3VALW to +3VS +3VALW 1U_0201_6.3V6M
1 2 1 8 1BreakDown@
2
0.1U_0201_10V6K
RN34 0.01_0603_1% 1
+5VS 2 VIN VOUT 7
VIN VOUT 1
1
100P_0201_50V8J
EMC@ C1031
68P_0402_50V8J
EMC@ C1033
C280
UZ1 1495mA WLAN_PWR_EN 3 6 1 2
1 14 +5VS_BR RZ13 1BreakDown@
2 0.01_0603_1% EN CT @ 2
+5VALW VIN1 VOUT1
2
2 13 4 5 CN22 2
VIN1 VOUT1 VBIAS GND 9 2200P_0402_25V7K
RUN_ON_EC 3 12 +5VS_CT1 CZ4 1 2 470P_0402_50V7K GND
<57,58,78> RUN_ON_EC ON1 CT1
G5029ARC1D TDFN2X2
4 11
+5VALW VBIAS GND
RUN_ON_EC 5 10 +3VS_CT1 CZ6 1 2 470P_0402_50V7K 2041mA +3VS +3VALW
ON2 CT2 +3VALW
6 9 +3VS_BR RZ15 1BreakDown@
2 0.01_0603_1%
1 +3VALW VIN2 VOUT2 1
7 8
VIN2 VOUT2
2
15 RE275
GPAD RH6789
10K_0201_5%
EM5209VF_DFN14_3X2 20K_0201_5%
SLP_WLAN#_GATE
<58> SLP_WLAN#_GATE
1
RZ1141 1 @ 2 0_0201_5%
2
G
DN3
1 3 SIO_SLP_WLAN#_R 2
<15> SIO_SLP_WLAN#
S
1 WLAN_PWR_EN
2N7002KW_SOT323-3 QR105
3
<58> AUX_EN_WOWL
2
BAT54CW_SOT323-3
RN33
RZ43 1 2 100K_0201_5% RUN_ON_EC RZ1149 2 1 100K_0201_5% SIO_SLP_WLAN#_R RZ1142 1 @ 2 0_0201_5% 100K_0201_5%
1
Close UZ1 Close UZ1
+5VALW +3VALW
+3VALW to +3V_PCH +3VALW
UZ4
+3V_PCH
+5VS +3VS CZ18
1U_0201_6.3V6M
2 1 1 8 +3V_PCH_BR RZ18 1BreakDown@
2 0.01_0603_1%
2 VIN VOUT 7
1 1 1 1 VIN VOUT
@ CZ11 @ CZ12
1U_0201_6.3V6M CZ8 1U_0201_6.3V6M CZ9 RZ1133 1 2 0_0402_5% PCH_ALW_ON_R 3 6 +3V_PCH_CT CZ20 1 2 2200P_0402_25V7K
<15,78> PCH_PRIM_EN EN CT
10U_0402_6.3V6M 10U_0402_6.3V6M
2 2 2 2 4 5
+5VALW VBIAS GND +3V_PCH
2 9 2
GND
G5029ARC1D TDFN2X2
1
RZ46 1 2 1M_0201_5% PCH_PRIM_EN CZ19
Touch Screen Load Switch +3VS_TS
2
0.1U_0402_10V7K
1 1
+3VALW +3VS_TS
0.1U_0201_10V6K
4.7U_0402_6.3V6M
CZ3
+3VS_TS_R
CZ29
CZ26
1U_0201_6.3V6M UZ5 100mA*1.5=150mA
2 1 1 6 RZ26 1BreakDown@
2 0.01_0603_1% 2 2
IN OUT
2 5 RZ99 2 1 52.3K_0201_1%
PCH_3.3V_TS_EN 2 1 PCH_3.3V_TS_EN_R
GND SET SSD Load Switch UZ32 +3.3VDX_SSD_R +3.3VDX_SSD +3.3VDX_SSD
3 4
<17> PCH_3.3V_TS_EN EN FLAG 3VS_Hinge_FLAG <58,77>
RZ97 G517AL1TP1U_TSOT23-6 1 8 RZ36 1BreakDown@
2 0.01_0603_1%
0_0201_5% +3VALW VIN VOUT
2
2 7 1
VIN VOUT CZ45
RZ39 SSD_SCP_PWR_EN 3 6 CZ39 1 2 470P_0402_50V7K 0.1U_0201_10V6K
<58> SSD_SCP_PWR_EN EN CT
100K_0201_5%
4 5 2
+5VALW VBIAS GND
1
9
GND JNGFF2(SSD2)
G5029ARC1D TDFN2X2
Ron=70m ohm
Current Limit =25K/52.3K=0.478A
+3.3VDX_SSD2
3
eDP Load Switch 3
UZ33 1
+3.3VDX_SSD_2_R +3.3VDX_SSD2 CZ46
0.1U_0201_10V6K
+EDPVDD 1 8 RZ34 1BreakDown@
2 0.01_0603_1%
+3VALW VIN VOUT 2
2 7
+3VALW +EDPVDD_R +EDPVDD VIN VOUT
CZ2157 700mA*1.5=1050mA 1 1
SSD_SCP_PWR_EN 3
EN CT
6 CZ37 1 2 470P_0402_50V7K JNGFF1(SSD1)
0.1U_0201_10V6K
4.7U_0402_6.3V6M
CZ2
1U_0201_6.3V6M UZ37
1 2 1 6 1BreakDown@
2 0.01_0603_1% 4 5
CZ41
RZ35 +5VALW
IN OUT VBIAS GND 9
2 5 RZ95 1 2 23.7K_0201_1% 2 2 GND
GND SET
ENVDD_R G5029ARC1D TDFN2X2
ENVDD 2 1 3 4
EN FLAG EDP_FLAG <58>
RZ93 G517AL1TP1U_TSOT23-6 RZ1958 1 2 100K_0402_5% SSD_SCP_PWR_EN
0_0201_5%
DV7
BAT54CW-7-F_SOT323-3~D
<58> LCD_VCC_TEST_EN 2 +VCCST Load Switch +VCCST_R +VCCST
1 ENVDD RZ40 1 2 100K_0201_5% +1VALW
3 UZ15
<13> ENVDD_PCH
Ron=70m ohm 1
2 VIN1
Current Limit =25K/23.7K=1.055A VIN2
+5VALW 7 6 RZ66 1BreakDown@
2 0.01_0603_1%
VIN thermal VOUT
1
+3VS_Hinge 3
+3VALW to +3VS_Hinge CZ28
1U_0201_6.3V6M
0.1U_0201_10V6K
+3VALW VBIAS 0.1U_0201_10V6K
1 1
4 5
CZ96
CZ97
DV331 2 1 EMC@ @ ON GND 2
4 4
2 2 TPS22961DNYR_WSON8
+3VS_Hinge_R +3VS_Hinge
AZ5B25-01F_DFN0603P2Y2 1 1 4.4mohm/6A
1
0.1U_0201_10V6K
4.7U_0402_6.3V6M
CZ1
AZ5B25-01F_DFN0603P2Y2
UZ17
1 2 1U_0201_6.3V6M 1 6 1BreakDown@
2 TR=12.5us@Vin=1.05V
CZ5
CZ7 RZ12 0.01_0603_1%

IN OUT
2 2 <78> SUS_ON_EC_ST
2 5 RZ103 1 2 52.3K_0201_1%
GND SET
RUN_ON_EC 2 1 RUN_ON_EC_R 3 4
EN FLAG 3VS_Hinge_FLAG <58,77>
RZ109 G517AL1TP1U_TSOT23-6
Vinafix.com
2
0_0201_5%
Ron=70m ohm
DV332
EMC@
P077-DC/DC SYSTEM
Size Document Number Rev
Current Limit =25K/52.3K=0.478A AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

A B C D E
5 4 3 2 1
+3V_PCH
5
UZ20
1
<57,58,77> RUN_ON_EC
P
B 4 RUN_ON_EC_GATE RZ58 1 2 0_0201_5%
SIO_SLP_S3# Y RUN_ON_P <64,87>
<15,42,79> SIO_SLP_S3# 2
A
1
TC7SH08FU_SSOP5 1
3
RZ50 CZ50
100K_0201_5% @ 0.1U_0402_10V6K
2
2
D D
RZ59 1 @ 2 0_0402_5%
+VCCSTG Load Switch +1VALW
UZ9
1
2 VIN1
VIN2 +VCCSTG
+5VALW 7 6 +VCCSTG_R RZ48 1 2 0_0402_5%
+VCCST VIN thermal VOUT
3
VBIAS
1U_0201_6.3V6M
1
4 5
ON GND
2
+3V_PCH +VCCSTG
CZ88
RE777
@ 2 TPS22961DNYR_WSON8
10K_0402_5%
4.4mohm/6A 1
5
UZ21 CZ47
TR=12.5us@Vin=1.05V
1
1 0.1U_0201_10V6K
<58> IMVP_VR_ON
P
B 4 RZ60 1 2 0_0402_5%
SIO_SLP_S3# SIO_SLP_S3#_R Y VR_ON <78,88,99> VCCSTG_EN VCCSTG_EN_R 2
0_0402_5% 1 2 RZ86 2 RZ1153 1 2 0_0402_5%
A
G
1
TC7SH08FU_SSOP5 1
3
RZ61 1 @ 2 0_0402_5% RZ71 CZ123

<15,66,79,88> SIO_SLP_S0#
100K_0402_5% 0.1U_0402_10V6K
2
2
+1.8VALW
5
C UZ26 C
RUN_ON_P 1
G VCC
B 4 VCCSTG_EN
RZ1953 1 2 0_0201_5% 2 Y
<13,87> CPU_C10_GATE# A
TC7SZ08FU_SSOP5
3
+VCCPLL_OC Load Switch
+1.2V_DDR
UZ16
1 +1.2V_VCCPLL_OC
2 VIN1
+3VALW VIN2
SUS_ON_EC_P <64,86> +1.2V_VCCPLL_OC_R
1 7 6 RZ67 1BreakDown@
2 0.01_0603_1%
CZ599 +5VALW VIN thermal VOUT
@ 0.1U_0402_10V6K 3
VBIAS +1.2V_VCCPLL_OC
5
@ UZ22
1 2 VCCSTG_EN RZ72 1 2 0_0402_5% 4 5
<58> SUS_ON_EC
P
B 4 RZ91 1 2 0_0402_5% ON GND

2 Y SUS_ON_EC_ST <77>
<15,79> SIO_SLP_S4# A 1
G
TPS22961DNYR_WSON8
B B
TC7SH08FU_SSOP5 CZ49
3
0.1U_0402_10V7K
2
1
CZ588
DZ59 1 2 @ 0.1U_0402_10V6K
RB751S-40_SOD523-2
2
RZ1954 1 2 0_0402_5% RZ1966 1 2 100K_0402_5%
1.2V_DDR_EN <85>
+1.2V_RUN
TDC 0.8A
1
RZ87 1
Peak Current=0.8 A
100K_0402_5% CZ2156
TypeC-SW MUX Load Switch
0.1U_0402_10V6K
OCP=1.3A fix by IC
2
2
+3VALW
UZ36 +1.2VSP +1.2V_RUN
EM1109V-AD_DFN3308-8_3X3
9
GND 1 RZ89 1BreakDown@
2 0.01_0603_1%
8 OUT
IN 2
@RF@ CZ90
1 1
CZ89 7
NC
NC I=800A MAX(393mA*2)
ADJ_1.2V
1
8.2P_0201_25V8D 4.7U_0201_6.3V6M 3 1
6 ADJ/NC
8.2P_0201_25V8D
22U_0402_6.3V6M
@ CZ200
NC 1 1
2 2 4
RF@CZ250
0.01U_0201_10V6K
RZ199
EN_1.2RUN 5 GND
CZ199
5.1K_0402_1%
EN 2
2
+3VALW RZ88 1 2 0_0201_5% 2 2
<15,77> PCH_PRIM_EN
1
1
@ CZ198
1
@ RZ198 0.1U_0201_10V6K
1M_0201_5% Vout = 0.8*(1+5.1K/10.2K)
2 RZ200
=1.2V
2
10.2K_0402_1%
5
A UE7 A
2
Vcc
RZ1955 1 2 0_0402_5% H_VCCST_PWRGD_GATE 2 4 H_VCCST_PWRGD

NC
<78,88,99> VR_ON A Y H_VCCST_PWRGD <8,79>

G
74AUP1G07SE-7_SOT353-5
3

P078-DC/DC/S0iX/CS

5 4 3 2 1
5 4 3 2 1
JXDP
+1VALW JTAG +1VALW
JDEG
RH492 1 2 XDP_PLTRST#
2.2K_0402_5%
1
XDP@
RH474 1 XDP@ 2 1K_0201_5% CFG3 CPU
CH3
+3V_PCH 0.1U_0201_10V6K RH475 1 @ 2 0_0201_5%
2 XDP_TDO
RH540 1 2 0_0201_5%
CPU_XDP_TDO <8> +EC_DEBUG_VCC +3VALW
RH493 1 2 PCH_SYS_PW ROK_XDP RE60
2.2K_0402_5% +1VALW +1VALW 2 1
10K_0804_8P4R_5%
XDP_TDI
JXDP RH541 1 2 0_0201_5%
CPU_XDP_TDI <8> 49.9_0201_1%
8
7
6
5
1 2 +3VALW
+VCCST 3 1 2 4
<8,19> XDP_PREQ# 3 4 CFG17 <8> +EC_DEBUG_VCC
5 6
RP20
<8,19> XDP_PRDY# 5 6 CFG16 <8>
7 8
7 8
1
9 10
10K_0201_5%
10K_0201_5%
10K_0201_5%
100K_0201_5%
@ RE65
<8> CFG0 CFG0 CFG8 <8> CPU_XDP_TMS <8>
2 100_0201_5% PCH_JTAG_TDO 9 10 XDP_TMS
1
2
3
4
1 11 12 RH542 1 2 0_0201_5%
RE63
RE64
RE298
D RH97 @ JDEG1 D
<8> CFG1 11 12 CFG9 <8>
13 14 1
RH98 1 @ 2 51_0201_5%PCH_JTAG_TMS 15 13 14 16 1 2 JTAG_TDI
<8> CFG2 15 16 CFG10 <8> 2 JTAG_TMS JTAG_TDI <58>
CFG3 17 18 3
<8> CFG3 CFG11 <8> JTAG_TMS <58>
2 51_0201_5%PCH_JTAG_TDI 17 18 XDP_TRST# 3 JTAG_CLK
2
RH100 1 @ 19 20 RH543 1 2 0_0201_5% 4
19 20 CPU_XDP_TRST# <8,19> 4 JTAG_TDO JTAG_CLK <58>
21 22 5
<8> XDP_BPM#0 21 22 CFG19 <8> 5 JTAG_TDO <58>
23 24 6 MSCLK
<8> XDP_BPM#1 23 24 CFG18 <8> 6
25 26 7 MSDATA
+VCCSTG 27 25 26 28 7 8 HOST_DEBUG_TX
<8> CFG4 27 28 CFG12 <8> 8 DEBUG_TX
29 30 9
<8> CFG5 29 30 CFG13 <8> 9
31 32 10
33 31 32 34 10
<8> CFG6 CFG14 <8>
RH494 1 2 51_0201_5%CPU_XDP_TMS 35 33 34 36
<8> CFG7 35 36 CFG15 <8>
37 38 11 0_0201_5% 2 @ 1 RE297
XDP_PW RGOOD <17> SBIOS_TX
RH495 1 2 51_0201_5%CPU_XDP_TDI 39 37 38 40 GND1 12
PW RBTN#_XDP 39 40 PCH_XDP_CLK_P <14> GND2 HOST_DEBUG_TX <58>
41 42
PCH_XDP_CLK_N <14>
RH496 1 2 51_0201_5%CPU_XDP_TDO 43 41 42 44
PW R_DEBUG#_XDP 43 44 XDP_PLTRST# MSDATA <58>
45 46 ACES_50521-01041-P01
PCH_SYS_PW ROK_XDP 47 45 46 48 XDP_DBRESET#
CONN@ MSCLK <58>
49 47 48 50
51 49 50 52 XDP_TDO
<15,23,24> PCH_SMBDATA
RH95 1 @ 2 100_0201_5% PCH_JTAG_TCK 53 51 52 54 XDP_TRST#
<15,23,24> PCH_SMBCLK PCH_JTAG_TCK 53 54 XDP_TDI
55 56
1 2 51_0201_5% CPU_XDP_TCK <15> PCH_JTAG_TCK CPU_XDP_TCK 57 55 56 58 XDP_TMS
RH498 DVT1.1_ : change RE60 from 0402 to 0201 and remove RE299 to short
<8> CPU_XDP_TCK 1 2 59 57 58 60 PCH_SPI_IO2_XDP
RH491 0_0402_5% RH573 1 XDP@ 2 1K_0201_5%
CPU_SPI_D2_XDP <14>
1 2 51_0201_5% CPU_XDP_TRST# <15> PCH_JTAGX 61 59 60
PCH
RH497 @
61
62 63
GND GND
JXT_FP270H-061G1AM
CONN@
XDP_TMS PCH_JTAG_TMS
RH12 1 2 0_0201_5%
RH479 1 XDP@ 2 0_0201_5% PCH_JTAG_TMS <15>
<15> PCH_ITP_PMODE
1 2 1K_0201_5% XDP_PLTRST# XDP_TDI PCH_JTAG_TDI
<8,13> PLTRST_CPU# RH480 @ RH477 1 2 0_0201_5%
PCH_JTAG_TDI <15>
1 XDP@ 2 1K_0201_5% XDP_PW RGOOD XDP_TDO PCH_JTAG_TDO

<14> CPU_SPI_D0_XDP RH489 RH478 1 2 0_0201_5%
PCH_JTAG_TDO <15>
1 2 0_0201_5% PCH_SYS_PW ROK_XDP
JAPS
<15,58> SYS_PW ROK RH490 @
.1U_0402_16V7K
1
1 XDP@ 2 1K_0201_5%
CD108
<58> PCH_RSMRST#_EC RH481
C
<8,78> H_VCCST_PW RGD RH482 1 @ 2 1K_0201_5% XDP_PW RGOOD APS CONN C
JAPS
1
+3VS +3V_PCH 1
2
<15,42,78> SIO_SLP_S3# 3 2
+3V_PCH +3VALW 3
4
<15> SIO_SLP_S5# 5 4
<15,78> SIO_SLP_S4# 5
6
<15> SIO_SLP_A# 6
1
+VCCIO 7
+3VALW 7
8
8
1
@ RH5 9
<15,64> PCH_RTCRST# 9
1
RH2 3K_0402_5% 10
RH483 11 10
1K_0201_5% <58,66,79> PBTN_SW # 11
2
150_0402_5% 12
13 12
<15,79> SYS_RESET# 13
2
14
PW RBTN#_XDP XDP_DBRESET# 14
2
RH6 1 2 0_0201_5% RH8 1 2 0_0201_5% 15

PW R_DEBUG#_XDP SIO_PW RBTN# <15,58> SYS_RESET# <15,79> <15,66,78,88> SIO_SLP_S0# 15
RH488 1 XDP@ 2 1K_0201_5% CFG0 16
0.1U_0201_10V6K 17 16
0.1U_0201_10V6K
18 17
1 1 18
19
CH174
CH175
XDP@ XDP@ 20 GND
GND
2 2
CONN@
ACES_50506-01841-P01
JLPDE JSPI FLASH DESCRIPTOR SECURITY OVERRIDE Debug Power Button

Strap Definitions(HDA_SDO /I2S0_TXD) BOT side
B B
JLPDE1
+3VS
GPP_R2/HDA_SDO (Internal 20 K Pull Down)
0 = ENABLE (DEFAULT)
1
1 2
2 3
1 = DISABLE (ME can update)

3 ESPI_IO0_1P8 <16,58>
4
4 ESPI_IO1_1P8 <16,58>
5
5 ESPI_IO2_1P8 <16,58>
6
6 ESPI_IO3_1P8 <16,58>
7
7 PCH_PLTRST#_EC_R PCH_PLTRST#_EC ESPI_CS#_1P8 <16,58>
8 RT1135 1 @ 2 0_0201_5%
8 PCH_PLTRST#_EC <14,27,42,52,55,66,68,69>
9 JSPI1
9 10 ESPI_CLK_5105_JLPDE 1 2 1
RE313 0_0201_5% ESPI_CLK_1P8 <16,58> <14> CPU_SPI_0_CS#1
10 2 1
<14,66> CPU_SPI_D0 2 SW _BOT
DVT1.1_ : fix 0812b design 3 4 2
<14,66> CPU_SPI_D1 3 PBTN_SW # <58,66,79>
11 4
GND1 <14,66> CPU_SPI_CLK 4
12 5
GND2 <14> CPU_SPI_0_CS#0 5
6
<14> CPU_SPI_D2 6 ME_FW P_PCH
7 0_0201_5% 2 1 RH487 1K_0201_5% 2 1 RH454 HDA_SDOUT <15>
<14> CPU_SPI_D3 7 <58> ME_FW P
ACES_50521-01041-P01 8 3 1
9 8
CONN@ +3V_ROM
10 9 T4BJB26BQR_4P
10
11
12 GND1
GND2
Follow Beaver Creek ACES_50521-01041-P01

CONN@
ESPI_CLK_5105_JLPDE
1
+5VALWP
EMC@
RE62
10_0201_5%
1
2
4.7P_0402_50V8C
EMC@ CE48
RE3
300_0402_5%
1
2
Place close pin LED6
G7
2
EMI depop location 1 2

<58> BREATH_LED#
A A
LTW -C193TS5-C_W HITE

P079-XDP/APS/SPI/LPDE...Debug
5 4 3 2 1
Vinafix.com
5 4 3 2 1
CPU_ID CORE_ID
Compal Confidential PCB CPU CML PCH-H GPU for XPS

Samsung 8Gb for N19P Q1/Q3 DDR6
RE301
RH5876 RH5897
ZZZ UH1 QTJ0@ UV18 N18PG62@
UH2
Project Code : For PCH USE
UV23 UV24 R1 130K_0402_5% CPU_ID CORE_ID SYSTEM SKU
File Name : PCB 2FP LA-J191P REV0 M/B 8Core + 65W S IC N18P-G62-A1 QS BGA 960P GPU S
UMA@ 100K_0201_5% 100K_0201_5%
3PHASEI5@ 3PHASEI5@
L L 3PHASE-I5
CL8070104399007 Super Sku CML-H PCH-H RE301 RE301
RE301CE3319 CONFIG RH5875 RH5897
L H NA
UH1 QTJ1@
K4Z80325BC-HC14 FBGA 1.2V K4Z80325BC-HC14 FBGA 1.2V H L 4PHASE-6+2
N19PQVRAMS@ N19PQVRAMS@ 240K 4700p
H H 4PHASE-8+2
UV25 UV26 62K_0402_5% 33K_0402_5% 130K 4700p UMA
N18PG62@ @ 100K_0201_5% 100K_0201_5%
8Core + 45W 62K 4700p N18P-G62 4PHASE62@ 4PHASE62@
CL8070104398806
ES sample ES sample 33K 4700p NA RH5875 RH5896
RE301 RE301
UH1 QTJ2@ K4Z80325BC-HC14 FBGA 1.2V K4Z80325BC-HC14 FBGA 1.2V 8.2K 4700p N19P-Q1
N19PQVRAMS@ N19PQVRAMS@
GPU for Precision 4.3K 4700p N19P-Q3 MAXQ

RV652 RV651 RV653
2K 4700p 100K_0201_5% 100K_0201_5%
UV18 N19PQ1@ 8.2K_0402_5% 4.3K_0402_5% 4PHASE82@ 4PHASE82@
D 6Core + 45W N19PQ1@ N19PQ3Q@ 1K 4700p D
CL8070104398908
100K_0201_5% 100K_0201_5% 100K_0201_5% RE336 RE336

N19PQVRAMS@ N19PQVRAMS@ N19PQVRAMS@ RE336CE3326 CONFIG
S IC N19P-Q1-A1 FCBGA 960P GPU A31 RE67 CE51 REV PHASE
240K 4700p
UV18 N19PQ3Q@ RE67
240K 4700p M00 PRE EVT 130K_0402_5% 8.2K_0402_5% 130K 4700p 3PHASE-I5
Micron 8Gb for N19P Q1/Q3 DDR6 130K 4700p X00 EVT
3PHASEI5@
RE336
4PHASE62@
62K 4700p
R1 62K 4700p X00 DVT1 33K 4700p
S IC N19P-Q3-A1 FCBGA 960P GPU A31 4.3K_0402_5%
UV23 UV24 33K 4700p X01 DVT1.1 8.2K 4700p 4PHASE-6+2
QS sample 8.2K 4700p X02 DVT2 4.3K 4700p
1K_0402_5%
DVT2_13 :Change RE67 from SD028820180 to SD028430180 for phase change
4.3K 4700p X03 DVT2.1 4PHASE82@ 2K 4700p
MT61K256M32JE-14:A 1.2V MT61K256M32JE-14:A 1.2V 2K 4700p 1K 4700p 4PHASE-8+2
N19PQVRAMM@ N19PQVRAMM@
1K 4700p A00 PVT
UV25 UV26
ES sample
RH505 RH505
TLS CONFIDENTIALITY
WLAN EC MT61K256M32JE-14:A 1.2V MT61K256M32JE-14:A 1.2V

N19PQVRAMM@ N19PQVRAMM@
HIGH(4.7K)
UE3
LOW(DEFAULT)(100K)
UWL1 HarriP@ RV652 RV645 RV653 4.7K_0201_5% 100K_0201_5% BIOS 20k internal pull-down
VPRO@ NVPRO@
QS sample
Harrison Peak
CNVI MEC5107K-D3-LJ-TR_WFBGA176-NH
100K_0201_5% 100K_0201_5% 100K_0201_5%
RH564 RH567 RH5858
S_W/L_MOD INTEL AX201.D2WD W/BT 5107_DIS_ES@ N19PQVRAMM@ N19PQVRAMM@ N19PQVRAMM@

UWL1 Killer@
UE3
100K_0201_5% 100K_0201_5% 100K_0201_5%
UMA@ UMAX@ UMA@
Killer 1650s
CNVI
S_W/L_MOD INTEL KILLER1650S.01 W/BT MEC5107K-D3-LJ-TR_WFBGA176-NH
RH566
5107_Signed@
UWL1 DAR@
DVT2_14 :
Change UE3 from SA0000CQ700 to SA0000CQ740 Sign EC 100K_0201_5%
Change UE3 from SA0000CQ720 to SA0000CQ730 Non sign EC UMAP@
Killer 500SQ
PCIE RH567 RH5858
S_W/L_MOD SAMSUNG WBQ76QOUS01 W/BT S ES sample
C
100K_0201_5% 100K_0201_5% C
N18PG62@ N18PG62@
RH566 RH5858
100K_0201_5% 100K_0201_5%
N19PQ1@ N19PQ1@
RH566 RH5857
100K_0201_5% 100K_0201_5%
N19PQ3Q@ N19PQ3Q@
B B
DRAM Option DRAM Config Option DRAM SDP / DDP Option

MEM_CONFIG0 MEM_CONFIG1 MEM_CONFIG2 MEM_CONFIG3 MEM_CONFIG4 R_COMP X76
SDP
MICRON 8G/2400
SA00009V20L
X7674531L07
SDP
HYNIX 8G/2400
SA0000A1H0L
X7674531L09
SDP
SAMSUNG 8G/2400 X7674531L08
SA00009U40L
DDP
MICRON 16G/2400
SA0000A310L
X7674531L10
DDP
HYNIX 16G/2400
SA0000ARA0L
X7674531L15
A A
DDP
SAMSUNG 16G/2400
SA00009S40L
X7674531L11
2019/11/30
Compal Secret Data
2018/12/31 Title
P080-BOM Option
0.4(X03)
LA-J191P
5 4 3 2 1
5 4 3 2 1
S1
EMC@ PL2500
+TBT_VBUS1 +DC_IN_1
VBUS Power path
HCB2012KF-121T50_2P
1 2
@ PT2500
EMC@ PL2501 PU2507 +CHG_VIN_20V LPS Function
HCB2012KF-121T50_2P
1 2 11
VIN_1
1
+3V_LDOP
2200P_0402_50V7K
2200P_0402_50V7K
Vout_1
0.01U_0402_25V7K
8.2P_0201_50V8B
100P_0201_50V8J
0.1U_0402_25V7K
0.1U_0402_25V7K
10U_0805_25VAK
1000P_0201_25V7K
100P_0201_50V8J
1U_0603_25V7K
1
12
EMC@ PC2501
EMC@ PC2502
EMC@ PC2503
EMC@ PC2504
EMC@ PC2505
EMC@ PC2506
EMC@ PC2507
EMC@ PC2508
EMC@ PC2509
EMC@ PC2574
1M_0201_1%
VIN_2
1
PC2510
PC2560
PR2501
2 10U_0805_25VAK
Vout_2
1
PC2500
2
3 0.01U_0402_50V7K
POVP +3V_LDO
2
4 1 2 PD2501
FLTB PR2539 RB520SM-30T2R_EMD2-2
221K_0402_1%
ENB_1#
5 200K_0402_1% 1 2
1
499K_0402_1%+DC_IN_1
ENB
PR2505
7
SS @ PR2508
6 1 2
NC_1
NC_2
NC_3
GND
EXP
1M_0201_1%
2
1
1
PC2561
+3V_LDO
PR2510
0.01U_0402_50V7K
6
13
10
S1_EXP PU2500
+3V_LDO
2
PR2514 1
2
AOZ1327DI-01_DFN12_3X3 4 0_0402_5% AC1_OVP
1 1 2 1 2 PC1946
100K_0201_1%
3
Need 4*6 mm shape 0.1U_0402_10V7K
10U_0402_6.3V6M
PR2513
100P_0402_50V8J
1
2
2.2U_0402_25V6M
on each layer for Thermal 47K_0402_1%
200K_0402_1%
200K_0402_1%
0.1U_0402_10V7K
1M_0201_1%
1
PR2518
AOZ1327 Low Active
1
PC2515
PR2521
PR2519
@PC2517
1
1
PC2516
PR2520
PC2514
AZV3001FZ47_X2DFN1410-6_1P4X1
2
ENB_1# PR1945
2
0_0201_5%
P
2
2
1 2 2 4
NC
A Y VBUS_C_CTRL_P1 <81,82>
2
D D
PR2529 PQ2511B PR2530
G
<44,81> VBUS_C_CTRL_P1#
1
0_0201_5% 2N7002KDW_SOT363-6 0_0201_1% D PU1902
PD1_LPS#
1 2 4 3 1 2 5 NL17SZ14DFT2G SOT353 PR1946
D
<58> DCIN1_EN
3
G PQ2572B PR2527 1M_0201_1%
1
D
X01.3 change PR2530,PR2570,PR2610 2N7002KDW_SOT363-6 0_0402_5% Inverter
1
from SD041100380 to SD041000080 @ S 2 1 2
100K_0201_1%
VBUS_C_CTRL_P1 <81,82>
2
PR2531 G
1
G
1M_0201_1% PQ2510
100K_0201_1%
PR2534
X01.2 change PR2531,PR2573,PR2611 to NC S 2N7002KW_SOT323-3
1
3
2
PR2535
X03.4 change SB00000ST00 to SB000009Q80
2
PQ2575A +3V_LDO
2
2N7002KDW_SOT363-6
PD2_LPS# <81> PD3_LPS# <81>
+3V_LDO
6
D 1
2
G PR2537 PR2538 PC1947
PR2536
3
AC1_OVP 0_0201_5% D 0_0201_5% D 0.1U_0402_10V7K
1 2 S 1 2 2 1 2 5 2
+3VALW
1
G PQ2513A G PQ2513B
100K_0402_1% 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
1
1
PC2571 S S
4
.1U_0402_16V7K PR1947
0_0201_5%
P
2
1 2 2 4
NC
VBUS_C_CTRL_P1# <44,81> A Y VBUS_C_CTRL_P2 <81,82>
G
1
PU1903
NL17SZ14DFT2G SOT353 PR1948
3
1M_0201_1%
Inverter
2
EMC@ PL2502
+TBT_VBUS2 +DC_IN_2
S2
HCB2012KF-121T50_2P
1 2
@ PT2501
+CHG_VIN_20V +3V_LDOP +3V_LDO
EMC@ PL2503 PU2508
HCB2012KF-121T50_2P
1 2 11
VIN_1
1
1
2200P_0402_50V7K
2200P_0402_50V7K
Vout_1
0.01U_0402_25V7K
8.2P_0201_50V8B
100P_0201_50V8J
100P_0201_50V8J
0.1U_0402_25V7K
0.1U_0402_25V7K
1
PC2518 PC1949
1000P_0201_25V7K
10U_0805_25VAK
1U_0603_25V7K
1
12
EMC@ PC2519
EMC@ PC2520
EMC@ PC2521
EMC@ PC2522
EMC@ PC2523
EMC@ PC2524
EMC@ PC2525
EMC@ PC2526
EMC@ PC2527
EMC@ PC2575
0.01U_0402_50V7K 0.1U_0402_10V7K
1M_0201_1%
VIN_2
1
1
PC2563 2
PR2543
2
2
PC2528
10U_0805_25VAK PD2505
Vout_2
221K_0402_1%
2
2
1
3 1 2
499K_0402_1%+DC_IN_2
POVP +3V_LDO
PR2542
PR1949
4 1 2 0_0201_5%
P
FLTB 1 2 2 4
NC
ENB_2# PR2657 @ PR2547
5 1 2 A Y VBUS_C_CTRL_P3 <81,82>
200K_0402_1%
ENB
G
1M_0201_1%
1
7 PU1904
SS
PR2550
NL17SZ14DFT2G SOT353 PR1950
6
6
3
NC_1
NC_2
NC_3
PU2501 1M_0201_1%
GND
EXP
Inverter
1
PC2564 PR2553
2
0.01U_0402_50V7K 4 0_0402_5% AC2_OVP
13
10
S2_EXP 1 1 2 1 2
+3V_LDO
2
3
10U_0402_6.3V6M
PR2552
100P_0402_50V8J
2.2U_0402_25V6M
47K_0402_1%
200K_0402_1%
200K_0402_1%
0.1U_0402_10V7K
1M_0201_1%
1
AOZ1327DI-01_DFN12_3X3
100K_0201_1%
1
PC2535
PR2560
Need 4*6 mm shape
PR2558
@PC2533
1
1
PC2532
PR2559
PC2534
AZV3001FZ47_X2DFN1410-6_1P4X1
on each layer for Thermal
2
PR2561
2
2
2
AOZ1327 Low Active
2
2
ENB_2#
PR2567
PQ2511A
1
D
PR2569 PR2570 0_0402_5%
6
C 0_0201_5% 2N7002KDW_SOT363-6 0_0201_1% D 2 1 2 C

PD2_LPS# VBUS_C_CTRL_P2 <81,82>
1 2 1 6 1 2 2 G
D
<58> DCIN2_EN
S
G PQ2572A PQ2526
X01.3 change PR2530,PR2570,PR2610 2N7002KDW_SOT363-6 S 2N7002KW_SOT323-3
100K_0201_1%
100K_0201_1%
3
from SD041100380 to SD041000080 S
1
@ X03.4 change SB00000ST00 to SB000009Q80

PR2579
PR2572
G
PR2573
2
1M_0201_1%
X01.2 change PR2531,PR2573,PR2611 to NC
PD1_LPS# <81> PD3_LPS# <81>

2
PQ2575B
3
2N7002KDW_SOT363-6 D
+3V_LDO 5 PR2577 PR2578
3
PR2540 G AC2_OVP 0_0201_5% D 0_0201_5% D
0_0402_5% 1 2 2 1 2 5
1 2 S G PQ2529A G PQ2529B
+3VALW
4
2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
S S
4
@
1
PC2572 VBUS_C_CTRL_P2# <44,81>

.1U_0402_16V7K
2
EMC@ PL2504 +DC_IN_3

+TBT_VBUS3
S3
HCB2012KF-121T50_2P
1 2 +CHG_VIN_20V
@
PT2502
EMC@ PL2505 PU2509 +3V_LDOP
HCB2012KF-121T50_2P
1 2 11
VIN_1
1
2200P_0402_50V7K
2200P_0402_50V7K
Vout_1
0.01U_0402_25V7K
8.2P_0201_50V8B
100P_0201_50V8J
100P_0201_50V8J
0.1U_0402_25V7K
0.1U_0402_25V7K
1000P_0201_25V7K
10U_0805_25VAK
1U_0603_25V7K
1
12
EMC@ PC2541
EMC@ PC2537
EMC@ PC2542
EMC@ PC2543
EMC@ PC2538
EMC@ PC2544
EMC@ PC2545
EMC@ PC2539
EMC@ PC2546
EMC@ PC2576
PC2536
1M_0201_1%
VIN_2
1
PC2565 0.01U_0402_50V7K
PR2583
2
PC2540
10U_0805_25VAK
Vout_2
2
2
PD2509
+3V_LDO
2
3 RB520SM-30T2R_EMD2-2
POVP
221K_0402_1%
2
1 2
499K_0402_1%+DC_IN_3
1
4 1 2
FLTB
PR2584
ENB_3# PR2659
5 200K_0402_1% @ PR2588
ENB 1 2
7 1M_0201_1%
SS
2
6
PR2590
NC_1
NC_2
NC_3
GND
EXP
6
PU2502
1
PC2566
0.01U_0402_50V7K PR2593
2
13
10
S3_EXP 4 0_0402_5% AC3_OVP

2
1 1 2 1 2
+3V_LDO 3
10U_0402_6.3V6M
PR2592
100P_0402_50V8J
2.2U_0402_25V6M
AOZ1327DI-01_DFN12_3X3 47K_0402_1%
200K_0402_1%
200K_0402_1%
0.1U_0402_10V7K
1M_0201_1%
1
1
1
PC2553
PR2599
Need 4*6 mm shape
PR2597
@PC2551
100K_0201_1%
1
PC2550
PR2598
PC2552
AZV3001FZ47_X2DFN1410-6_1P4X1
on each layer for Thermal
1
2
PR2602
2
AOZ1327 Low Active
2
2
ENB_3#
PR2607
6
0_0402_5% D
PR2609 PQ2576A PR2610 <81,82> VBUS_C_CTRL_P3 2 1 2 PQ2574A
3
0_0201_5% 2N7002KDW_SOT363-6 0_0201_1% D G 2N7002KDW_SOT363-6

PD3_LPS#
1 2 1 6 1 2 5
D
<58> DCIN3_EN
S
G PQ2574B S
1
1
X01.3 change PR2530,PR2570,PR2610 2N7002KDW_SOT363-6
100K_0201_1%
B from SD041100380 to SD041000080 S B

1
@
100K_0201_1%
PR2613
G
A00 PR2611
1
PQ2576B 1M_0201_1% X01.2 change PR2531,PR2573,PR2611 to NC

2
PR2614
2N7002KDW_SOT363-6
PD1_LPS# <81> PD2_LPS# <81>
2
D
PR3013 5 PR2615
2
6
0_0402_5% G AC3_OVP 0_0201_5% D PR2618
3
1 2 +3V_LDO 1 2 2 0_0201_5% D
+3VALW S G PQ2546A 1 2 5
4
2N7002KDW_SOT363-6 G PQ2546B
@ S 2N7002KDW_SOT363-6
1
1
PC2573 S
4
.1U_0402_16V7K
VBUS_C_CTRL_P3# <48,81>
2
+3VALW
AC Disconnect Logic
200K _0201_1%
+3VALW
Battery connector
1
PR2620
200K _0201_1%
1
PR2621 PR2623 From Charger

2
PR2622
0_0201_5% 0_0201_5%
1 2 1 2 AC_DISC_OUT# <82> EMC@ PL2506
<58> AC_DISC#
HCB2012KF-121T50_2P
1 2
2
PR2624 PR2625
+VBATT BATT++
6
To EC, Vbus power path AC_DIS#

1
0_0201_5%
2 2
D
1
75_0201_1%
2
EMC@ PL2507
CHG_PROCHOT# <82> HCB2012KF-121T50_2P
1
G 1 2
1
PR2626 To Charger EMC@ PL2508 EMC@ EMC@

@ PC2555 PQ2570A S 0_0201_5% X01.4 change PR2625 from SD000012AZ0 to SD00000LP00 HCB2012KF-121T50_2P PD2502 PD2503
1
1000P_0402_25V8J 2N7002KDW_SOT363-6 Note: AC_DISC_OUT# 1 2 TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3

2
1
When AC plug In , Change to High(floating)
2
0.01UF_0402_25V7K
100P_0402_50V8J
100P_0402_50V8J
1000P_0402_50V7K
When AC plug Out , Change to Low for reset Prochot#
1
1
PC2567
PC2568
EMC@ PC2569
PC2570
PR2630
Battery
3
D 0_0201_5% D
2
2
5 1 2 2
(3S2P) 86W
3
G G PQ2571A
EMC@
EMC@
EMC@
2N7002KDW_SOT363-6
S PQ2570B S (3S1P) 56W
4
2N7002KDW_SOT363-6
JIMBTY battery connector

SMART Battery: PBAT_CHARGER_SMBCLK <58,82>
01.B A T + BAT100
02.B A T + DEREN_40-42507-01001RHF_10P PBAT_CHARGER_SMBDAT <58,82>
03.B A T + 1
1
2
04.B A T + 2 3
05. CLK_ SMB 3 4 1 2 +3.3V_BAT_LDO
06. DA T _ SMB 4
5
5 PR2670 1 2 100_0402_5%
07.+3 . 3 V_ B A T _ LDO 6
6
7
PR2671 100_0402_5%
PR2640 PR2641 PR2639

08.SY S_ P R ES# 7 8
0_0201_5% AC_DIS# 0_0201_5% AC_DIS# 0_0201_5% AC_DIS#
09 . G N D 8 9
1 2 1 2 1 2 10 . G N D 9
10
10
SYS_PRES# <64>
A
11 . G N D GND_1
11
12
A
PR2645 PR2646 PR2644

12 . G N D GND_2 13
13 . G N D GND_3
6
0_0402_5% D 0_0402_5% D 0_0402_5% D 14

<58> VBUS1_ECOK
1 2 2
<58> VBUS2_ECOK
1 2 2
<58> VBUS3_ECOK
1 2 2 14 . G N D GND_4
G PQ2568A G PQ2569A G PQ2567A
2N7002KDW_SOT363-6 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
S S S
+3VALW +3VALW +3VALW
1
1
200K _0201_1%
200K _0201_1%
200K _0201_1%
1
2
PR2649
PR2650
PR2648
@ @ @
2
PR2654 PR2655 PR2653

3
0_0201_5% D 0_0201_5% D 0_0201_5% D

1 2 5 1 2 5 1 2 5
<44,81> VBUS_C_CTRL_P1# <44,81> VBUS_C_CTRL_P2# <48,81> VBUS_C_CTRL_P3#
G PQ2568B G PQ2569B G PQ2567B
2N7002KDW_SOT363-6 2N7002KDW_SOT363-6 2N7002KDW_SOT363-6
S S S
4
Vinafix.com PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
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NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
Title
Smart Adapter circuit (39.1) PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Si ze Document
P081-PWR_Switch

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A B C D E

MODEL NAME : FDQ50 / FDC55

Vinafix.com Security Classification Compal Secret Data Compal Electronics, Inc.

Date: Friday, November 22, 2019 Sheet 1 of 100

Quadro PEG 3.0 x8 lane 45W 8C+2 USB_31 P.48

M.2 Slot C Key-M

Touch Panel I2C BUS Port0 (I2C0)

G3/SPI 48MHz I/O Fuction Board Connector P55

PWM PS/2 Battery Gauge

Fan Control Touch Pad BCBUS KBC KSIO Int.KBD

Security Classification Compal Secret Data Compal Electronics, Inc.

5 None 5 Type-C Conn 2 (Right Side) 4 Type-C Conn 1 (Right Side)

6 None 6 None 5 Type-C Conn 2 (Right Side)

PCI EXPRESS DESTINATION USB3.0 DESTINATION 8 None 7

Lane 1 7 None 9 None

Lane 2 8 None 10 Finger Print

Lane 4 10 None 14 NGFF-1 WLAN + BT

Lane 6 CNVi WLAN + BT CLKOUT_PCIE DESTINATION CLKOUT_PCIE DESTINATION

Lane 7 CARD READER 0 None 10 None

Lane 8 None 1 NGFF-2 SSD2 11 None

1 Lane 9 SSD 2 None 12 None 1

Lane 10 SSD SATA DESTINATION 3 NGFF-2 SSD1 13 None

Lane 11 SSD 0A N/A 4 CARD READER 14 None

Lane 12 SSD 1A SSD 5 Thunderbolt 15 None

Lane 13 None 0B N/A 6 NGFF-1 WLAN

Lane 14 None 1B N/A 7 GPU

Lane 16 None A3 N/A 9 None

Lane 17 SSD_2 A4 SSD

Lane 18 SSD_2 A5 N/A

Date: Friday, November 22, 2019 Sheet 3 of 100

UZ6 Rail Name G517AL1TP1U +EDPVDD

MP2979AGQKT VR_ON Rail Name

TPS51285BRUKR ALWON RUN_ON_EC

Rail Name UZ16

Vinafix.com Security Classification

Dat e: Friday, November 22, 2019 Sheet 4 of 100

G3->S5 [Battery only, AC absent]

RTC Standup EC_Output RTCRST#SRTCRST#

+1.0V _MPHY GT VCCPRIM_GATED_1P05

EC Output PCH_RSMRST# tPCH32 : DSW_PWROK high to RSMRST# high

PCH_Output CL_RST# (Vpro and nVpro different)

Vinafix.com Security Classification

RH24 1 2 24.9_0201_1% PEG_RCOMP G2

<16> DMI_CRX_PTX_P1 E6 C6 DMI_CTX_PRX_P1 <16>

<16> DMI_CRX_PTX_P2 D5 B5 DMI_CTX_PRX_P2 <16>

<42> CPU_DP1_AUXP D27 C26 EDP_AUXP <38>

Security Classification Compal Secret Data Compal Electronics, Inc.

ECC Byte swapping (with othe Bytes) is not allowed.

Security Classification Compal Secret Data

CFG Straps for Processor

1 : Disabled; No Physical Display Port

TP@PAD~D T45 CMRSVD15 BN35

TP@PAD~D T48 CMRSVD14 BN33

TP@PAD~D T58 CMRSVD23 E30

TP@PAD~D T59 CMRSVD7 B30 BL31 CMRSVD12 T82 PAD~D TP@

Security Classification Compal Secret Data Compal Electronics, Inc.

+VCC_CORE +VCC_CORE +VCC_CORE +VCC_CORE

96000mA(Hexa Core GT2)

AG34 K13 W30

AG37 VCC_SENSE_R RH198 1 2 0_0402_5% @

1. Vcc_SENSE/ Vss_SENSE Trace Length Match < 25 mils

Security Classification Compal Secret Data

Backside cap Backside cap