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  • 171 EE3041 XuLyTinHieuSoVoiFPGA

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    23 views8 pages

    171 EE3041 XuLyTinHieuSoVoiFPGA

    Uploaded by

    hottruong

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
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    DHQG TPHCM-DH Bach Khoa Khoa D-DT-BM Bign Tir De thi HK 17) Mon: Xir ly tin higu s voi FPGA (MSMIL: FE3041) _ Neay thi: 2112/2017 ~ Thi gian Kim bai: 90 phit (SV KHONG duo sir dung tii liga, Laptop. PC Tablet va dign thoai di dongs (Clu 1: (2 d) Hay trai ra (unfold) DEG trong hinh sau von hé so J (2 @) (6) 3D 6/+0,2.4 | Cie cng oc Ww. w! 4D U—V, = U,V, : ©) voi k= (i+ w)%d va w'=L(i + Wd (E) ai+735 Witu=J(Wi+Lu/d!) + (u%d) Cau 2: (2 d) Cho trudc hé théng & hinh sau (cae s6 di kém b6 cény ‘nhn 1a $6 thir ne cus mut) vi mdi bd han c6 pipeline 2 tang vi Tw = 2u.t.. mdi bO cOng cé pipeline | ting vaTa = Nut at As IN = . - - OUT i i i a i 2) AZ ya eno) ' ms m2 Ma Hay gap (fold) DFG nay vai hé sé gap N = 4 voi cae tap gip sau: Su = (M4, M1, M2, M3} Sa = (Al, Ad, a3, A2} a) Thye hign ti dinh thi dé cae tap gap cho két qui ehi cO cde tri hodn Khong am trong ci true wap b) Gap DFG da durge tai dinh thi: chi lip bang tinh thoi gian Tiy vit Tyer cust MOI nut. khOny ean ve hind Ghi chi: © Phuong trinh gap Dr: e D,(U=+V) = Nw(e)-P,+v-u voi w(e) la sé phan tur Delay trén canh e, P, La s6 ting pipeline ewa nit UL v la 96 thir rena V trong tip gdp chia V. va u fa sé thar ty cua U trong tap pap chita | © Cong thite tinh théri gian vido Tip va thoi gian ra Ty twang tiny cho sit U. Tin = + Py si To = + Pu + max{DH(U > Vd} (Cfu 3: (2.4) Thigt ké mach bign doi ma iri 3 x 3 vor | ngd vaw va Lad ra they quy tie saw Ma tran vao Ma train ra fa bec] fe ab (def > jefd ig hoi iohg DSP-FPGA Thi HK 171 wang 1.2 8.7.65 4.3.2 1]0 gihli di febialc 876543210 ing fiedcba a) Lap bang thoi gian sony va gian dé thi gian séng, tt dé suy ra sO thanh whi cin cho mach nay 18 bao nhiéu? b) Lap bang ep phat thanh ghi thudin-ngbich. (Khong cin v2 mach) Cu 4: (2 d) Xét 1 b9 loc co phutong trinh ngd ra: y(n) = ax(n) + bx(n — 2) + ex(n~ 4) + dx(n- 6) a) Hay vé DG cua bé loc nay, Lap cng thite mé ta RIA (chun ngo ra) wong duveny cho wi th nay. Tird6 suy ra ede canh co ban es, ee Vie? b) Cho tude d = [1 OJ! timp vas (Gia sit dp va s phai thou cae digu kign: pld= 0: sTd#0 va sle> 0) ¢) V8 mang tam thu can thiet ke Cau 5: (2.4) Thiét ké mach loc FIR od 3 nhanh (ré) G-tap FIR filter) ¥(N) = hox(n) + hix(n-1) + hax(n-2) v6i cdc hé 56 Ia hy = 109, i= 107, vay = HU a) Véi sé hoc phan bo (distributed arithmetic), hy eho bidt cin di cia FPGA) c6 kich tharde bao mhigu va ndi dung cus bang ni b) Viet ma Verilog cho mach loc nay. (Gia sir ngd vau mai Lan cung edp 3 nvdu det Ligu lien Gep: x(n), xin 1) va x(n-2),) ln eit (ROM hose BG mon ant Ky GV rede oe Ma HG Trung My DSP-FPGA Thi HKI71 trang 22 DHQG TPHCM-DH Bach Khoa Khoa D-DT-8M ign Tir Dap an cua Dé thi HK 171 Xir ly tin higu s6 voi FPGA (MSMIL: EE3041) Ngay thi: 21122017 ‘Théi gian kim bai: 90 phi (SV KHONG dirge surdung tai figu, Laptop, PC Tablet vii dién thoui di dongs Cau 1: (24) Vi co phan tl Delay néi voi khoa, ta thém nut gia F (A= Ow }24F) 61+ 0,2,4 —-©) Ye 61+ 1,3,5 Thy hién trai ra DFG theo bang sau voi J = 3. (0.5) Ww Ww UAV, = uv, Bang dang 1 Bang dang 2 ij ow (i+ w)%3 | w' =i (i + wy/3 | iow k 0 3 cae 7 ae ! e ff 3 0 1 3 fora, 4 2/3 fgets o| 4 1 1 ) [aja 2 2 | 4 yey fo | 5 career | 1 5 é u 2 [5 eiaesein ee Thye hign trai ra DFG cho cac nut B, E va C voi khoa thee cas thoi dics sa WI + u=J( Wl +Lu/JJ) + (u%u) Taco: W=W'J => W' = WiJ = 6/3 = Tu do ta co bang sau: (0.5 <4) of diéin Chuyer 61 +0 = 3/2) + 0) + i 61+ 2= 3/2140) 42 6l+4=3(2I4 1) 47 | Bat xudng lore 7= 321+ 0)94 ! 6143 = 3216 1) + 6145 3/2 1) 4 el Dap an cia DSP-FPGA Thi HKITI - wang 16 Kt qua sau ciing khi bo cac nuit gia: (1 d) Phvon teint ma 1 Cau 2: (2d) ‘Thu ty trong tap gap: 0 4 2 3 Sa= {Al A, A3 AQ} Sw= (M4, M1, M2, M3} Néu danh sé nut theo thi'tu: 1. 4 twongangvoiAt -Ad.a5 GS tuenga Nhu vay ta ¢@ tap gap cho cac nut o 1 2 3 S= 4 3 2 Sa= {8 5 6, 7} Khi dé ta co bang sau: (0.5 d) Phuong trinh gap De 10.5.8) Sau khietming Dp(U a1) = Nwiey= Py eras Dy als Meta =e D-(1 >» 3)= 4 (0) -1 ee ea Yeats e- ve Det» 5)=4(1)-1 Dit 4(W)-12 120s 0 Det —» 7)=4(1)-1 | Dt Det > 6)= 4 (2)~1 Dx > 8)= 4 (2)-1 Det + B= D2 > 1)= 4(0)-140-3= Dif4 + 3)= 4(0)-142~ = [x5 > 2)= 4(0)-2+3-1= 0 Dx6 —~ 2)= 4(0)-2+3-2 DA? > 4)= 4(0)-2+1-3= -4(°7) Dit aia) 1+ > a(y-iey 4(1) = OA8 = 4)= 4(0)-2+1-0= 107) 41-24 Voi bang trén ta thy vige tsi dinh thi s@ phai xay ra voi cac ay, os Bip an cita DSP-FPGA_Thi HKI71 trang 2'6 0 2e1-320 mt D. 21,62, 7-94, va8 «4 viDs

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