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Course Code: CSE205
Semester: IV
COMPUTER ARCHITECTURE
Course Objectives
Computer Architecture course aims to describe a broad range of architectural designs, with an
emphasis on understanding concurrency at different levels like Instruction level parallelism,
thread level parallelism, Data level parallelism and exploiting memory hierarchy for
performance optimization.

UNIT- I 16 Periods
Introduction: Classes of Computers-Defining Computer Architecture-Trends in Technology-
Trends in Power and Energy in Integrated Circuits-Trends in Cost-Dependability- Measuring,
Reporting, and Summarizing Performance-Quantitative Principles of Computer Design.
Instruction-Level Parallelism: Concepts and Challenges-Basic Compiler Techniques for
Exposing ILP-Reducing Branch Costs with Advanced Branch Prediction-Overcoming Data
Hazards with Dynamic Scheduling-Dynamic Scheduling: Examples and the Algorithm-
Hardware-Based Speculation

UNIT - II 14 Periods
Data-Level Parallelism: Introduction-Vector Architecture-SIMD Instruction Set Extensions
for Multimedia-Graphics Processing Units-Detecting and Enhancing Loop-Level Parallelism-
Crosscutting issues-Mobile Vs Server GPUs and Tesla Vs Core i7

UNIT - III 13 Periods

Thread-Level Parallelism: Introduction-Centralized Shared-Memory Architectures-
Performance of Symmetric Shared-Memory Multiprocessors-Distributed Shared-Memory
and Directory-Based Coherence-Synchronization: The Basics-Models of Memory
Consistency: An Introduction
Warehouse-Scale Computers to Exploit Request-Level: Introduction-Programming
Models and Workloads for Warehouse-Scale Computers-Computer Architecture of
Warehouse-Scale Computers
UNIT - IV 17 Periods
Memory Hierarchy Design: Introduction-Ten Advanced Optimizations of Cache
Performance-Memory Technology and Optimizations-Protection: Virtual Memory and
Virtual Machines-The Design of Memory Hierarchies-Memory Hierarchies in the ARM
Cortex-A8 and Intel Core i7. Review of Memory Hierarchy: Cache Performance-Six Basic
Cache Optimizations-Virtual Memory-Protection and Examples of Virtual Memory

TEXT BOOK
1. John L. Hennessy, David A. Patterson. Computer Architecture - A Quantitative
Approach, Morgan Kaufmann is an imprint of Elsevier, Fifth Edition, 2012.

REFERENCE
1. William Stallings. Computer Organization and Architecture - Designing for
Performance, Pearson Education, Tenth edition, 2006.
ONLINE MATERIAL
1. https://nptel.ac.in/courses/106102062/

UNITWISE LEARNING OUTCOMES

Upon successful completion of each unit, the learner will be able to
Unit I  Identify trends in technology to evolve modern implementations with
performance evaluation
 Select techniques for extending basic pipelining to increase parallelism
explored at instruction level
Unit II  Illustrate vector architecture and summarize SIMD instruction set
 Extend enhancement of loop level parallelism
Unit III  Recall the basic architecture of centralised and distributed shared
memory
 Apply programming model and demonstrate the workload for
warehouse scale computers
Unit IV  Manipulate evaluation metrics for improving cache performance
 Cache optimizations and virtual memory protection

COURSE LEARNING OUTCOMES

Upon successful completion of this course, the learner will be able to
 Identify trends in technology to evolve modern implementations with performance
evaluation
 Select techniques for extending basic pipelining to increase parallelism explored at
instruction level.
 Illustrate vector architecture and summarize SIMD instruction set
 Recall the basic architecture of centralised and distributed shared memory
 Manipulate evaluation metrics for improving cache performance
 Justify cache optimizations approaches and explain virtual memory protection
techniques
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Course Code: CSE206
Semester: IV

COMPUTER SYSTEM DESIGN LABORATORY

Course Objectives
This course will help the learner to understand I/O operations, Timer, ADC operations,
Interrupts and Memory management for ARM architecture

List of experiments

I / O operations
1. Controlling the GPIO pins of Mbed Board.
2. Controlling the on board LEDs and Switches

Timer
3. Designing Digital clock using 7 segment display on Mbed board.
4. Designing Program flow control using Internal Timers

ADC and DAC Operation

5. Interfacing ADC on Mbed Board.
6. PWM based DC motor control using POT

Interrupts
7. Implementation of Hardware Interrupt controlled Hexadecimal and decade counters
8. Implementation of Hardware Interrupt controlled closed loop control system

Assembly Language Programming (MASM/KEIL)

9. Program on memory segmentation
10. Program on Interrupt service
11. Program on Task context maintenance
12. Program on Paging

Additional Exercise
Designing the cache memory for performance using GEM5
COURSE LEARNING OUTCOMES
Upon successful completion of this course, the learner will be able to
 Demonstrate I/O operations using Mbed board
 Demonstrate Timer operations
 Illustrate the ADC and DAC signals in Mbed board
 Demonstrate interrupt routines for counter and closed loop control system
 Demonstrate memory management using Assembler directives