Analog Electronic Circuits (17EI33), 3rd Sem EIE

Analog Electronic
Circuits
(18EI33)
rd
3 Sem EIE
Module - 1:
BJT AC analysis (Problems)

P Manohar
Associate Professor
Dept. of EIE
RNSIT
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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

Syllabus

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

1. BJT AC Analysis - I (Problems)

1. The re transistor model
2. CE Fixed Bias Configuration
3. CE Voltage Divider Bias Configuration
4. CE Emitter Bias Configuration
5. Emitter Follower Configuration
2. BJT AC Analysis - II (Problems)
1. Cascaded Systems
2. The Hybrid Equivalent Model
3. Approximate Hybrid Equivalent Circuit

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

1. BJT AC Analysis - I (Problems)

There are two models commonly used in the small-signal ac analysis of transistor networks:
i) the re model and
ii) the hybrid equivalent model.

1. The re transistor model :

Fig. 1.1: Common emitter BJT

Improved BJT Equivalent circuit:

26mV
rd  re 
IE

Fig 1.2: Improved BJT Equivalent circuit

1) Input impedance Zi:

Vbe
Zi   (   1)re
Ib
or
Z i  re
2) Output impedance Zo:
VCE
Z o  ro 
I C

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE
3) Voltage Gain Av:

Fig 1.3: Determining the voltage gain and current gain for the common-emitter transistor amplifier.

Vo  RL
Av  
Vi re
4) Current Gain Ai:
Io
Ai  
Ii

re model for the common emitter transistor configuration:

Fig 1.4: re model for the CE config.

P - 1.1: Using the re model, determine the following if β = 80, IE(dc) = 2 mA and ro = 40 kΩ
a) Zi
b) Ib
c) Ai = Io/Ii = IL/Ib if RL = 1.2 kΩ
d) Av if RL = 1.2 kΩ

Fig 1.5: re model

26mV 26mV
re    13
IE 2mA

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE
a) Z i  re  80  13  1.04k
b) I E  (   1) I b
I 2mA
IB  E   24.691A
  1 81
c) I
Ai  L
IB
I  r 80(24.691A)(40k)
IL  B o   1.917mA
ro  RL 40k  1.2k
I 1.917mA
Ai  L   77.639
I B 24.691A
d) V  (ro || RL )  1.165k
Av  o    89.615
Vi re 13 where
ro RL 40k  1.2k
ro || RL    1.165k
ro  RL 41.2k
P - 1.2: Using the re model, determine the following if β = 140, IE(dc) = 3.525 mA and ro = 50
kΩ
a) Zi
b) Ib
c) Ai = Io/Ii = IL/Ib if RL = 2.7 kΩ
d) Av if RL = 2.7 kΩ

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

2. CE Fixed Bias Configuration

Fig. 2.1: CE fixed-bias amplifier

Fig 2.2: ac equivalent circuit for the common emitter fixed bias network
1) Input impedance Zi:
Z i  RB || re
But, usually RB ≥ 10βre
Therefore,
Z i  re

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE
2) Output impedance Zo:
Z o  RC || ro
If ro ≥ 10RC, then
Z o  RC

3)Voltage Gain Av:

Vo R || r
Av   C o
Vi re
The effect of ro can be ignored if ro ≥ 10RC
Vo R
Av   C
Vi re
DC Analysis:

Vcc  VBE
IB 
RB

I E  (  1) I B

26mV
re 
IE

Fig 2.3: Fixed Bias Circuit

P-2.1: For the network of Fig. 2.4:

(a) Determine re.
(b) Find Zi (with ro = ∞Ω).
(c) Calculate Zo (with ro = ∞Ω).
(d) Determine Av (with ro = ∞Ω).
(e) Find Ai (with ro = ∞Ω).

Fig. 2.4: CE fixed-bias amplifier

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

Fig 2.5: ac equivalent circuit for the common emitter fixed bias network
DC analysis:
a)

AC analysis:
b)

c)

d)

e)

1.069k
Ai  (280.11)  99.81
3k
P-2.2: Repeat problem P-2.1 by including ro = 50 kΩ in all calculations and compare results.

a)

c)

d)

e)

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

P-2.3: For the network of Fig. 2.6:

(a) Determine Zi and Zo.
(b) Find Av and Ai.
(c) Repeat part (a) with ro = 20 kΩ
(d) Repeat part (b) with ro = 20 kΩ.

Fig. 2.6: CE fixed-bias amplifier

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

3. CE Voltage Divider Bias Configuration:

Fig 3.1 : CE Voltage divider bias amplifier

Fig 3.2: ac equivalent circuit of the voltage divider bias network

R1 R2
R '  R1 || R2 
R1  R2
1) Input impedance Zi:
Z i  R' || re
2) Output impedance Zo:

Z o  RC || ro
If ro ≥ 10RC, then
Z o  RC

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE
3)Voltage Gain Av:
Vo R || r
Av   C o
Vi re
The effect of ro can be ignored if ro ≥ 10RC
Vo R
Av   C
Vi re
DC Analysis:
Test βRE ≥ 10R2
RV
VB  2 cc
R1  R2

VE  VB  VBE
VE
IE 
RE
26mV
re 
IE

Fig 3.3: Voltage Divider Bias Circuit

P-3.1: For the network of Fig. 3.4,

determine:
(a) re.
(b) Zi.
(c) Zo (ro = ∞Ω ).
(d) Av (ro = ∞Ω ).
(e) Ai (ro = ∞Ω ).

Fig 3.4 : CE Voltage divider bias amplifier

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE
Fig 3.5: ac equivalent circuit of the voltage divider bias network
DC analysis:
a)

AC analysis:
b)

c)

d)

e)

1.35k
Ai  (368.76)  73.209
6.8k
P-3.2: Repeat problem P-3.1 by including ro = 50 kΩ in all calculations and compare results.

a)

c)
d)

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE
e)
1.35k
Ai  (324.3)  73.211
5.98k
P-3.3: For the network of Fig. 3.6:
(a) Determine re
(b) Calculate Zi and Zo.
(c) Find Av and Ai.
(d) Repeat part (b) with ro = 25 kΩ.

Fig. 3.6: CE Voltage divider-bias amplifier

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

4. CE Emitter Bias Configuration (Unbypassed)

Fig 4.1: CE emitter bias configuration

Fig 4.2: ac equivalent circuit of the CE Emitter bias network

The input impedance looking into the network to the right of RB

Vi
Zb   re  (   1) RE
Ib
Z b  re  RE
Z b   (re  RE ) or Z b  RE Since RE >> re,

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE
1) Input impedance Zi:
Z i  RB || Z b

2) Output impedance Zo:

Z o  RC

3)Voltage Gain Av:

Vo R
Av   C
Vi Zb
For the approximation, Z b  RE
Vo R
Av   C
Vi  RE
Vo R
Av   C
Vi RE
DC Analysis:

Vcc  VBE
IB 
RB  (   1) RE

I E  (  1) I B

26mV
re 
IE

Fig 4.3: Emitter Bias Circuit

P-4.1: For the network of Fig.4.4, without CE

(unbypassed), determine:
(a) re.
(b) Zi.
(c) Zo.
(d) Av.
(e) Ai.

Fig 4.4:CE Emitter Bias Amplifier

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

Fig 4.5: ac equivalent circuit of the CE Emitter bias network

DC analysis:
a)

AC analysis:
b)

c)
d)

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE
e)

P-4.2: For the network of Fig. 4.6:

(a) Determine re.
(b) Find Zi and Zo.
(c) Calculate Av and Ai.

Fig 4.6:CE Emitter Bias Amplifier

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

5. Emitter Follower configuration

Fig 5.1: Emitter follower configuration

Vo
Av  1
Vi

Fig 5.2: ac equivalent circuit of the Emitter follower network

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

Vi
Zb   re  (   1) RE
Ib

The input impedance of a transistor with an unbypassed resistor RE is determined by

Z b  re  (  1) RE

Z b  re  RE

Z b   (re  RE )
Since RE >> re, Z b  RE
1) Input impedance Zi:
Z i  RB || Z b
2) Output impedance Zo:
Z o  RE || re
RE >> re,
Therefore,
Z o | re
3)Voltage Gain Av:
Vo RE
Av  
Vi RE  re
But RE >> re,
therefore,
Vo
Av  1
Vi
DC Analysis:
Vcc  VBE
IB 
RB  (   1) RE

I E  (  1) I B

26mV
re 
IE

Fig 5.3: Emitter Bias Circuit

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

P-5.1 For the emitter-follower network of Fig.

5.4, determine:
(a) re.
(b) Zi.
(c) Zo.
(d) Av.
(e) Ai.

Fig 5.4: Emitter follower

Fig 5.5: ac equivalent circuit of the Emitter follower network

DC analysis:
a)

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

AC analysis:
b)

c)

d)

e)

P-5.2: For the network of Fig. 5.6:

(a) Determine re and βre.
(b) Find Zi and Zo.
(c) Calculate Av and Ai.

Fig 5.6:Emitter Follower

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

1. BJT AC Analysis - II (Problems)

Single Stage Amplifier:
i) Single stage Amplifier with no Source VS and no Load RL.

Fig. 2.1: Single stage amplifier

The No-load Voltage gain AvNL is given by

ii) Single stage Amplifier with Source VS but no Load RL (i.e., RL =∞)

The No-load Voltage gain with source AVs is given by

iii) Single stage Amplifier with Load RL but no source VS (i.e., VS = 0)

The Loaded Voltage gain AvNL is given by

Vo A R
AvL   vNL L
Vi Z o  RL

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

iv) Single stage Amplifier with Load RL and source VS

Vo A Z
AvS   vL i
VS Z i  RS
AvNL RL
where AvL 
Z o  RL

1. Multistage Amplifier (Cascaded System):

Fig 2.2: Cascaded System

The total voltage gain of the cascaded system is
Vo
AvT   Av1. Av 2
Vi
V A Z
where Av1  o1  vNL1 i 2 ----loaded gain of stage 1
Vi Z i 2  Z o1
V A R
Av 2  o  vNL2 L ----loaded gain of stage 2
Vi 2 RL  Z o 2
AvNL1 ----- No load gain of stage 1
AvNL2 ----- No load gain of stage 2

Vo Zi
AvS   AvT where Z i  Z i1
VS Z i  Rs

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE
The total current gain is
Zi
AiT   AvT . where Z i  Z i1
RL

P-1.1: For the configuration of Fig. 2.3, determine:

(a) The loaded gain for each stage.
(b) The total gain for the system, Av and Avs.
(c) The total current gain for the system.
(d) The total gain for the system if the emitter-follower configuration were removed.

Fig 2.3 : Cascaded System

(a) For the emitter-follower configuration, the loaded gain is

For the common-base configuration, the loaded gain is

(b)

(c)

(d)

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE
P - 1.2: For the cascaded system of Fig. 2.4 with two identical stages, determine:
(a) The loaded voltage gain of each stage.
(b) The total gain of the system, Av and Avs.
(c) The total current gain of the system.

Fig 2.4 : Cascaded System

2 The Hybrid Equivalent Model

2.1 Complete Hybrid Equivalent circuit:

Fig 2.5: Complete Hybrid Equivalent circuit

Common emitter configuration:

Fig 2.6: a) Graphical symbol
hie → input resistance
hre →reverse transfer voltage ratio
hfe → forward transfer current ratio
hoe → output conductance
Fig 2.6 (b) Hybrid Equivalent circuit
 The input current, Ii = Ib,
 The output current, Io = Ic
 Ie = Ib + Ic.
 The input voltage Vi = Vbe,
 The output voltage Vo = Vce.

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

3. Approximate Hybrid Equivalent Circuit

Fig 2.7 Approximate hybrid equivalent circuit.

3.1 Approximate Hybrid model versus re model:

Fig. 2.8 Hybrid versus re model of common-emitter configuration

hie  re

h fe   ac

P - 3.1: Given IE = 2.5 mA, hfe = 140, hoe = 20µS, determine the common-emitter hybrid
equivalent circuit.

Fig 2.9 Approximate hybrid equivalent circuit.

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

P - 3.2: (a) Given IE (dc) = 5.8 mA, β = 120, and ho = 25 µS, sketch the Common-emitter hybrid
equivalent model.
(b) Given hie = 1 kΩ, hre = 2 × 10-4, hfe = 90, and hoe = 20 µS, sketch the re model.
Fixed-bias configuration:

Fig 2.10: Fixed-bias configuration.

Fig 2.11: approximate hybrid equivalent circuit

1) Input impedance Zi:
Z i  RB || hie
2) Output impedance Zo:
Z o  RC || 1 / hoe
Z o  RC
3) Voltage Gain Av:
Vo h ( R || 1 / hoe )
Av    fe C
Vi hie
4) Current Gain Ai:
Io
Ai   h fe
Ii

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

P - 3.3: For the network of Fig. 2.12, determine:

(a) Zi.
(b) Zo.
(c) Av.
(d) Ai.

Fig 2.12: Fixed-bias configuration.

(a)

(b)

(c)

(d)

Voltage-Divider Configuration:

Fig 2.13: Voltage-divider bias configuration.

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

Fig 2.14: Approximate hybrid equivalent circuit

1) Input impedance Zi:
Z i  R' || hie
where R'  R1 || R2
2) Output impedance Zo:
Z o  RC || 1 / hoe Z o  RC
or
3) Voltage Gain Av:
Vo h ( R || 1 / hoe )
Av    fe C
Vi hie
4) Current Gain Ai:

Vo h fe R '
Ai   '
Vi R  hie
P - 3.3: For the network of Fig. 2.15:
(a) Determine Zi and Zo.
(b) Calculate Av and Ai.

Fig 2.13: Voltage-divider bias configuration.

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 Analog Electronic Circuits (17EI33), 3rd Sem EIE

(a) R '  R1 || R2 Z o  RC
68k  12k  2.2k
R' 
(68k  12k)
 10.2k
Zi  R' || hie
10.2k  2.75k
Zi 
(10.2k  2.75k)
 2.16k
(b) h fe 180 h fe R ' 180  10.2k
Av   Rc    2.2k  144 Ai   
hie 2.75k R  hie
'
(10.2k  2.75k)
 12.95

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