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SRM IST
Faculty of Engineering and Technology
Department of Electronics and Communication Engineering
18ECC201J – Analog Electronics Circuits Laboratory
Fourth Semester, 2019-20 (Even Semester)

LABORATORY REPORT COVER SHEET

Name : Hrivu Dasmunshi

RegisterNumber : RA1911004010566

Semester/Section : 4 sem/Isection

Batch 2

Venue : TP-1019

Title oftheExperiment : Design and analysis of Bjt common emitter amplifier

configuration.

DateofPerformance : 25/01/2021

DateofSubmission :10/02/2021

Particulars Max. Marks Marks Obtained

Pre and Post Lab Questions 10

Design and Calculations 15

Lab Performance & record 15

Total 40

REPORT VERIFICATION

StaffName : Umamaheswari S

StaffSignature :
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1.DESIGN AND ANALYSIS OF BJT COMMON EMITTER AMPLIFIER

CONFIGURATION

1.1 OBJECTIVE

1. To design a single stage CE amplifier Circuit for the givenspecifications.

2. To perform the transient analysis and determine the phase difference between input and
output signals.
3. To measure the voltage gain of the amplifier over a range of frequencies and plot the
frequency responsecurve.
4. To determine the values of lower and upper 3-dB frequencies and 3-dBbandwidth.

1.2 HARDWAREREQUIRED

a. Powersupply : Variable regulated low voltage DC source(0-30V,0-2A)

b. Equipments : AFO(0.3Hz-3MHz),CRO(0-30MHz)
c. Resistors : To becalculated.
d. Capacitors : To becalculated.
e. Semiconductors : BC 107 (orequivalent)
f. Miscellaneous : Breadboard andwires.

1.3 THEORY

Amplifier is an electronic circuit that is used to raise the strength of a weak signal. The
process of raising the strength of a weak signal is known as amplification. One importance
requirement during amplification is that only the magnitude of the signal should increase and
there should be no change in signal shape. The transistor is used for amplification. When a
transistor is used as an amplifier, the first step is to choose a proper configuration in which
device is to be used. Then the transistor is biased to get the desired Q-point. The signal is
applied to the amplifier input and gain is achieved.
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1.3.1 CE amplifieroperation
Consider a CE amplifier circuit as shown in fig. 1-1

Rc
R1
CC

Vout
Vcc Rs Cc
Q1

Rf

Vin
R2

Re
Ce

Fig 1.1 CE Amplifier

When the capacitors are regarded as ac short circuits, it is seen that the circuit input
terminals are the transistor base and emitter, and the output terminals are the collector and the
emitter. So, the emitter terminal is common to both input and output, and the circuit
configuration is termed Common – Emitter (CE).

1.3.2 TransientAnalysis
Transient analysis is nothing but taking voltages and current at different instants.It is
seen that there is a 180ophase shift between the input and output waveforms (Figure
2.4(a&b)). This can be understood by considering the effect of a positive going input signal.
When VS increases in a positive direction, it increases the transistor VBE. The increase in VBE
raises the level of IC, thereby increasing the drop across Rc, and thus reducing the level of the
VC. The changing level of VC is capacitor-coupled to the circuit output to produce the ac
output voltage, VO. As VS increases in a positive direction, VO goes in a negative direction.
Similarly, When VS changes in a negative direction, the resultant decrease in VBE reduces the
IC level, thereby reducing VRC, and producing a positive goingoutput.
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1.3.3 CE amplifier circuit elements and theirfunctions

(i) Biasing circuit:The resistances R1, R2 and RE form the biasing and stabilization
circuit.The biasing circuit must establish a proper operating point, otherwise a part of
the negative half-cycle of the signal may be cut-off in theoutput.
(ii) Input capacitor, C1: An electrolyte capacitor C1 is used to couple the signal to the base
of the transistor. If it is not used, the signal source resistance, Rs will come across R2 and
thus change the bias. C1 allows only ac signal to flow but isolates the signal source from
R2.
(iii) Emitter bypass capacitor, Ce: An Emitter bypass capacitor, Ce is used parallel with RE
to provide low reactance path to the amplified ac signal. If it is not used, then
amplifiedac signal flowing through RE will cause a voltage drop across it, thereby
reducing theoutputvoltage.
(iv) Coupling capacitor, Cc: The coupling capacitor, Cc couples one stage of amplificationto
the next stage. If it is not used, the bias conditions of the next stage will be
drasticallychanged due to the shunting effect of RC. This is because RC will come in
parallel with the upper resistance R1 of the biasing network of the next stage, thereby
altering the biasing conditions of the latter. In short, the coupling capacitor C2 isolates
the dc of onestage from the next stage, but allows the passage of acsignal.
1.3.4 CE amplifier circuitcurrents
(i) Basecurrent
iB = IB +ib
Where IB = dc base current when no signal is applied
ib = ac base when ac signal is applied
and iB = total basecurrent
(ii) Collectorcurrent
iC = IC+ic
Where IC = zero signal collector current
ic = ac collector current when ac signal is applied
and iC = total collectorcurrent
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(iii) EmitterCurrent
iE = IE + ie
Where IE = Zero signal emitter current
Ie = ac emitter current when ac signal is applied
and iE = total emittercurrent
It is useful to keep in mind that
IE = I B + I C
and ie = ib +ic

Also, IE IC and ieic

1.3.5 CE amplifier frequencyresponse
The voltage gain of an amplifier varies with signal frequency. It is because reactance’ s
of the capacitors in the circuit changes with signal frequency and hence affects the output
voltage. The curve between voltage gain and signal frequency of an amplifier is known a
frequency response. Figure 1.5
It is clear that the voltage gain drops off at low (< fL) and high (> fH) frequencies
whereas it is uniform over mid-frequency range (fL to fH).
(i)
At low frequencies (< fL), the reactance of coupling capacitor is quite high and hence
very small part of signal will pass from amplifier stage to the load. Moreover, CE cannot shunt
the RE effectively because of its large reactance at low frequencies. These two factors cause
afalling of voltage gain at low frequencies.
(ii)
At high frequencies (> fH), the reactance of Cc is very small and it behaves as a
shortcircuit. This increases the loading effect of amplifier stage and serves to reduce the
voltage gain. Moreover, at high frequency, capacitive reactance of base-emitters junction is
low which increases the base current. These reduce the current amplification factor. Due to
these two reasons, the voltage gain drops off at highfrequency.
(iii)
At mid frequencies (fL to fH), the voltage gain of the amplifier is constant. The effect
ofcoupling capacitor Cc in this frequency range is such as to maintain a uniform voltage
gain.Thus, as the frequency increases in this range, reactance of CC decreases which tend
toincrease thegain.
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1.3.6 CE amplifieranalysis
The first step in AC analysis of CE amplifier circuit is to draw ac equivalent circuit by
reducing all dc sources to zero and shorting all the capacitors. Fig 1.2 shows the ac equivalent
circuit.

Rs R
Q1 Q1

Rc R
R1R2 R R
Vs Vs

Fig 1.2: Equivalent Circuit of CE

The next step in the ac analysis is to draw h-parameter circuit by replacing the transistor
in the ac equivalent circuit with its h-parameter model. Fig. 1.3 shows the h-parameter
equivalent circuit for CE circuit.

Fig 1.3: h- Parameter Equivalent Circuit

The typical CE circuit performance is summarized below:
Device input impedance, Zb = hie
Circuit input impedance, Zi = R1|| R2|| Zb
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1
Device outputimpedance,Z 
C
hoe

Circuit output impedance, ZO RC ZC RC

h fe
Circuit voltage gain, A  (R R)
V C L
hie

Circuit current gain, A

hfe RC RB
i
(RC  RL)(RC  hie)

Circuit power gain, AP = AV x Ai

1.4 MODELGRAPH
1.4.1 TransientAnalysis

Fig 1.4(a) Input Voltage Waveform

Fig 1.4(b) Output Voltage Waveform

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1.4.2 FrequencyResponse

Fig 1.5 Frequency Response

1.5 CE AMPLIFIER CIRCUITDESIGN

Design of CE circuit normally commences with a specification of supply voltage,

minimum voltage gain, frequency response, signal source impedance load impedance,
stability factor and the Q-point.
Selection of IC, RC and RE
h fe
A  (R R )
V C L
hie

 For satisfactory transistor operation, Ic should not be less than 500µA. A good
minimum Ic to aim for is1mA.
 The VCE should typically be around 3v to ensure that the transistor operates linearly
andto allow a collector voltage swing of ±1v which is usually adequate for small-
signalamplifier
o Note: RC should normally be very much larger than RL, so that RL has little effect
onvoltagegain.

 Select VE = 5v for good bias stability in mostcircumstances.

o Note: When VE>>VBE, VE will be only slightly affected by any variation in VBE (due
totemperature change or othereffects)

 Once VE, VCE and Ic are selected, VRC is determined as VRC = VCC – VCE –VE

VRC VE
Then, RC and RE are calculated as RC and R E
IC IC
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Selection of bias resistors

As discussed in lab-1, experiment-1.1, section-1.1, selection of voltage divider current
(I2) as IC/10 gives good bias stability and reasonably high input resistance. The bias resistors
are calculated as
V
R  B and R VCC VB
2 1 
I2 I2

Selecting R2 = 10RE gives I2 = IC/10 the precise level of I2 can be calculated as I2 = VB/R2 and
this can be used in the equation for R1.
Selection of bypass capacitor, CE
Basically the capacitor values are calculated at the lowest signal frequency that the
circuit is required to amplify. This frequency is the lower cut-off frequency, fL.

Choose hie
XCE  at fL for CE calculation to give the smallest value for the bypass
1 hfe
capacitor.
Selection of coupling capacitors, C1 and C2
The coupling capacitors C1 and C2 should have a negligible effect on the frequency
response of the circuit. To minimize the effects of C 1 and C2, the reactance of each coupling
capacitor is selected to be approximately equal to one-tenth of the impedance in series with it
at the lowest operating frequency of the circuit (fL).

X C1
Zi rs
 10
X C3 Z R
O L
 10
Usually, RL>> ZO and often Zi>> rS, so that ZO and rS can be omitted in the above equations.

1.6 DESIGNPROBLEM

(i) Design a single stage CE transistor amplifier using BC107 transistor with Vcc =
15V,VCEQ = 5V, VE = 3V, RL = 47Kand fL =100Hz.

(ii) Determine Zi, ZO, AV, Ai and AP for the CE circuit designed in problem(i).
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Procedure
Given VCC = 15V, VCE = 5V, VE = 3V, RL = 47kand fL = 100Hz.
The data sheet of BC107 transistor shows:
hie = 3kand hFE=190
Selection of RC
RC<< RL so that RL will have little effect on the circuit voltage gain.
RL
R
Select C  47K 4.7K (Standard value)
 10
10
Selection of RE

R
 V
E V  E
IC
E
I
E

Where IC
VRC VCC VCE  V (15 5 3)V 4.7K
  E   1.4mA
RC RC

RE
3V 2.14KΩ (use a standard 2.2 k)
 1.4m
A
Selection of R1 and R2
Selection of voltage divider current I2 as IC/10 gives good bias stability and reasonably high
input resistance
Selecting R2 = 10 RE gives I2 = IC/10

i.e.
, R2 102K22K(standard value)

and I2 1.4mA
IC  140μA
 10 10
VCCVB 15 (VBEVE) 15 (0.7 5)
R    (use standard 68k)
1 I2 140μ4 140μ466.43KΩ

Selection of C1 and C2
The coupling capacitors C1 and C2 should have negligible effect on the frequency response of
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the circuit. So, the reactance of each coupling capacitor is selected to be approximately equal
to 1/10thof the impedance in series with it at the lowest operating frequency for the circuit.
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X C1 Zi R1 R 2 h ie
   68K 22K 3K 254
10 10 10

C1
1 1 6μF
 2ππ X  2π100254
L C1 (Standard value10µF)

XC2 47K 1
RL  4.7KΩ  C2  1 0.34μF
 10 10 2ππL XC2  2π1004.7K

(use a standard 0.47μf)

C1 = CCin Input Side
C2 = CC in Output Side
Selection ofCE

XCE h ie 3KΩ

1hfe  1190 15.71

 1
C E  2ππL XCE  1 101.36μF (use a standard 100μf)
2π10015.71
Neglect source resistance RS and feedback resistor Rf

Calculation of Zi, ZO, AV, Ai and AP

Input impedance, Zi = R1||R2|| hie = 68k||22k||3K
= 2.54KΩ
Output impedance, ZO = RC = 4.7k

A 190
Voltage gain, V (RC R L)  (4.7K 47K) 270.61
 3K
h

feh
ie

Current gain, A  hfeRCRB 190 4.7K (68K 22K) 37.23


i
(R  R L )(RC
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Power gain, AP = AV x Ai = 270.61 X 37.23 = 10K
1.6.1 Design Constraints
If IC> VCC/2(RE+RC) and VCE< VCC/2 is not satisfied, then thermal runaway will occur.

15V

4.7KΩ
68KΩ

0.33µF
6µF

47KΩ
22KΩ
100mV, 100µF
1KHz
2.2KΩ

Fig 1.6 Designed Circuit for CE

1.7 PROCEDURE
Transient and Frequency response curve measurements

a. Feed 100mV (peak-to-peak) sinusoidal signal at 1KHz frequency as the input signal
(Vs)to the CEcircuit.
b. Observe the input and output voltages simultaneously on a CRO. Note down the
amplitude, frequency and phase difference between the two voltages in thetable.
c. In the above assembled circuit, keep the magnitude of the source same, ie., 100mv and
vary the frequency from 50 Hz to 10 MHz and measure the voltage gain of the amplifier
ateach frequency across RL. Take atleast 10 readings and tabulate the reading in Table.
Ploton a semi log graph sheet the frequency response (voltage gain Vs frequency) curve
using the abovemeasurements.
d. From the plot, determine the values of (a) Mid band voltage gain, Av(mid), (b) Lower
Cut-off frequency,(c) upper cut-off frequency and (d)Bandwidth.
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1.8 TABULATION
TransientAnalysis
Amplitude Frequency Phase difference
Input signal 100 mV 1kHz 180

Output signal 11 V 1kHz

(a)
FrequencyResponse Vi = 50mV

Output Voltage (Vo) Gain in db

Frequency (Hz) Gain (Av)
(V) Av = 20 log(Vo/Vi)
42.706 V 42.706 V 32.6
20.765 Hz

40.530 Hz 82.176 V 82.176 V 38.2

60.409 Hz 117.118 V 117.118 V 41.3

80.832 Hz 143.00 V 143.00 V 43.10

100.294 Hz 153.383 V 153.383 V 43.7

(b)
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1.9 PRELABQUESTIONS
1. DefineBiasing.
2. Identify the type of biasing circuit used in the amplifier and justify its selection over
other biasingcircuits.
3. How the bypass and coupling capacitances affect the low frequency response of the
amplifier?
4. What are the different h-parameters of CEamplifier.
5. What are the main applications of CEamplifier.

1.10 POSTLABQUESTIONS

1. How do coupling capacitors C1 and C2 affect the frequency response?Why?

2. What is the effect on the amplifier performance of omittingRE?
3. What is the effect on input impedance of removing bypass capacitorCE?
4. (a) What is the phase relationship between the input and output signals of aCEamplifier?
(b) Was this relationship confirmed by the results of your experiments? Explain how.
5. Is the output impedance of a Common emitter amplifier a fixed quantity? Confirm
youranswer by referring specifically to any substantiating data in thisexperiment.
6. From a measurement of the rise time of the output pulse of an amplifier, whose input is
asmall amplitude square wave, one canestimatethe parameter of theamplifier.
7. What is the effect found whenVCE>VCC/2?
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1.11 RESULT
a. The phase difference between the input and output voltage waveform is 180 degrees.

b. The Mid-band voltage gain=46.13dB

c. The Lower cutoff frequency=82.750 Hz

d. The Upper cutoff frequency=6.48 MHz

e. Bandwidth =6.48 MHz-82.013 Hz=6.48 MHz