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Raising a new Generation of Leaders

EIE411:
COMPUTER ORGANIZATION
AND ARCHITECTURE
Module Topic: Instruction Set Architecture
(Part II)
Module Lecturer: Dr. Joke Badejo
MODULE TOPIC: INSTRUCTION SET ARCHITECTURE
§ Introduction
§ Instruction Formats
§ Design Decisions for Instruction Sets; Internal Storage in the CPU: Stacks Versus
Registers; Number of Operands and Instruction Length; Little Versus Big Endian
§ Instruction Types
§ Data Movement; Arithmetic Operations; Boolean Logic Instructions; Bit
Manipulation Instructions; Input/Output Instructions; Instructions for Transfer of
Control
§ Operand/Data Types
§ Addressing
§ Address Modes

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OPERAND (OR DATA) TYPES

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 TYPES OF OPERAND (OR DATA TYPES)
§ Addresses
§ Numbers
§ Integer/floating point
§ Characters
§ ASCII etc.
§ Logical Data
§ Bits or flags
§ Machine instructions operate on data.

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 NUMBERS
§ All machine languages include numeric data types
§ Numbers stored in a computer are limited:
§ Limit to the magnitude of numbers representable on a machine
§ In the case of floating-point numbers, a limit to their precision
§ Three types of numerical data are common in computers:
§ Binary integer or binary fixed point
§ Binary floating point
§ Decimal
§ Packed decimal
§ Each decimal digit is represented by a 4-bit code with two digits stored per
byte
§ To form numbers 4-bit codes are strung together, usually in multiples of 8 bits
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CHARACTERS
§ A common form of data is text or character strings
§ Textual data in character form cannot be easily stored or
transmitted by data processing and communications systems
because they are designed for binary data
§ Most commonly used character code is the International
Reference Alphabet (IRA)
§ Referred to in the United States as the American Standard Code
for Information Interchange (ASCII)
§ Another
code used to encode characters is the Extended Binary
Coded Decimal Interchange Code (EBCDIC)
§ EBCDIC is used on IBM mainframes
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LOGICAL DATA
§ An n-bit unit consisting of n 1-bit items of data, each item
having the value 0 or 1
§ Two advantages to bit-oriented view:
§ Memory can be used most efficiently for storing an array of
Boolean or binary data items in which each item can take on
only the values 1 (true) and 0 (false)
§ To manipulate the bits of a data item
§ If floating-point operations are implemented in software, we need to be
able to shift significant bits in some operations
§ To convert from IRA to packed decimal, we need to extract the rightmost
4 bits of each byte
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INTEL X86 DATA TYPES
§ 8-bit byte, 16-bit word, 32-bit double word, 64-bit quad word, 128-bit
double quad word
§ Addressing is by 8-bit or byte unit.
§ Words do not need to align at even-numbered address
§ The x86 uses the little-endian style; that is, the least significant byte is
stored in the lowest address.
§ Majority of implementations provide floating-point hardware
§ Optional floating-point coprocessor for single- and double-
precision IEEE 754 floating point data types

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ARM DATA TYPES
§ 8 (byte), 16 (halfword), 32 (word) bits
§ Halfword and word accesses should be word aligned
§ Unsigned integer interpretation supported for all types
§ Two’s-complement signed integer interpretation supported for all
types
§ Majority of implementations do not provide floating-point hardware
§ Floating-point arithmetic implemented in software
§ Saves power and area
§ Optional floating-point coprocessor for single- and double-precision
IEEE 754 floating point data types
§ ARM defines which endian to load and store data with its E-bit signal.

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 X86 SINGLE-INSTRUCTION, MULTIPLE-DATA (SIMD)
INSTRUCTIONS
§ 1996 Intel introduced MMX technology into its Pentium product line
§ MMX is a set of highly optimized instructions for multimedia tasks
§ Video and audio data are typically composed of large arrays of small
data types
§ Three new data types are defined in MMX
§ Packed byte
§ Packed word
§ Packed doubleword
§ Each data type is 64 bits in length and consists of multiple smaller data
fields, each of which holds a fixed-point integer

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SINGLE-INSTRUCTION-MULTIPLE-DATA (SIMD) DATA TYPES
§ Introduced to the x86 architecture as part of the extensions of the instruction
set to optimize performance of multimedia applications
§ These extensions include MMX (multimedia extensions) and SSE (streaming
SIMD extensions)
§ Data types:
§ Packed byte and packed byte integer
§ Packed word and packed word integer
§ Packed doubleword and packed doubleword integer
§ Packed quadword and packed quadword integer
§ Packed single-precision floating-point and packed double-precision
floating-point
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ADDRESSING

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ADDRESSING MODES
§ Refers to operand reference techniques
§ An operand reference in an instruction either contains
§ the actual value of the operand (immediate) or
§ a reference to the address of the operand.
§ The effective address (EA) of an operand is refers to the actual location of the
operand.
§ In a system without virtual memory, the effective address will be either a main
memory address or a register.
§ In a virtual memory system, the effective address is a virtual address or a
register.
§ The actual mapping to a physical address is a function of the memory
management unit (MMU) and is invisible to the programmer.
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ADDRESSING MODES
a) Immediate
b) Direct
c) Indirect
d) Register
e) Register Indirect
f) Displacement
g) Stack

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IMMEDIATE ADDRESSING
§ Simplest form of addressing
§ Operand = A
§ This mode can be used to define and use constants or set initial
values of variables
§ Typically the number will be stored in twos complement form
§ The leftmost bit of the operand field is used as a sign bit
§ Advantage:
§ No memory reference other than the instruction fetch is
required to obtain the operand, thus saving one memory or
cache cycle in the instruction cycle
§ Disadvantage:
§ The size of the number is restricted to the size of the address
field, which might be small compared with the word length
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IMMEDIATE ADDRESSING
§ Operand is part of instruction
Instruction
§ Operand = address field
Opcode Operand
§ e.g. ADD 5
§ Add 5 to contents of accumulator
§ 5 is operand

§ No memory reference to fetch data

§ Fast
§ Limited range

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DIRECT ADDRESSING
§ Address field contains address of operand
§ Effective address (EA) = address field (A) Instruction

§ e.g. ADD A Opcode Address A

§ Add contents of cell A to accumulator Memory

§ Look in memory at address A for operand

§ Was common in earlier generations of
computers
§ Requires only one memory reference and no Operand
special calculation
§ Limitation is that it provides only a limited
address space

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INDIRECT ADDRESSING
§ Reference to the address of a word in memory which
contains a full-length address of the operand Instruction

§ EA = (A) Opcode Address A

Memory
§ Parentheses are to be interpreted as “contents of”
Pointer to
operand
§ Advantage:
§ For a word length of N an address space of 2N is available
§Disadvantage: Operand
§ Instruction execution requires two memory references to
fetch the operand
§ May be nested, multilevel or cascaded but rarely used
multilevel or cascaded indirect addressing
i.e. EA = (((A)))
§ Disadvantage is that three or more memory references
could be required to fetch an operand, thus slower
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REGISTER ADDRESSING
§ Address field refers to a register rather
than a main memory address Instruction
§ EA = R
Opcode Register Address R
§ Advantages: Registers

§ Only a small address field is needed

in the instruction; shorter instructions
and faster instruction fetch
§ No time-consuming memory Operand

references are required

§ Disadvantage:
§ The address space is very limited

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REGISTER INDIRECT ADDRESSING
§ Analogous to indirect addressing Instruction

§ The only difference is whether the Opcode Register Address R

address field refers to a memory Memory
location or a register
Registers
§ EA = (R)
§ Address space limitation of the
address field is overcome by having Pointer to
Operand
that field refer to a word-length Operand

location containing an address

§ Uses one less memory reference
than indirect addressing
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DISPLACEMENT ADDRESSING
§ Combines the capabilities of direct
addressing and register indirect addressing Instruction
i.e. EA = A + (R)
Opcode Register R Address A
§ Requires that the instruction have two
Memory
address fields, at least one of which is
explicit Registers
§ The value contained in one address field
(value = A) is used directly
§ The other address field refers to a register Pointer to
whose contents are added to A to produce Operand + Operand
the effective address
§ Most common uses:
§ Relative addressing
§ Base-register addressing
§ Indexing 21
RELATIVE ADDRESSING
§ A version of displacement addressing
§ R = PC (Program counter)
§ EA = A + (PC)
§ i.e. get operand from A memory cells from current location
pointed to by PC

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BASE-REGISTER (OR BASED) ADDRESSING
§ A holds displacement
§ R holds pointer to base address
§ R may be explicit or implicit
§ e.g. segment registers in 80x86
§ Convenient means of implementing segmentation
§ In
some implementations, a single segment base register is
employed and is used implicitly
§ In
others, the programmer may choose a register to hold the base
address of a segment and the instruction must reference it
explicitly
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INDEXED ADDRESSING
§ Themethod of calculating the EA is the same as for base-register
addressing
§ An important use is to provide an efficient mechanism for
performing iterative operations
§ An index register (either explicitly or implicitly designated) is
used to store an offset (or displacement), which is added to the
operand, resulting in the effective address of the data.
§ For example, if the operand X of the instruction Load X is to be addressed
using indexed addressing, the EA of the operand is actually X+1
§ -- if R1 = 1(the index register).

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 STACK ADDRESSING
§ A stack is a linear array of locations
§ Sometimes referred to as a pushdown list or last-in-first-out queue
§ A stack is a reserved block of locations
§ Items are appended to the top of the stack so that the block is partially
filled
§ A pointer is associated with the stack
§ the value of the pointer is the address of the top of the stack
§ The stack pointer is maintained in a register
§ Thus references to stack locations in memory are register indirect
addresses
§ Stack addressing is a form of implied addressing
§ The machine instructions need not include a memory reference but
implicitly operate on the top of the stack
§ Operand is (implicitly) on top of stack
§ e.g. ADD --Pop top two items from stack and add
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 ADDRESSING MODES
- SUMMARY
§ A = contents of an
address field in the
instruction
§ R = contents of an
address field in the
instruction that refers to
a register
§ EA = actual (effective)
address of the location
containing the
referenced operand
§ (X) = contents of
memory location X or
register X

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BASIC ADDRESSING MODES - SUMMARY

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EXERCISE 1
An address field in an instruction contains decimal value 14. Where
is the corresponding operand located for
a) immediate addressing?
b) direct addressing?
c) indirect addressing?
d) register addressing?
e) register indirect addressing?

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REFERENCES
§ William Stallings. Computer Organization and Architecture.
10th Edition, Prentice Hall Upper Saddle River, NJ 07458. 2016
§ Chapter 12 : Instruction Sets: Characteristics and Functions
§ Chapter 13 : Instruction Sets: Addressing Modes and
Formats

§ Linda Null and Julia Lobur. The Essentials of Computer

Organization and Architecture. 4th Edition, Jones & Bartlett
Learning. 2015
§ Chapter 5: A Closer Look at Instruction Set Architectures
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MORE PRACTICE EXAMPLES
AND QUESTIONS

61
APPENDIX

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LA = linear address
(X) = contents of X
SR
PC
=
=
segment register
program counter
x86
A
R
=
=
contents of an address field in the instruction
register
ADDRESSING
B = base register MODES
I = index register
S = scaling factor 31
 x86 INSTRUCTION FORMAT
0 or 1 0 or 1 0 or 1 0 or 1
bytes bytes bytes bytes § Variations can be provided efficiently and
Instruction Segment
Operand Address compactly, variable-length instruction
size size
prefix override
override override § Increases the complexity of the processor

0 or 1 0 or 1
0, 1, 2, 3, or 4 bytes 1, 2, or 3 bytes bytes bytes 0, 1, 2, or 4 bytes 0, 1, 2, or 4 bytes

Instruction prefixes Opcode ModR/m SIB Displacement Immediate

Mod Reg/Opcode R/M Scale Index Base

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
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 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
data processing
immediate shift cond 0 0 0 opcode S Rn Rd shift amount shift 0 Rm
data processing
register shift cond 0 0 0 opcode S Rn Rd Rs 0 shift 1 Rm
data processing
cond 0 0 1 opcode S Rn Rd rotate immediate
immediate
ARM
load/store
immediate offset cond 0 1 0 P U B W L Rn Rd immediate INSTRUCTION
load/store
register offset cond 0 1 1 P U B W L Rn Rd shift amount shift 0 Rm FORMAT
load/store • All instructions
multiple cond 1 0 0 P U S W L Rn register list in the ARM
branch/branch
cond 1 0 1 L 24-bit offset
architecture are
with link
32 bits long
and follow a
regular format.
S = For data processing instructions, signifies that B = Distinguishes between an unsigned • Fixed-length
the instruction updates the condition codes byte (B==1) and a word (B==0) access
S = For load/store multiple instructions, signifies L = For load/store instructions, distinguishes
instruction
whether instruction execution is restricted to between a Load (L==1) and a Store (L==0)
supervisor mode L = For branch instructions, determines whether
P, U, W = bits that distinguish among a return address is stored in the link register
different types of addressing_mode 33
X86 OPERATION TYPES
§ The x86 provides a complex array of operation types including a
number of specialized instructions – CISC machine
§ The intent was to provide tools for the compiler writer to produce
optimized machine language translation of high-level language
programs
§ When a new procedure is called the following must be performed
upon entry to the new procedure:
§ Push the return point on the stack
§ Push the current frame pointer on the stack
§ Copy the stack pointer as the new value of the frame pointer
§ Adjust the stack pointer to allocate a frame

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ARM OPERATION TYPES
§ Load and store instructions
§ Branch instructions
§ Data-processing instructions
§ Multiply instructions
§ Parallel addition and subtraction instructions
§ Extend instructions
§ Status register access instructions

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X86 DATA
TYPES

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 Byte unsigned integer
7 0

Word unsigned integer

15 0

Doubleword unsigned integer

31 0

Quadword unsigned integer

63 0
sign bit
twos comp
Byte signed integer
7 0
(twos complement)

X86 NUMERIC
sign bit
Word signed integer
15 0
(twos complement)

DATA FORMATS
sign bit
Doubleword signed integer
31 0
(twos complement)
sign bit
Quadward usigned integer
63 0
(twos complement)t
sign bit
exp signif.
Half precision
15 9 0
floating point
sign bit
exp significand
Single precision
31 22 0
floating point
sign bit
exp significand
Double precision
63 51 0
floating point

sign bit integer bit

exponent significand
Double extended precision
floating point
79 63 0

Figure 12.4 x86 Numeric Data Formats 37

ARM ENDIAN SUPPORT

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THUMB-2 INSTRUCTION SET
§ The only instruction set available on the Cortex-M microcontroller
products
§ Is a major enhancement to the Thumb instruction set architecture (ISA)
§ Introduces 32-bit instructions that can be intermixed freely with the older 16-bit
Thumb instructions
§ Most 32-bit Thumb instructions are unconditional, whereas almost all ARM
instructions can be conditional
§ Introduces a new If-Then (IT) instruction that delivers much of the functionality of
the condition field in ARM instructions
§ Delivers overall code density comparable with Thumb, together with
the performance levels associated with the ARM ISA
§ Before Thumb-2 developers had to choose between Thumb for size
and ARM for performance
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