BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI

WORK-INTEGRATED LEARNING PROGRAMMES DIVISION

BITS BITS-WIPRO Collaborative Programme:
M. Tech in Software Systems(WASE)
& M Tech in Computing Systems & Infrastructure(WIMS)
Second Semester 2020 - 21
COURSE HANDOUT

Course Title
SSWT ZC263/ CSIW ZC263: Digital Electronics & Microprocessors

Course Description
Binary logic gates; logic circuits; Boolean algebra and function minimization; number systems and
codes; arithmetic logic units; flip-flops; registers and counters; introduction to microprocessors;
microprocessor architecture; addressing modes, instruction set and assembly language
programming; memory and I/O interfacing; system design example

Course Objective

No Course Objective

CO1 The course aims at understanding the fundamentals of Digital electronics (Building
Blocks of digital systems, Boolean algebra etc).

CO2 Understand Digital System Design ( combinational and sequential circuits ) and
understand its practical application in day to day life.

CO3 Learn the basic microprocessor Architecture, Instruction set, programming, interfacing
memory and IO which will enable students to design a microprocessor based systems for
different applications.

Text Books

T1 Mano, M. Morris, Michael D. Ciletti, Digital Design, Pearson Education, 4th Ed., 2008.

T2 Barry B. Brey, The Intel Microprocessors, Architecture, Programming and Interfacing, Pearson
Education, 8th Ed., 2009

Reference Books

R1 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture
R2 A. Saha and N. Manna, Digital Principles and Logic Design
R3 Douglas V Hall, Microprocessors and Interfacing, McGraw-Hill, revised second edition.2006
Learning Outcomes:

No Learning Outcomes

LO1 Basic Understanding of the Digital system and Design of the digital systems.

LO2 Design of the combinational and sequential circuits and its applications.

LO3 Architecture of the microprocessors, Interface of various types of memory, I/O devices
and design of various microprocessor based applications.

Legend
M = Module, RL = Recorded Lecture, CS = Contact Session, LE = Lab Exercises, SS = Self Study,
HW = Home Work Problems

Module Summary

No Title of the Module

M1 Boolean algebra, logic gates , canonical representations, Boolean function minimization
M2 Combinational Logic (Arithmetic circuits (binary adder-subtractor), BCD adder, Decoders,
Encoders, Multiplexers, De-Multiplexers)
M3 Sequential Logic building blocks (latches and flip-flops, characteristic and excitation tables,
state equations, analysis of sequential circuits)
M4 Registers & Counters (parallel and serial data transfer, universal shift register, ripple and
synchronous counter)
M5 Microprocessor Architecture (Programmers Register Set of Intel x86 Processor, address/data
buses and memory segmentation)
M6 Addressing Modes & Data Movement Instructions (data and program memory addressing
modes, instructions involved in movement of data)
M7 Assembly language Programming (Data movement instructions, Arithmetic and Logic
instructions, instructions for data strings, introduction to the assembler and assembly language
programming)
M8 Interrupts & Programme Control Instructions (Interrupt instructions, vectors and control,
conditional and unconditional program control instructions, subroutines)
M9 Memory Design (Memory devices, interface of RAM and ROM to 8086, decoding logic, odd
and even addressing)

M10 I/O Interfacing & System Design (isolated vs memory-mapped I/O, port decoding, building a
complete microprocessor based system)
Detailed Structure

M1: Boolean algebra, logic gates and canonical representations.

Learning Objectives: Introduction to digital systems; logic gates; Binary codes; Boolean functions and
canonical forms of representation; minimization using k- Maps.

Type Description/Plan/Reference
RL1.1 Introduction to Digital systems, Canonical forms: Sum Of Products & Product Of Sums
representations, Maxterms&Minterms.
RL1.2 Minimization using k-MAP : Minimal Sum of Products expression, Three variable &
Four variable functions
CS1.1 Quick recap of the topics of the recorded lecture by the Instructor (20 Minutes).
 Examples (From T1): Ex: 2.18; introduce the concept of Compliments and
compare between two forms of representations using example 2.19,.
 Examples (From T1): Ex: 3.5(a); 3.9(a);: Introduce POS Implementation and
use of don’t cares ex: 3.13(b), 3.23.
SS1.1 Self Study Number Systems and Codes. Chapter 1 T1. Basic laws of Boolean algebra 2.4;
2.5 from T1.( This should be announced in LMS in the beginning asking them to
come prepared before this contact class)
HW1.1 Assign problems as Home Work : Ex: 3.16; 3.23; 3.24;

M2: Combinational Logic:

Learning Objectives: (Arithmetic circuits (binary adder-subtractor), BCD adder, Decoders, Encoders,
Multiplexers, De-Multiplexers)

RL2.1 Arithmetic circuits (Half adder/Half Subtractor, Binary adder, Multiplier)

RL 2.2 Decoders: What is a Decoder, Decoder using gates, Modular design, Decoder
Applications.
RL 2.3 Encoders: What is an Encoder, Priority Encoder, Application of Encoder
RL 2.4 Multiplexer: 2:1 Multiplexer, Building Larger Multiplexers, Multiplexer Applications
RL 2.5 DeMultiplexer: Building a Demultiplexer, Applications of Demultiplexers
CS2.1 Arithmetic Circuits: Quick recap of the topics of the recorded lecture RL2.1 by the
Instructor (15 Minutes).
 Topic 4.6: BCD adder design, (Book T1)
 Topic 4.8 Magnitude Comparator.(Book T1)

CS2.2 Combinational MSI Blocks: Recap of what is given in recorded lecture RL2.2, RL2.3,
RL2.4 & RL2.5 (20 Minutes),
 Exercise 4.30: Combinational circuit design using Decoder: (Book T1)
 Exercise 4.33: Multiplexer Modular design Exercise 4.33: (Book T1)
 Exercise 4.34 Combinational circuit design using Multiplexer (Book T1)

SS2.1 Ripple carry adder and what are its speed limitations and how look ahead carry adder
improves the speed. Design of a 4 bit binary Multiplier
HW2.1 Assign problems as Home Work :ex: 4.7; 4.10; 4.27; 4.37.
Lab Verify the working of Ripple carry adder using multisim
work

M3&M4: Sequential Logic Building blocks, Registers & Counters

Learning Objectives: (Latches and flip-flops, characteristic and excitation tables, state equations, analysis
of sequential circuits, functional description of registers & Counters)

RL 3.1 Latches & Flip flops: SR Latch, D latches: D, JK and T Flip-flops.

RL 3.2 Design of a sequential circuit using D FF: Sequence Detector example.
RL 4.1 Registers: Design of N-bit register using D FFs, Design of Shit Register; universal Shift
Register
RL 4.2 Counters: Ripple counters; Synchronous counters
CS3.1 Latches & Flip flops. Quick recap of the topics of the recorded lecture RL3.1&3.2 by
the Instructor (15 Minutes).
 Section 5.5: Analysis of clocked sequential circuits. (Book t1)
 Exercise Problems: 5.7; 5.10 (Book T1)
CS3.2 Registers & Counters. Quick recap of the topics of the recorded lecture RL4.1&4.2 by
the Instructor (15 Minutes).
 Exercise Problem 6.7, 6,17 (Book T1)
SS3.1  State reduction : Section 5.7, Ring counter; twisted ring counter (Book T1)
HW3.1 Assign problems as Home Work :ex: 5.16;,6.6; 6.14.

M5: Microprocessor Architecture:

Learning Objectives: (Programmers Register Set of Intel x86 Processor, address/data buses and memory
segmentation)
RL 5.1 Architecture of x86 CPU: Internal functional blocks of x86 CPU; Programmers Register
set; Flag Registers.
RL5.2 Address Data bus Multiplexing: Odd and Even Memory banks. Address data
Demultiplexing using Latch.
CS4 Architecture of x86 CPU Quick recap of the topics of the recorded lecture RL4.1 & 4.2
by the Instructor (20 Minutes).
 Section 2.1 (Book T2) Programmers model of x86 CPU
 Section 2.2 (Book T2) Memory segmentation: Different segments of Memory and
their functions.
 Exercise Problems: Chapter 2 (14; 20) Book T2

MID Semester Examination. Syllabus used for the First 4 Sessions.

M6: Addressing Modes & Data Movement Instructions

Learning Objectives: (data and program memory addressing modes, Data Transfer Instructions and
Programming examples)
Type Description/Plan/Reference
RL6.1 Introduction to data addressing modes
Rl6.2 Introduction to memory addressing modes, form assembly language statements using
data movement instructions
RL7.1 Introduction to data movement instructions involving data strings.
CS5 Quick recap of the topics of the recorded lecture by the Instructor (20 Minutes).
 Examples (From T2): Ex: 3.6, 3.8, 3.9, 3.10. Introduction to data addressing
modes using assembly language statements
 Examples (From T2): Ex: 3.14, 3.15: Introduction to program memory
addressing modes using JMP, CALL instructions and stack memory.
 Examples (From T2): Ex: 4.3, 4.4, 4.11. Introduction to data movement
instructions along with data strings transfer.
SS5.1 Self Study of Scaled Index Addressing and relative addressing, pages 98-99 of T2.
HW5.1 Assign problems as Home Work : Chapter 3 (22, 29, 33, 39);

M7:Assembly language Programming

Learning Objectives: (Arithmetic and Logic instructions, instructions for data strings, introduction to the
assembler and assembly language programming, Interrupt instructions, vectors and control, conditional and
unconditional program control instructions, subroutines)

Type Description/Plan/Reference
RL 7.2 Introduction to arithmetic instructions using assembler
RL 7.3 Introduction to Logical Instructions
RL8.1 Introduction to program control instructions (un-conditional/conditional jump
instructions).
RL 8.2 Introduction to program control instructions (procedures/macro) and interrupt instruction
CS6.1  Examples (From T2): Ex: 5.13, 5.17, 5.21. Introduction to arithmetic
instructions (contd..).
 Examples (From T2): Ex: 6.1, 6.2, Introduction to jump instructions
 Examples (From T2): Ex: 6.14, 6.15, 6.16, 6.17 Introduction to procedures.
SS6.1 Self Study of BCD and ASCII arithmetic instructions, Sec 5-3, pages 172-175 of T2.
HW6.1  Assign problems as Home Work : Chapter 4 (25, 27, 43); Chapter 5 (26, 32,
44, 48) Examples (From T2): Ex: 6.18. Introduction to Interrupts.

M9: Memory Interfacing

Learning Objectives: (Memory devices, interface of RAM and ROM to 8086, address decoding logic, odd
and even addressing)
Type Description/Plan/Reference
RL9.1 Memory Address Space, Interfacing memory with odd and even banks, Memory internal
blocks
RL 9.2 Address decoding logic; Memory fold back, variable size memory interfacing, ROM and
RAM address space.
CS7 Quick recap of the topics of the recorded lecture by the Instructor (20 Minutes).
(While some Problem numbers are given these are broad guidelines and the Faculty
could pick some other similar examples)
 Memory read write Machine cycles;
 Section 10.2: Memory Address decoding (Book T2)
 Section 10.4: 8086 Memory interfacing (Book T2)

SS7.1 Timing diagrams of memory read & memory write cycles.

HW7.1 Memory interfacing design examples.

M10: I/O Interfacing

Learning Objectives: (isolated vs memory-mapped I/O, port decoding, building a complete microprocessor
based system)

Type Description/Plan/Reference
RL10.1 Interfacing input devices: Introduction I/O mapped I/O; key pad interfacing
RL 10.2 Interfacing Output devices: LED interfacing; seven segment display interfacing
RL 10.3 System Design example
CS8 Quick recap of the topics of the recorded lecture by the Instructor (20 Minutes).

 Section 10.2: I/O Port address decoding (Book T2)

 Interfacing A/D converter with 8086.
 Stepper Motor controller Interface
SS8.1 System Design example
CS 9 Review and recap of the

Comprehensive Examination. Syllabus Used for All 8 Sessions.

Course Plan: This plan is to use in conjunction with the modularized course structure

Sl No. Recorded Contact Session Self-study Home-work Lab Exercise

Lecture
1 RL 1.1 CS0 T1:sec1.3 T1:
1.4,2.4,2.5,2. Ex.,1.9,2.14
6,2.8
examples
 chap-1
2 RL 1.2 CS1.1, T1 Eg. from T1: Sec 3.2, T1: Ex .3.16,
chapter 2& 3 3.3, 3.5,3.7 3,24,3.28.
T1:Fig1.5,Ex1.13,1 R1-Ex-2.35
.14,1.33, 2.14
2.18,2.19,3.5(a),
3.9(a)
3.13b,3.23,R2-
Ex3.46
3 RL 2.1& No Session R2-Sec 5.2, R2-Ex 5.8,
RL 2.2 5.7,5.11 T1 Ex- 4.30,
T1sec 4.5, R1 2.38
4.9
R1sec2.8.2
4 RL 2.3, RL CS2.1 R2Ex 5.14, T1 Sec4.10, T1Ex4.33 R1
2.4 5,21 4.11, R2 Sec Ex-2.39,
RL 2.5 R1Ex2.36,2.39 5.9, 5.14, R2Ex5.17,
CS2.2 5.24, R2Ex
5.28,5.29
5 RL 3.1, No Session T1: Sec T1Ex:5.3,5,5
RL3.2 5,2,5.3.5.4 ,R2Ex 7.7.
6 RL 4.1, RL CS 3.1,R2Ex8.13 R2Sec7.14, R2Ex7.8,
4.2 CS 3.2, 7.15, T1 R2Ex8.9,
Section HW 3.1
5.7,6.2 R2
8.7, SS3.1
7 RL 5.1 No Session

8 RL 5.2 CS4 R2Chapter2 .

9 RL 6.1, RL No session T2,chap3Ex

6.2 28,32
10 RL 7.1 CS 5 SS5.1 HW 5.1

11 RL 7.2 and No session T2 Section T2,chap5Ex

RL 7.3 5.5,5.6 53,55
12 RL 8.1 CS 6.1 SS6.1 HW6.1
RL 8.2
13 RL 9.1 No session T2 Section T2,chap10
10.1, Ex 18,21
14 RL 9.2 CS7 SS7.1 HW7.1
 15 RL 10.1 & No session T2,chap11
RL 10.2 Ex 35,49
16 RL 10.3 CS8 SS8.1

17 CS 9

Syllabus for Comprehensive Exam (Open Book) All topics given in Plan

Experiential learning components

1. Lab Work(separate sheet is attached)

 Infrastructure Needed:

 Simulation software Multisim for Digital Electronics

 EMU8086 for Microprocessor

 Lab Sessions required: 5-6 sessions.

2. Work integration:Students can apply the learning to the work they are doing related to digital
design, use concept of combinational circuit in the Design for testability using MUX scan chain etc.
Students can relate the architecture of the Microprocessor they are using in their work and also
Applications of Microprocessor based system