Computer Organization & ARM Microcontrollers

B.E., V Semester, Electronics & Communication Engineering /

Telecommunication Engineering
[As per Choice Based Credit System (CBCS) scheme]

Subject Code 21EC52 CIE Marks 50

Number of Lecture 3:0:2:0 SEE Marks 50
Hours/Week (L:T:P:S)
Total Number of 40 hours Theory + 13 Lab slots Exam Hours 03
Lecture Hours
CREDITS – 04
Module-1, Basic Structure of Computers: Basic Operational Concepts, Bus Structures,
Performance – Processor Clock, Basic Performance Equation, Clock Rate, Performance
Measurement.
Text Book 1: Chapter 1 – 1.3, 1.4, 1.6 (1.6.1-1.6.4, 1.6.7), Chapter 2 – 2.2 to 2.10
Input/Output Organization: Accessing I/O Devices, Interrupts – Interrupt Hardware,
Direct Memory Access, Buses, Interface Circuits, Standard I/O Interfaces – PCI Bus,
SCSI Bus, USB.
Text Book 1: Chapter 4 – 4.1, 4.2, 4.4, 4.5, 4.6, 4.7

Module-2, Memory System: Basic Concepts, Semiconductor RAM Memories, Read Only
Memories, Speed, Size, and Cost, Cache Memories – Mapping Functions, Replacement
Algorithms, Performance Considerations.
Text book 1: Chapter 5 – 5.1 to 5.4, 5.5 (5.5.1, 5.5.2), 5.6
Basic Processing Unit: Some Fundamental Concepts, Execution of a Complete
Instruction, Multiple Bus Organization, Hard-wired Control, Micro programmed Control.
Basic concepts of pipelining,
Text book 1: Chapter7, Chapter 8 – 8.1

Module-3, ARM Embedded Systems: Introduction, RISC design philosophy, ARM

design philosophy, Embedded system hardware – AMBA bus protocol, ARM bus
technology, Memory, Peripherals, Embedded system software – Initialization (BOOT)
code, Operating System, Applications. ARM Processor Fundamentals, ARM core dataflow
model, registers, current program status register, Pipeline, Exceptions, Interrupts and
Vector Table, Core extensions.
Text book 2: Chapter 1, 2

Module -4, Introduction to the ARM Instruction set: Introduction, Data processing
instructions, Load – Store instruction, Software interrupt instructions, Program status
register instructions, Loading constants, ARMv5E extensions, Conditional Execution.
Text book 2: Chapter 3

Module -5, Introduction to the THUMB instruction set: Introduction, THUMB register
usage, ARM – THUMB interworking, Other branch instructions, Data processing
instructions, Stack instructions, Software interrupt instructions.
Efficient C Programming: Overview of C Compilers and optimization, Basic C Data
types, C looping structures.
Text book 2: Chapter 4, 5

Text Book:
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Computer Organization, 5th Edition,
Tata McGraw Hill, 2002. (Listed topics only from Chapters 1, 2, 4, 5, 8).

2. Andrew N Sloss, Dominic System and Chris Wright, “ARM System Developers Guide”,
Elsevier, Morgan Kaufman publisher, 1st Edition, 2008.
Reference Books:
Question Bank….

Module - 3

1) Explain the architecture of ARM Cortex M3 processor with the help of a neat block diagram
2) Discuss the functions of R0 to R15 and other special purpose registers with a neat block
diagram of register organization
3) List the applications of ARM Cortex M3 processor
4) Explain the operation modes of Cortex M3 with diagrams
5) Explain Cortex M3 Program Status Register (PSR) format in detail
6) Describe basic set of guidelines applied while designing the ARM instruction set for
Embedded system design.
7) Describe in brief the hardware architecture of embedded system designed using ARM core
8) Describe in brief the software architecture of embedded system designed using ARM core
9) Describe dataflow model of ARM core
10) Describe CPSR of ARM core
11) Describe conditional execution in ARM core. NE, EQ, CC, LS, GE, AL
Module - 4

1) Describe Barrel shifter usage in ALU operations in ARM core design

2) Explain the operation of LSR and ASR with an example consider R0 = 0x8000 0000
3) Describe the operation of SBC and RSC with an example, list the contents of registers and
flags before and after the execution of this instruction.
4) Describe the operation of SBC and SUB with an example, list the contents of registers and
flags before and after the execution of this instruction.
5) Describe the operation of SBC and ADC with an example, list the contents of registers and
flags before and after the execution of this instruction.
6) Describe the operation of MUL and MLA with an example, list the contents of registers and
flags before and after the execution of this instruction.
7) Describe the operation of MUL and UMULL with an example, list the contents of registers
and flags before and after the execution of this instruction.
8) Describe the operation of SUB and CMP with an example, list the contents of registers and
flags before and after the execution of this instruction.
9) Describe the operation of SBC and ADC with an example, list the contents of registers and
flags before and after the execution of this instruction.
10) Describe the operation of AND and TST with an example, list the contents of registers and
flags before and after the execution of this instruction.
11) Describe the operation of EOR and TEQ with an example, list the contents of registers and
flags before and after the execution of this instruction.
12) Describe the operation of BX and BLX with an example, list the contents of registers and
flags before and after the execution of this instruction.
13) Describe the operation of MOV and MOVEQ with an example, list the contents of registers
and flags before and after the execution of this instruction.
14) Describe the operation of MOV and MOVEQ with an example, list the contents of registers
and flags before and after the execution of this instruction.
15) Describe the operation of MOVEQ and MOVEQS with an example, list the contents of
registers and flags before and after the execution of this instruction.
16) Describe the operation of pre-index, post-index, pre-index with writeback with an example,
list the contents of registers and flags before and after the execution of this instruction.
17) Describe the operation of LDM and STM with an example, list the contents of registers and
flags before and after the execution of this instruction.
18) Describe the operation of LDMIA, STMDB with an example, list the contents of registers
and flags before and after the execution of this instruction.
19) Describe the operation of LDMIB, STMDA with an example, list the contents of registers
and flags before and after the execution of this instruction.
20) Explain following instructions with example ASR, LSR, ROR, RRX, BIC,
21) Explain following instructions with example ADC, ORR, LDR, STR, MRS, MSR, POP,
PUSH
22) Write a program to find factorial of a number
23) Write a program to find the smallest / largest number in an array of numbers.
24) Write a program to add two 64 bit numbers
25)
Module - 5

1) Illustrate the ARM complier’s role in handling char / short variables

2) With an example prove that non-word sized variables lead to inefficient program execution
3) With an example prove that Thumb code provides better code density
4) With an example illustrate interworking between ARM and thumb code
5) Illustrate the following thumb instructions
a. ASR
b. LSL
c. LSR
6) Illustrate the following
a. LSR & ROR for given input data
b. SUB and CMP for a given data
7) Illustrate Stack instruction in thumb mode
8) Illustrate SWI instruction in thumb mode
9) Illustrate LDR and LDRB in thumb instructions
10) Illustrate STR and STRB in thumb instructions
11)
Module - 1

1) Describe he functional components of a processor

2) Describe the bus architecture in a processor
3) Describe the hardware - interrupt mechanism
4) Describe DMA
5) With suitable timing diagram, explain the synchronous bus operation for IO read operation
6) With suitable timing diagram, explain the synchronous bus operation for IO Write operation
7) With suitable timing diagram, explain the Asynchronous bus operation for IO read operation
8) With suitable timing diagram, explain the Asynchronous bus operation for IO Write
operation
9) Describe PCI bus architecture with suitable diagrams
10) Describe SCSI bus architecture
11) Describe USB bus architecture
12)
Module - 2

1) Explain the principle of operation of a CMOS based SRAM cell

2) Explain the principle of operation of a CMOS based DRAM cell
3) Design a Memory organization of 32M x 8 SRAM chip
4) Design a Memory organization of 16 x 8 SRAM chip
5) Describe Cache memory
6) Describe the operation of Direct mapping cache memory management
7) Describe the operation of Associative mapping cache memory management
8) Describe single-bus organization of Datapath within a processor
9) Illustrate ALU operation within a processor
10) Illustrate register transfer operation within a processor
11) Illustrate Memory read operation within a processor
12) Explain Multi-bus architecture of a processor
13) Explain Hardwired Control mechanism in processor design
14) Explain Microprogrammed Control mechanism in processor design
15) Explain the concept of pipelining… list out the advantages against non-pipelined processors
16)