Exercise 4 - Summer Semester 2019

July 2, 2019

This document is part of the laboratory for the exam ”Fundamentals of

IC Deign”. It is for students attending the same-named lecture organized by
the Institute for Integrated Circuits of the TUHH. All information is supplied
without liability.

During this laboratory the simulation software LTSpice by Analog Devices

will be used.
Institute for Integrated Circuits
Prof. Dr.-Ing. Matthias Kuhl

In the last exercise, the final operational amplifier has to be design in order to fulfill the
given specifications.

Task 4 Creating a Symbol

To simplify further schematics and to allow multiple instances of the same design to
be placed in higher hierarchy levels, a symbol for the operational amplifier has to be
created.
Before linking a symbol to the schematic place the transistors and compensation capacitor
for the output stage as in Fig. 1 (M15, M16, C1). Make sure that no voltage or current
sources are left in the schematic and create Input/Output pins for the following nodes:

1. Positive input V+
2. Negative input V−
3. Output voltage Vout
4. Supply voltage VDD

Figure 1: Schematic in LTSpice for which a symbol has to be created.

Next go to Hierarchy → Create a new Symbol. A new tab will appear in which the symbol
can be drawn as shown in Fig. 2.

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Institute for Integrated Circuits
Prof. Dr.-Ing. Matthias Kuhl

Figure 2: Example for a symbol drawing for the operational amplifier.

To link the schematic pins with the corresponding pins in the symbol, pin instances have
to be placed (Right click → AddP in). Make sure, the pin-names in your symbol match the
names in the schematic and that you create a pin for VDD (A ground pin is not necessary)
as shwon in Fig. 3.

Figure 3: Example for a symbol drawing for the operational amplifier with pins assigned.

After your symbol design is finished, safe it in the same folder as the schematic with the
same name.

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Institute for Integrated Circuits
Prof. Dr.-Ing. Matthias Kuhl

To create an instance of the amplifier open a new schematic in the same folder as the
symbol- and schematic file of your amplifier. By opening Edit → Component and changing
the top directory to the current work-directory, your amplifier appears in the list.

Task 5 Two Stage Amplifier Design

In this task, the testbenches for the simulations are explained as well as the final specifi-
cations that have to be reached by your design.

Task 5.1 Testbenches

After creating the symbol, multiple instances of your design can be placed in other
schematics in order to simulate different characteristics of the amplifier.

Task 5.1.1 Gain, Phase-Margin and Unity-Gain-Frequency

To simulate the Gain (A), Phase-Margin (PM) and the Unity-Gain-Frequency (UGF), a
testbench as shown in Fig. 4 has to be used. Due the low-pass filter in the feedback with
a pole at a very low frequency, only the common-mode voltage (VCM ) is fed back to the
negative input, hence the closed loop transfer function becomes the open loop transfer
function.

Figure 4: Testbench for Gain, PM and UGF.

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Institute for Integrated Circuits
Prof. Dr.-Ing. Matthias Kuhl

Set up your AC simulation to run in Decade mode from 10 Hz to 10 GHz with 100 points
per decade. The final specifications have to be fulfilled for any common mode within the
specified input common mode range. To get your phase margin, measure the phase at
your unity gain frequency to obtain

P M = −180◦ − φ(U GF ) (1)

Task 5.1.2 Slew Rate

The slew rate of an amplifier can be simulated by applying a voltage step at the input of
the OPAMP in unity gain configuration as in Fig.5.

Figure 5: Testbench for the Slew Rate.

To extract the slew rate, measure the slope of the output signal between 10 % and 90 %
of the signal amplitude (Fig. 6) for both the rising and falling edge.
For the simulation use a pulse from V0 = 1V to V1 = 2V with a pulse length of 1 µs.

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Figure 6: Slew rate simulation example.

Task 5.2 Specifications

Figure 7: Final two-stage amplifier.

In this task, you have to design you final amplifier with output stage and compensation
circuit as shown in Fig.7.

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The specifications for the final design are:

• CLoad = 10 pF
• Unity Gain Frequency (UGF) ≥ 3.5 MHz
• Open-Loop DC Gain (ADC ) ≥ 85 dB
• Phase-Margin ≥ 60◦
• Input-Swing = 1 V → VDD − 900 mV
• Slew Rate ≥ 4 V /µs
• Maximum Power Consumption including Beta Multiplier (Pmax ) ≤ 350 µW

To reach this specification you might have to change also the design of your differential
stage again, depending on your previous design. Using only the pole splitting technique is
enough to reach the given specifications. However, feel free to apply the lead compensation
technique to reach even better performance.
Hints:
• Start by thinking about how much current you can spend for the whole operational
amplifier to stay below the given Pmax
• Calculate the compensation capacitor CC , using the Unity Gain Frequency specifi-
cation. Therefor use the simplified equation

gm1 = ωUG ∗ CC (2)

with ωUG being the Unity Gain Angular Frequency.

• If the slew rate is not high enough, think about increasing the current in the output
or differential stage of your amplifier.
ISS
SR = (3)
C

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