(1604) Digital Circuits - Digital Electronics Topic Wise Test - 04

TARGATE EDUCATION
www.targate.org, bilaspur@targate.org
9300432128
Test Name : (1604) Digital Circuits / Digital Total Questions : 30

Electronics Topic Wise Test- 04
Difficulty Level : difficulty:medium Total Marks : 30.00
Test Type : Free Duration : 90.00 mins
Instruction :
General Instructions
Read the following instructions carefully
1. Total duration of the examination is 90 minutes. Calculator is available on top, right-hand side of
the screen.
2. The clock will be set at the server. The countdown timer at the top, right-hand side of the screen
will display the time available for you to complete the examination. When the timer reaches
zero, the examination will end automatically. You will not be required to end or submit your
examination.
The Question Palette displayed on the right-hand side of the screen will show the status of
each question using one of the following symbols:
This question has not been visited yet.
This question has been visited,but not answered.
This question has been answered and will be considered for evaluation.
This question has been marked for review and has not been answered.
This question has been answered and marked for review, which will be considered for
evaluation.
4. Click on , which appears to the left side of Question Palette to maximize the Question Area. To
view the Question Palette again, click on , which appears to the right side of Question Area.
5. Click on to navigate to the bottom and Click on to navigate to the top of the Question
Area, without scrolling.
Navigating to a Question:
6. Click on the question number in the Question Palette to go to that particular question directly.
7. You can view all the questions by clicking on the Question Paper button that appears at top,
right-hand side of the screen.
Page - 1/32
TARGATE EDUCATION
9300432128
Answering a Question :
8. Procedure for answering a multiple choice type question (MCQ) :

a. To select your answer, click on the button of the corresponding option.
b. To deselect your chosen answer, click on the button of the chosen option once again or click
on the Clear Response button.
c. To change your chosen answer, click on the button of the newly identified answer.
9. Procedure for answering a numerical answer type (NAT) question:
a. To enter a numerical answer, use the virtual numeric keypad that appears below the
question.
b. A fractional number in the decimal notation (e.g. -0.3 or -.3) can be entered as an answer
with or without '0' before the decimal point.
c. To clear your answer, click on the Clear Response button.
10. To change your answer to a question that has already been answered, first select that question
and then follow the usual procedure for answering any question.
Saving your answer :
11. To save your answer, you MUST click on the Save & Next button. To mark the question for
review, click on the Mark for Review & Next button.
12. After the elapse of time scheduled for the examination (90 minutes), all the answers (including
those “Answered and Marked for Review”) will be automatically submitted.
Navigating through sections:
13. Sections in this question paper are displayed above the Question Area. Questions in a section
can be viewed by clicking on the section name. The section you are currently viewing is
highlighted.
14. After clicking the Save & Next button on the last question of any section, you will automatically
be taken to the first question of the next section.
15. You can shuffle between sections and questions anytime during the examination.
16. You can see the section summary as a part of the legend appearing above the Question Palette of
every section.
Q.1
If the input clock frequency f = 1 MHz, then frequency at is _______(in
Page - 2/32
TARGATE EDUCATION
9300432128
MHz)
Answer : (0.025) to (0.225),
Solution :
Flip-flop toggles on the negative going transition of each input clock

pulse
Similarly all flip-flops toggle on the negative transition of clock.
Frequency at output of each flip flop is exactly half of the input

frequency
Q.2 A 5-bit modulo-32 ripple counter uses JK flip-flop. If the propagation

delay of each FF is 50 ns, the maximum clock frequency is ________(in
MHz)
A. 4
B. 5
C. 3
D. 2
Answer : A,
Solution :
Page - 3/32
TARGATE EDUCATION
9300432128
Today delay =
Q.3 The Flip-flop shown in below figure are positive edge triggered. Let the
initial state be 00. The state transition sequence is :
A.
B.
C.
D.
Answer : A,
Solution :
Here
Clk
1 - - 0 0
2 1 1 1 1
3 0 1 0 1
4 0 0 0 0
5 1 1 1 1
Page - 4/32
TARGATE EDUCATION
9300432128
Output sequence is
Q.4 The frequency of the pulse______(in Hz) at Z in the network shown in

figure is
Answer : (10.30) to (10.51),
Solution :
8-bit ring counter counts 8 states i.e. mod-8
4-bit parallel counter counts 16 states i.e. mod-16
Mod-20 ripple counter counts 20 states
3-bit Johnson counter 6 states i.e. mod-6
Q.5 An XY flip flop is constructed from an SR flip flop as shown in figure.

The expression for next state Q(t + 1) is
A. XY + XQ(t)
B. XY + YQ(t)
C. Both A & B
D. None
Page - 5/32
TARGATE EDUCATION
9300432128
Answer : C,
Solution :
By giving different sets of input values and Q(t) (present state) we have to
determine next state Q(t+1)
X Y Q(t) S R Q(t+1)
0 0 0 1 0 1
0 0 1 1 0 1
0 1 0 0 1 0
1 0 0 0 0 0
1 0 1 0 0 1
1 1 0 1 1
1 1 1 1 1
K-map for Q(t + 1)
or +
Q.6 Which of the following counter represents shown in below is
Page - 6/32
TARGATE EDUCATION
9300432128
A. MOD-2
B. MOD-3
C. MOD-4
D. None
Answer : B,
Solution :
;
Clock
0 -- 00
1 10 10
2 01 01
3 00 00
Q.7 Consider the following Flip-Flop
Values of A, B respectively are

A. A = J; B = K
B.
C.
D.
Page - 7/32
TARGATE EDUCATION
9300432128
Answer : C,
Solution :
) Input for D flip-flop
) output for D flip-flop
It represents JK Flip-flop output =
Hence B = J; A = K
Q.8 State diagram representation of the following sequential circuit is
A.
Page - 8/32
TARGATE EDUCATION
9300432128
B.
C.
D.
Page - 9/32
TARGATE EDUCATION
9300432128
Answer : D,
Solution :
Clock (LDB) Decimal
- 000 0
1 11 00 00 100 1
2 11 11 00 010 2
3 11 00 00 110 3
4 11 11 11 001 4
5 11 00 00 101 5
6 11 00 00 111 6
7 11 00 00 111 7
8 11 11 11 000 0
Counting sequence 0,1,2,3,4,5,6,7,0
Q.9 A flip-flop has a delay of 10 nsec from the time the clock edge applied
to the time the output is obtained. There is mod-10 ripple counter
that uses this type of flip-flops. The maximum delay in output is :
A. 100 nsec
B. 10.24
C. 40 nsec
Page - 10/32
TARGATE EDUCATION
9300432128
D. 33.21
Answer : C,
Solution :
number of flip-flops required = 4
maximum delay =
Q.10 In the following sequential circuit, the initial state (before the first clock
pulse) of the circuit is .
The state ( ), immediately after the 333rd clock pulse is
A. 00
B. 01
C. 10
D. 11
Answer : B,
Solution :
From the circuit we can find out that,
Present State Next State
1 0 0 1
Page - 11/32
TARGATE EDUCATION
9300432128
1 0 1 0
0 1 1 0
0 1 0 1
So, the state diagram is
At every 4n clock the system is at 00
So, at 332 it will be at 00
So, 333rd clock it will be at 01
Q.11 Consider the sequential circuit shown below. The total number of
different states followed by the circuit __________
Answer : 8,
Solution :
The given circuit is a 4 bit ripple counter. When (in the state 1000)
the output of EXOR gate is 0, and the counter resets to 0000
the counter counts 8 states from 0000 to 0111
Q.12 The following counter has _______ number of states.
Page - 12/32
TARGATE EDUCATION
9300432128
Answer : (2.8) to (3.2),
Solution :
So, the state diagram of the counter will be
it has 3 states
Q.13 Consider a mod-1000 ripple up counter. The duty cycle for its MSB is
________%.
Page - 13/32
TARGATE EDUCATION
9300432128
Answer : (48.70) to (48.90),
Solution :
Duty cycle of MSB
Q.14 A six bit shift register is initialized to a value of 100000. Minimum

number of clock pulses needed to produce 101101 form the initial value
is ______
Answer : (4.9) to (5.1),
Solution :
Let output of XNOR gate is Y
Page - 14/32
TARGATE EDUCATION
9300432128
Minimum five clock pulses are required to get the sequence 101101
Q.15 The input A and clock applied to the D flip-flop are shown in figure below.
The output is
Page - 15/32
TARGATE EDUCATION
9300432128
A.
B.
C.
D.
Answer : D,
Solution :
D flip-flop changes its output according to input and clock pulse applied to
it. The flip flop shown in figure is positive edge triggered so the output
modifies at every positive edge of clock according to the input.
Q.16 Consider the circuit given below
Page - 16/32
TARGATE EDUCATION
9300432128
If Enable = 0; 7
segment display 11(b = c = e = f = 1)Enable = 1; 7 segment display data
according to inputsInitially both the counter were cleared. After 78 clock
pulses the data displayed on the 7 segment display is _______.
Answer : (10.9) to (11.1),
Solution :
After 78 clock pulse
Output of counter
Output of counter
7 segment display
a b c d e f g Enable
11100010
Page - 17/32
TARGATE EDUCATION
9300432128
Data displayed on 7 segment is ‘11’
Q.17 A new two input flip flop is designed as shown in figure. The table shows
the characteristic table of the A – B flip flop.
A B
0 0
0 1 1
1 0
1 1 0
The combination logic is
A.
B.
C.
Page - 18/32
TARGATE EDUCATION
9300432128
D.
Answer : D,
Solution :
State table
A B J K
0 0 1 1
0 1 1 1 0
1 0 0 0
1 1 0 0 1
Page - 19/32
TARGATE EDUCATION
9300432128
Q.18 A 8 –bit register is made of one 4-bit PISO register (synchronous loading)
cascaded with a 4-bit SIPO register as shown in the figure below.
Total number of clock pulses required to perform write and read

operations for one byte is
A. 8
B. 10
C. 12
D. 14
Answer : B,
Solution :
Since loading is synchronous type, for every nibble to load one clock pulse
is needed
Number of Operation
Clock Pulses
1 LSB nibble written
4 LSB nibble read
1 MSB nibble written
4 MSB nibble read
Total clock pulses = 1 + 4 + 1 + 4
= 10
Page - 20/32
TARGATE EDUCATION
9300432128
Q.19 Consider the waveform given below :
The output can be obtained from the circuit

A.
B.
C.
D.
Page - 21/32
TARGATE EDUCATION
9300432128
Answer : C,
Solution :
By checking all the options
Option (c) correctly matches.
Assuming the initial value of counter output as zero, the counter
Page - 22/32
TARGATE EDUCATION
9300432128
output for 8 clock pulses in decimal form is

A. 0, 3, 2, 1, 0, 1, 2, 3
B. 0, 1, 2, 3, 2, 1, 0, 1
C. 0, 1, 2, 3, 3, 2, 1, 0
D. 0, 3, 2, 1, 0, 0, 1, 2
Answer : B,
Solution :
Initially
J – K flip-flop is cleared
As clock pulse is applied counter starts up counting
As counter reaches after 3 clock pulses J – K flip flop is preset
Counter starts down counting until is low and this repeats.
So, Output in decimal form is
0, 1, 2, 3, 2, 1, 0, 1......
The duty cycle of is

A. 20%
Page - 23/32
TARGATE EDUCATION
9300432128
B. 40%
C. 30%
D. 25%
Answer : C,
Solution :
Output of counter
0 0 0 0 0 1 0
0 0 0 1 1 1 0
0 0 1 0 1 1 0
0 0 1 1 0 1 0
0 1 0 0 0 0 0
0 1 0 1 1 0 1
0 1 1 0 1 0 1
0 1 1 1 0 0 0
1 0 0 0 0 0 0
1 0 0 1 1 0 1
Duty cycle
Q.22 Three 4-bit shift registers are connected in cascade as shown in figure
below. Each register is applied with
A4
–bit data 1011 is applied to the shift register 1. The minimum number of
clockpulses required to get same input data at output are with same
clock will be _________.
Answer : (11.8) to (12.2),
Solution :
Page - 24/32
TARGATE EDUCATION
9300432128
Minimum number of clock pulses required = 12
Q.23 Two counter circuits, counter-1 and counter-2 are shown below with
their clock frequencies as 80 kHz and 40 kHz respectively
If
Page - 25/32
TARGATE EDUCATION
9300432128
are frequencies at outputs respectively, then what is the value of

is__________
Answer : (0.8) to (1.2),
Solution :
Counter – 1 is a twisted ring counter
Counter-2 is a ring counter
Q.24 How long will it take to transfer an 8 bit data into a serial-in-parallel-out
shift register, if the clock frequency is 5 MHz?
A. 0.2
B. 1.6
C. 3.2
D. 5
Answer : B,
Solution :
Clock period
For SIPO, time taken to transfer data
Page - 26/32
TARGATE EDUCATION
9300432128
Q.25 Consider the partial 2 bit counter, following the sequence 0 -2 -3 -1 -0 as

shown below
To complete the circuit input X must be

A.
B.
C.
D.
(D)
Answer : D,
Solution :
The given sequence
For T flipflop, if input is ‘1’ the output is complemented

Present state Next state FF inputs
0 0 1 0 1 0
1 1 1 1 1 1
1 1 1 1
1
Page - 27/32
TARGATE EDUCATION
9300432128
Thus,
Q.26 Identify the state diagram of J-K flip-flop. Here the first input(J) is
represented by the MSB of input and the second input (K) is represented
by the LSB of input.
A.
B.
C.
D.
Answer : D,
Solution :
Page - 28/32
TARGATE EDUCATION
9300432128
Excitation table J-K flip flop
Q.27
A certain JK-FF has propagation delay . The largest MOD of the
counter such that, the counter can be designed from these FFs which will
operate upto 10 MHz will be ________.
Answer : (255.8) to (256.2),
Solution :
Clock period =
=100 nsec
So, number of required
Q.28 The number of clock pulses needed to change the contents of an 8-bit up-
counter from to is ____________.
Answer : (142.8) to (143.2),
Solution :
Page - 29/32
TARGATE EDUCATION
9300432128
Number of states for 8-bit up-counter
Thus the counter ranges from -0 to 255
Hence, to go from to
The counter has to go initially from 171 to 255 and then from 0 to 58.
Hence,
From 171 to 255 = 255 – 171 = 84 clock pulse required
From 255 to 0 = 1 clock pulse required
And from 0 to 58 = 58 clock pulse required
The total number of clock pulse required is
= 84 + 1 + 58
= 143
Alternatively
Total number of clock pulse required
Q.29 An 8-bit register is made of one 4-bit PISO register [synchronous

loading] cascaded with a 4-bit SIPO register as shown in the figure
below. Total number of

clock pulses required to perform write and read operations for one byte
is ______.
Page - 30/32
TARGATE EDUCATION
9300432128
Answer : (9.8) to (10.2),
Solution :
Since loading is synchronous type, for every nibble to load one clock pulse
is needed
Number of operation
Clock Pulses
1 LSB nibble written
4 LSB nibble read
1 MSB nibble written
4 MSB nibble read
Total clock pulses = 1 + 4 + 1 + 4
= 10
Q.30 An 8-bit register and D flip flop shown in figure below are synchronized
with same clock
Assuming the flip flop is initially cleared. The circuit act as a

A. Binary to 2’s compliment converter
B. Binary to Gray code converter
C. Binary to 1’s compliment converter
D. Binary to Excess-3 converter
Answer : B,
Solution :
Page - 31/32
TARGATE EDUCATION
9300432128
Initially the input at ‘D’ will be and the signal X is ‘0’
Therefore
For the next clock pulse
And
Similarly for every clock pulse each bit of register shows the Ex-OR
combination of binary inputs. Thus, the circuit represents the conversion
from binary to Gray code.
Page - 32/32

(1604) Digital Circuits - Digital Electronics Topic Wise Test - 04

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

(1604) Digital Circuits - Digital Electronics Topic Wise Test - 04

Uploaded by

Copyright:

Available Formats

TARGATE EDUCATION

Test Name : (1604) Digital Circuits / Digital Total Questions : 30

This question has not been visited yet.

This question has been visited,but not answered.

8. Procedure for answering a multiple choice type question (MCQ) :

Saving your answer :

Navigating through sections:

Flip-flop toggles on the negative going transition of each input clock

Similarly all flip-flops toggle on the negative transition of clock.

Frequency at output of each flip flop is exactly half of the input

Q.2 A 5-bit modulo-32 ripple counter uses JK flip-flop. If the propagation

Q.4 The frequency of the pulse______(in Hz) at Z in the network shown in

Answer : (10.30) to (10.51),

8-bit ring counter counts 8 states i.e. mod-8

4-bit parallel counter counts 16 states i.e. mod-16

Mod-20 ripple counter counts 20 states

3-bit Johnson counter 6 states i.e. mod-6

Q.5 An XY flip flop is constructed from an SR flip flop as shown in figure.

K-map for Q(t + 1)

Q.6 Which of the following counter represents shown in below is

Q.7 Consider the following Flip-Flop

Values of A, B respectively are

) Input for D flip-flop

) output for D flip-flop

It represents JK Flip-flop output =

Q.8 State diagram representation of the following sequential circuit is

Clock (LDB) Decimal

Counting sequence 0,1,2,3,4,5,6,7,0

number of flip-flops required = 4

From the circuit we can find out that,

Present State Next State

So, the state diagram is

At every 4n clock the system is at 00

So, at 332 it will be at 00

So, 333rd clock it will be at 01

the counter counts 8 states from 0000 to 0111

Q.12 The following counter has _______ number of states.

Answer : (2.8) to (3.2),

So, the state diagram of the counter will be

Answer : (48.70) to (48.90),

Duty cycle of MSB

Q.14 A six bit shift register is initialized to a value of 100000. Minimum

Let output of XNOR gate is Y

Q.16 Consider the circuit given below

After 78 clock pulse

Data displayed on 7 segment is ‘11’

Total number of clock pulses required to perform write and read

Total clock pulses = 1 + 4 + 1 + 4

Q.19 Consider the waveform given below :

The output can be obtained from the circuit

By checking all the options

Option (c) correctly matches.

Q.20 Consider the circuit given below

Assuming the initial value of counter output as zero, the counter

output for 8 clock pulses in decimal form is

As clock pulse is applied counter starts up counting

As counter reaches after 3 clock pulses J – K flip flop is preset

Counter starts down counting until is low and this repeats.

So, Output in decimal form is

Q.21 Consider the circuit given below

The duty cycle of is

Minimum number of clock pulses required = 12