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26 October - 20 November, 2009: Fpga Architectures & VHDL Introduction To Fpgas & Fpga Design Flow
26 October - 20 November, 2009: Fpga Architectures & VHDL Introduction To Fpgas & Fpga Design Flow
Nizar Abdallah
ACTEL Corp.2061 Stierlin Court Mountain View
CA 94043-4655
U.S.A.
FPGA Architectures & VHDL
Nizar Abdallah
nizar@ieee.org
October 2009
FPGA Architectures & VHDL
Introduction to FPGAs & FPGA design flows
Introduction to Synthesis
The VHDL hardware description language
Design verification, validation, and testing
Programmable ASICs
Logic
CPLDs FPGAs
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ΔΦαηφλμϕ
ΔΦαηφλμϕ
ψΓ∀234567∞
ψΓ∀234567∞
ARM
Cortex-M1
Verification
Algorithmic
RTL
C How it is
Gate Structural connected
How it is
Layout Physical implemented
Actel Corporation Confidential © 2009 17
FSM Abstraction Level
Finite State Machine
E3
DIN DOUT
COMBINATIONAL
LOGIC
REGISTERS
CLOCK
CIN SUM
A
B
COUT
ENTITY
ENTITYdec2to4
dec2to4isis
PORT(A,B,enable:in
PORT(A,B,enable:inBIT;BIT;
vdd,vss,vdde,vsse:in
vdd,vss,vdde,vsse:inBIT;
BIT;
Y:out
Y:outbit_vector(0
bit_vector(0toto3));
3));
end
enddec2to4;
dec2to4;
architecture
architecturedflow
dflowofofdec2to4
dec2to4isis
signal
signala_bar,b_bar:bit;
a_bar,b_bar:bit;
Combinational
signal
signala1,a2,a3,a4:bit;
a1,a2,a3,a4:bit; Logic Synthesis
begin
begin
a_bar
a_bar<=
<=not
nota;a; Gate Netlist =
b_bar
b_bar <= notb;b;
<= not
Gate Level
Structural Description
ENTITY
ENTITYadderadderisis
PORT(A,B,enable:in
PORT(A,B,enable:inBIT; BIT;
vdd,vss,vdde,vsse:in
vdd,vss,vdde,vsse:inBIT;BIT;
ck:
ck:ininbit;
bit;
Y:out
Y:outbit_vector(0
bit_vector(0toto3));
3));
end dec2to4;
end dec2to4; Sequential
architecture
architecturedflow
dflowofofadder
adderisis Logic Synthesis
signal
signalregstr:reg_vector(0
regstr:reg_vector(0toto3)3)
register;
register; Gate Netlist =
signal a1,a2,a3,a4:bit;
signal a1,a2,a3,a4:bit; Gate Level
begin
begin Structural Description
select
if
if (select)
(select) a1
a1 +/−
result
result == a1
a1 ++ a2;
a2; a2 + result result
else
else
result
result == a1
a1 –– a2;
a2; − a2
Mentor Graphics:
Model Technology ModelSim
Cadence:
NC-VHDL simulator
Clive Maxfield,
The Design Warrior's Guide to FPGAs:
Devices, Tools, and Flows,
Elsevier Science & Technology, 2004
ISBN 0750676043
Smith, D. J.,
HDL Chip Design,
Doone Publications, Madison AL, 2001
ISBN 0965193438
K.C. Chang,
Digital Systems Design With VHDL and Synthesis: An
Integrated Approach,
Wiley-IEEE Computer Society Press, First edition 1999
ISBN 0-7695-0023-4