University of Science and Technology

of Southern Philippines
Alubijid | Cagayan de Oro | Claveria | Jasaan | Oroquieta | Panaon

DESIGNING BUFFER

USING 180nm TECHNOLOGY

In partial fulfillment of the requirements for

ECE416 Technical Elective

Instructor:

Engr. Arcel Salem

Instructor

Student:

Nambatac, John Nicole C.

BS ECE 4B
OBJECTIVES

1. Design a buffer which is composed to 4 cascaded inverters.

2. The width of PMOS and NMOS of the inverters are all ratioed to be 2:1.

3. The output load is set to 1.0pF

4. The input signal is a pulse train of which the period=10ns, duty cycle=50%, rise time=fall

time=0.1ns, VDD=3.3v

5. Keep the length of each MOS the minimal size. The width of the MOS are magnified, but still

keep the proper 2:1 as the PU(pull-up) to PD(pull-down) ratio. The cases you have to run

simulation is PU:PD = (2/1:1/1), (6/1:3/1), (18/1:9/1), (48/1:24/1), and (144/1:72/1).

6.Record the “rise time”, “fall time”, “low to high delay", "high to low delay” by DSCH and

Microwind simulation results of the above 5 cases.

7. Laboratory must include each case’s output waveform and the schematic.

THEORY

BUFFER GATE

If we were to connect two inverter gates together so that the output of one fed into the

input of another, the two inversion functions would “cancel” each other out so that there would

be no inversion from input to final output:

 While this may seem like a pointless thing to do, it does have practical application.

Remember that gate circuits are signal amplifiers, regardless of what logic function they may

perform.

A weak signal source (one that is not capable of sourcing or sinking very much current to

a load) may be boosted by means of two inverters like the pair shown in the previous illustration.

The logic level is unchanged, but the full current-sourcing or sinking capabilities of the final

inverter are available to drive a load resistance if needed.

For this purpose, a special logic gate called a buffer is manufactured to perform the same

function as two inverters. Its symbol is simply a triangle, with no inverting “bubble” on the

output terminal:

Buffer Circuit with Open-Collector Output

The internal schematic diagram for a typical open-collector buffer is not much different

from that of a simple inverter: only one more common-emitter transistor stage is added to re-

invert the output signal.

 
 “High” Input Analysis

Let’s analyze this circuit for two conditions: an input logic level of “1” and an input logic

level of “0.” First, a “high” (1) input:

As before with the inverter circuit, the “high” input causes no conduction through the left

steering diode of Q1 (emitter-to-base PN junction). All of R1‘s current goes through the base of

transistor Q2, saturating it:

 Having Q2 saturated causes Q3 to be saturated as well, resulting in very

little voltage dropped between the base and emitter of the final output transistor Q4. Thus, Q4

will be in cutoff mode, conducting no current.

The output terminal will be floating (neither connected to ground nor Vcc), and this will

be equivalent to a “high” state on the input of the next TTL gate that this one feeds in to. Thus, a

“high” input gives a “high” output.

“Low” Input Analysis

With a “low” input signal (input terminal grounded), the analysis looks something like

this:
 

All of R1‘s current is now diverted through the input switch, thus eliminating base

current through Q2. This forces transistor Q2 into cutoff so that no base current goes through Q3

either.

With Q3 cutoff as well, Q4 is will be saturated by the current through resistor R4, thus

connecting the output terminal to ground, making it a “low” logic level. Thus, a “low” input

gives a “low” output.

Schematic Diagram with Totem Pole Output Transistors

The schematic diagram for a buffer circuit with totem pole output transistors is a bit more

complex, but the basic principles, and certainly the truth table, are the same as for the open-

collector circuit:
Answer the following questions:

1. What is duty cycle?

A duty cycle or power cycle is the fraction of one period in which a signal or system is

active. Duty cycle is commonly expressed as a percentage or a ratio.

2. What is delay time?

The length of time between when the input to a logic gate becomes stable and valid to

modify and when the output of that logic gate becomes stable and valid to alter is known as delay

time..

3. How do you calculate rise time and fall time?

 4. What is pulse width and period?

Pulse width is the elapsed time between the rising and falling edges of a single pulse. To

make this measurement repeatable and accurate, we use the 50% power level as the reference

points.

Period is the length of time in seconds that the waveform takes to repeat itself from start to

finish. This value can also be called the Periodic Time, ( T ) of the waveform for sine waves, or

the Pulse Width for square waves.

RESULTS AND DISCUSSIONS

Schematic:
Schematic diagram using Dsch2
 Timing diagram of the buffer

Using the DSCH2 software the buffer schematic diagram is created and simulated to test if the
design function as we intended.

In this simulation, we didn’t apply the cases yet because this won’t show the parasitic and only
outputs ideal waveforms. There will be no differences between the output even if we change the
values of the widths of the PMOS and NMOS. In the simulation, we can observe delays on the
output. This is very normal for the buffer as its function is to delay fast signals for input
synchronization.

Layout:
In layout designing and simulations, we will be using Microwind. Cases that will be used for
testing the output is listed in table 1

For the simulation parameters, we will use a clock with 0.1ns fall time, 0.1ns rise time, 4.8 time
off 5 ns time on

the information is also showed in figure 2 for better visual

Figure 2. clock parameters
Case 1:
Layout

Graph

Rise time and fall time

Case 2:
Layout

Graph Rise time and Fall time

Case 3:

Layout Graph

Rise time and Fall time

Case 4:
 Layout Graph

Rise time and Fall time

Case
5:

Layout

Graph

Rise time and Fall time

 High to low Low to high
Rise time (ns) Fall time (ns)
delay (ps) delay (ps)

Case 1 0.198 1.049 1.724 1.304

Case 2 0.103 0.350 0.622 0.589

Case 3 0.071 0.117 0.202 0.320

Case 4 0.061 0.044 0.151 0.101

too small to be
Case 5 0.058 0.067 0.084
measured
Table 2. results

CONCLUSION
If we observe carefully, as we increase the width of PMOS and NMOS while maintaining
proper ratio of 2:1, the rise and fall time of the output signal becomes smaller. The reason behind
this is, the wider the pathway, more holes and electrons can be transferred from source to drain.
This also means that faster transfer of holes and electrons resulting to small delay as well as the
rise time and fall time of the output signal.
additionally, we also realized that the load also needed to be considered when designing
CMOS. The higher the load capacitance means that the designing will need wider pathway to
minimize the delay. this can be done by adjusting the width of the PMOS and NMOS by
changing the ratio. We can also manipulate our delay depending on what result we are aiming. If
we want a specific rise time and fall time in or design, we can achieve by changing the width of
the PMOS and NMOS.