Microcontroller and Application

TE E&TC

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Ms Rupali Mane

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 TABLE OF CONTENT

Chapter Title Page

No No.

1. Basics of 8051 8

Motivation: ................................................................................................................ 8

Syllabus: .................................................................................................................... 8

Books Recommended:............................................................................................... 8

Weight age in University Examination: 20-30 Marks .............................................. 8

Objective: .................................................................................................................. 8

Key Definitions: ........................................................................................................ 8

Theory ....................................................................................................................... 9

Multiple Choice Questions ...................................................................................... 43

Outcome .................................................................................................................. 45

Short Questions: ...................................................................................................... 45

Long Questions: ...................................................................................................... 46

2. 8051 Assembly Language Error! Bookmark not defined.

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8051 Programming: ................................................. Error! Bookmark not defined.

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 Long Questions: ...................................................... Error! Bookmark not defined.

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 LIST OF FIGURES

Figure Title Page.

No
Figure 1-1 Internal Block Diagram of 8051 ............................................................................ 12
Figure 1-2 Programming model of 8051 ................................................................................. 17
Figure 1-3 : Pin Diagram of 8051 ............................................................................................ 18
Figure 1-4 Oscillator and Clock Circuit................................................................................... 18
Figure 1-5 8051 Memory representation ................................................................................. 21
Figure 1-6 SFR register layout ................................................................................................. 24
Figure 1-7 : Port-0 Structure .................................................................................................... 25
Figure 1-8 Port-1 Structure ..................................................................................................... 26
Figure 1-9 Port-2 Structure ...................................................................................................... 27
Figure 1-10 Port-3 Structure .................................................................................................... 27
Figure 1-11 Operation of Timer on Mode-0 ............................................................................ 31
Figure 1-12Operation of Timer in Mode-1 .............................................................................. 32
Figure 1-13 : Operation of Timer in Mode-2 ........................................................................... 32
Figure 1-14 Operation of Timer in Mode-3 ............................................................................. 32
Figure 1-15 8051 Interrupt control system .............................................................................. 39
Figure 1-16 Power Saving Modes of 8051 .............................................................................. 42
Figure 3-1 Schematic diagram of external memory access ..... Error! Bookmark not defined.
Figure 4-1 ARM architecture .................................................. Error! Bookmark not defined.
Figure 5-1 Branch and Exchange instructions ......................... Error! Bookmark not defined.
Figure 5-2 Branch instructions................................................. Error! Bookmark not defined.
Figure 5-3Data processing instructions ................................... Error! Bookmark not defined.
Figure 5-4 ARM shift operations ............................................. Error! Bookmark not defined.
Figure 5-5 Logical shift left ..................................................... Error! Bookmark not defined.
Figure 5-6 Logical shift right ................................................... Error! Bookmark not defined.
Figure 5-7 Arithmetic shift right .............................................. Error! Bookmark not defined.
Figure 5-8 Rotate right ............................................................. Error! Bookmark not defined.
Figure 5-9Rotate right extended .............................................. Error! Bookmark not defined.

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Figure 6-1GPIO ....................................................................... Error! Bookmark not defined.
Figure 6-2 Pin Configuration of LPC2148 .............................. Error! Bookmark not defined.
Figure 6-3 Multiplexing of pin function .................................. Error! Bookmark not defined.
Figure 6-4 Special function Registers ...................................... Error! Bookmark not defined.
Figure 6-5 Square wave generation ......................................... Error! Bookmark not defined.
Figure 6-6 Timer/counter ......................................................... Error! Bookmark not defined.
Figure 0-1 Pulse width Modulation ......................................... Error! Bookmark not defined.

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 LIST OF TABLES

Table 1-1 Microcontrollers of 8051 family ............................................................................. 10

Table 1-2 Program Status Word .............................................................................................. 12
Table 1-3 Register Bank Select control bits ............................................................................ 13
Table 1-4Alternate function of bits of PORT 3 ....................................................................... 19
Table 1-5 Alternate function of bits of PORT 3 ...................................................................... 27
Table 1-6 Timer/Counter Control Logic .................................................................................. 29
Table 1-7 : TMOD Register ..................................................................................................... 29
Table 1-8 : Mode Select bits .................................................................................................... 30
Table 1-9 TCON Register ....................................................................................................... 30
Table 1-12 SCON register format ............................................................................................ 33
Table 1-13 Mode select bit format ........................................................................................... 33
Table 1-14 Data transmission/reception in Mode-0................................................................. 35
Table 1-10IE register format .................................................................................................... 39
Table 1-11 : IP register format ................................................................................................. 40
Table 1-15 : PCON register format .......................................................................................... 41
Table 5-1The ARM Instruction set (Continued) ...................... Error! Bookmark not defined.
Table 5-2 condition code summary.......................................... Error! Bookmark not defined.
Table 5-3 ARM Data processing instructions .......................... Error! Bookmark not defined.

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 1. Basics of 8051

Motivation:
This module introduces the student to the world of microcontrollers, including definitions,
SFRs, and a summary of what’s involved in designing and building a microcontroller project.
To enable the students to understand the need of microcontroller and its difference between
microprocessor and microcontroller and their requirements in market

Syllabus:
Sr.No Topic Fine Detailing No of Hours Weeks

1 Basics of 8051 1. Comparison of microprocessor 08 02

and
2. microcontroller,
3. Architecture and pin functions of
8051 chip controller, CPU timing
and machine cycles
4. Internal memory organization,
Program counter and stack,
5. Input/output ports
6. Counters and timers
7. Serial data input and output
8. Interrupts, Power saving modes

Books Recommended:
1. Ayala, 8051 Microcontroller, Cengage (Thomson)
2. Mazidi & Mazidi, ‘The 8051Microcontroller & Embedded system, using Assembly and
C, 2nd edi, Pearson edu.

Weight age in University Examination: 20-30 Marks

Objective:
This chapter enables the students to learn the basics of 8051 microcontroller, its architecture
and pin configuration. It gives knowledge about inbuilt The Timer/Counters, The serial
Interface, The Interrupt System, The Power Modes, Interfacing with various devices

Key Definitions:
1. Bit: A digit of the binary number or code is called bit. Also, the bit is the fundamental
storage unit of computer memory.

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 2. Byte: The 8-bit (8-digit) binary number or code is called byte
3. Word: 16-bit binary number or code is called word.
4. Bus: Bus is a group of conducting lines that carries data, address and control signals.
5. Bi-directional: The microprocessor has to fetch (read) the data from memory or input
device for processing and after processing, it has to store (write) the data to memory or
output device. Hence the data bus is bi-directional.
6. Fetch and execute cycle: In general, the instruction cycle of an instruction can be
divided into fetch and execute cycles. The fetch cycle is executed to fetch the opcode
from memory. The execute cycle is executed to decode the instruction and to perform
the work instructed by the instruction.
7. Port: The port is a buffered I/O, which is used to hold the data transmitted from the
microprocessor to I/O device or vice-versa.

Theory
Lecture 1
Comparison of microprocessor and microcontroller
Learning Objective: In this lecture student will able to understand basics of microcontrollers
and compare between microprocessors and microcontrollers.

1.7.1 Introduction:
A microcontroller (also microcontroller unit, MCU or µC) is a small computer on a single
integrated circuit consisting of a relatively simple CPU combined with support functions such
as a crystal oscillator, timers, watchdog, serial and analog I/O etc.

1.7.2 Microprocessor vs. Microcontroller

Microprocessor
1. CPU is stand-alone, RAM, ROM, I/O, timer are separate
2. designer can decide on the amount of ROM, RAM and I/O ports.
3. expensive
4. versatility
5. general-purpose

Microcontroller
1. CPU, RAM, ROM, I/O and timer are all on a single chip
2. fix amount of on-chip ROM, RAM, I/O ports

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 3. for applications in which cost, power and space are critical
4. single-purpose
5. Some of the microcontrollers of 8051 family are given as follows:

Table 1-1 Microcontrollers of 8051 family

ON-CHIP ON-CHIP
DATA PROGRAM NO. OF FULL
16-BIT
DEVICE MEMORY MEMORY VECTORED DUPLEX
TIMER/COUNTER
INTERUPTS I/O
(bytes) (bytes)

8031 128 None 2 5 1

8032 256 None 2 6 1

8051 128 4k ROM 2 5 1

8052 256 8k ROM 3 6 1

8751 128 4k EPROM 2 5 1

8752 256 8k EPROM 3 6 1

AT89C51 128 4k Flash Memory 2 5 1

AT89C52 256 8k Flash memory 3 6 1

Let’s check the take away from this lecture

A microcontroller at-least should consist of:
a) RAM, ROM, I/O devices, serial and parallel ports and timers
b) CPU, RAM, I/O devices, serial and parallel ports and timers
c) CPU, RAM, ROM, I/O devices, serial and parallel ports and timers
d) CPU, ROM, I/O devices and timers’
How are microcontrollers classified on the basis of internal bus width?
a) 8,16,32,64 bits
b) 4,8,16,32 bits
c) 8,16 bits
d) 4,16,32 bits ROM, I/O devices and timers

L1. Exercise:
Q.1 Explain difference between microcontroller and microprocessor

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Q.2 Write Some of the microcontrollers of 8051 family

Learning from the lecture ‘basics of microcontrollers’:

Student will able to define the term microcontroller and compare it with microprocessors.

Lecture 2
Architecture and pin functions of 8051 chip controller
Learning Objective: In this lecture student will able to draw architecture 8051
microcontrollers.

1.7.3 Features of 8051

Some of the features that have made the 8051 popular are:

1. 8-bit data bus

2. 16-bit address bus
3. 32 general purpose registers each of 8 bits
4. 16 bit timers (usually 2, but may have more, or less).
5. 3 internal and 2 external interrupts.
6. Bit as well as byte addressable RAM area of 16 bytes.
7. Four 8-bit ports, (short models have two 8-bit ports).
8. 16-bit program counter and data pointer

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1.7.4 Architecture of 8051 microprocessor

Figure 1-1 Internal Block Diagram of 8051

8051 employs Harvard architecture. It has some peripherals such as 32 bit digital I/O, Timers
and Serial I/O. The basic architecture of 8051 is given in above figure

Accumulator: ACC is the Accumulator register. The mnemonics for accumulator-specific

instructions, however, refer to the accumulator simply as A.

B Register: The B register is used during multiply and divide operations. For other instructions
it can be treated as another scratch pad register.

Program Status Word (PSW): The Program Status Word is used to store a number of
important bits that are set and cleared by 8051 instructions. The PSW SFR contains the carry
flag, the auxiliary carry flag, the overflow flag, and the parity flag. Additionally, the PSW
register contains the register bank select flags which are used to select which of the "R" register
banks are currently selected.

Table 1-2 Program Status Word

Bit No D7 D6 D5 D4 D3 D2 D1 D0

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 Bit Position PSW.7 PSW.6 PSW.5 PSW.4 PSW.3 PSW.2 PSW.1 PSW.0

Bit
CY AC F0 RS1 RS0 OV ----- P
Definitions

• CY: Carry Flag; used in arithmetic, JUMP, ROTATE, and BOOLEAN instructions
• AC: Auxiliary Carry flag used for BCD operations.
• F0: User defines flag. Available to the user for general purposes
• RS1, RS0: Register bank Select control bits 1 & 0. Set/cleared by software to determine
working register bank. Operation is as follows:

Table 1-3 Register Bank Select control bits

Register Bank Select

Operation Addresses
RS1 RS0

0 0 Select Register Bank 0 00H-07H

0 1 Select Register Bank 1 08H-0FH

1 0 Select Register Bank 2 10H-17H

1 1 Select Register Bank 3 18H-1FH

• P: Parity flag: Set/cleared by hardware each instruction cycle to indicate and odd/even
number of “one” bits in the accumulator, i.e., even parity.

The "R" registers: The "R" registers are a set of eight registers that are named R0, R1, etc.
up to and including R7. These registers are used as auxiliary registers in many operations. The
Accumulator alone would not be very useful if it were not for these "R" registers. The "R"
registers are also used to temporarily store values.

Stack Pointer: The Stack Pointer register is 8 bits wide. It is incremented before data is stored
during PUSH and CALL executions. While the stack may reside anywhere in on-chip RAM,
the Stack Pointer is initialized to 07H after a reset. This causes the stack to begin at location
08H.

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Data Pointer: The Data Pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL).
Its intended function is to hold a 16-bit address. It may be manipulated as a 16-bit register or
as two independent 8-bit registers.

Ports 0 to 3: P0, P1, P2 and P3 are the SFR latches of Ports 0, 1, 2 and 3, respectively.

P0 (Port 0, Bit-Addressable): This is input/output port 0. Each bit of this SFR corresponds to
one of the pins on the microcontroller. For example, bit 0 of port 0 is pin P0.0, bit 7 is pin P0.7.
Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin
whereas a value of 0 will bring it to a low level.

P1 (Port 1, Bit-Addressable): This is input/output port 1. Each bit of this SFR corresponds to
one of the pins on the microcontroller. For example, bit 0 of port 1 is pin P1.0, bit 7 is pin P1.7.
Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin
whereas a value of 0 will bring it to a low level.

P2 (Port 2, Bit-Addressable): This is input/output port 2. Each bit of this SFR corresponds to
one of the pins on the microcontroller. For example, bit 0 of port 2 is pin P2.0, bit 7 is pin P2.7.
Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin
whereas a value of 0 will bring it to a low level.

P3 (Port 3, Bit-Addressable): This is input/output port 3. Each bit of this SFR corresponds to
one of the pins on the microcontroller. For example, bit 0 of port 3 is pin P3.0, bit 7 is pin P3.7.
Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin
whereas a value of 0 will bring it to a low level.

Serial Data Buffer: The Serial Data Buffer is actually two separate registers, a transmit buffer
and a receive buffer register. When data is moved to SBUF, it goes to the transmit buffer where
it is held for serial transmission. (Moving a byte to SBUF is what initiates the transmission.)
When data is moved from SBUF, it comes from the receive buffer.

Timer Registers: Register pairs (TH0, TL0), and (TH1, TL1), are the 16-bit counting registers
for Timer/Counters 0, and 1, respectively.

Control Registers: Special Function Registers IP, IE, TMOD, TCON, T2CON, SCON, and
PCON contain control and status bits for the interrupt system, the timer/counters, and the serial
port.

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IE (Interrupt Enable): The Interrupt Enable SFR is used to enable and disable specific
interrupts. The low 7 bits of the SFR are used to enable/disable the specific interrupts, where
as the highest bit is used to enable or disable ALL interrupts. Thus, if the high bit of IE is 0 all
interrupts are disabled regardless of whether an individual interrupt is enabled by setting a
lower bit.

IP (Interrupt Priority, Bit-Addressable): The Interrupt Priority SFR is used to specify the
relative priority of each interrupt. On the 8051, an interrupt may either be of low (0) priority or
high (1) priority. An interrupt may only interrupt interrupts of lower priority. For example, if
we configure the 8051 so that all interrupts are of low priority except the serial interrupt, the
serial interrupt will always be able to interrupt the system, even if another interrupt is currently
executing. However, if a serial interrupt is executing no other interrupt will be able to interrupt
the serial interrupt routine since the serial interrupt routine has the highest priority.

PCON (Power Control): The Power Control SFR is used to control the 8051's power control
modes. Certain operation modes of the 8051 allow the 8051 to go into a type of "sleep" mode
which requires much less power. These modes of operation are controlled through PCON.
Additionally, one of the bits in PCON is used to double the effective baud rate of the 8051's
serial port.

Let’s check the take away from this lecture

1) What is function of port 0
i) I/O ii) Address
iii) Data iv) address/data bus and I/O
2) What is function of DPTR
i) To point external memory ii) To point I/O
iii) To point internal memory 64 Kbytes iv) to store data

L2. Exercise:
Q.1 Explain the functions of PC,DPTR,Port 0 and Port 3.
Q.2 Draw the architecture of 8051 and explain the functions of each block

Learning from the lecture ‘architecture of 8051’:

Student will able to draw the architecture of 8051 and explain the functions of each block.

Lecture 3
Architecture and pin functions of 8051 chip controller, CPU timing and machine cycles

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 continued.
Learning Objective: In this lecture student will able to learn to draw 8051 microcontrollers
Architecture, and draw pin configuration of 8051

TCON (Timer Control, Bit-Addressable): The Timer Control SFR is used to configure and
modify the way in which the 8051's two timers operate. This SFR controls whether each of the
two timers is running or stopped and contains a flag to indicate that each timer has overflowed.
Additionally, some non-timer related bits are located in the TCON SFR. These bits are used to
configure the way in which the external interrupts are activated and also contain the external
interrupt flags which are set when an external interrupt has occurred.

TMOD (Timer Mode): The Timer Mode SFR is used to configure the mode of operation of
each of the two timers. Using this SFR your program may configure each timer to be a 16-bit
timer, an 8-bit auto-reload timer, a 13-bit timer, or two separate timers. Additionally, you may
configure the timers to only count when an external pin is activated or to count "events" that
are indicated on an external pin.

TL0/TH0 (Timer 0 Low/High): These two SFRs, taken together, represent timer 0. Their
exact behavior depends on how the timer is configured in the TMOD SFR; however, these
timers always count up. What is configurable is how and when they increment in value.

TL1/TH1 (Timer 1 Low/High): These two SFRs, taken together, represent timer 1. Their
exact behavior depends on how the timer is configured in the TMOD SFR; however, these
timers always count up. What is configurable is how and when they increment in value.

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Figure 1-2 Programming model of 8051

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1.7.5 Pin diagram of 8051

Figure 1-3 : Pin Diagram of 8051

1.7.6 Oscillator and Clock Circuit:

XTAL1 and XTAL2 are the input and output of a single-stage on-chip inverter, which can be
configured with off-chip components as a Pierce oscillator, as shown in Figure 4.4.

Figure 1-4 Oscillator and Clock Circuit

The oscillator, in any case, drives the internal clock generator. The clock generator provides
the internal clocking signals to the chip. The internal clocking signals are at half the oscillator
frequency, and define the internal phases, states, and machine cycles.

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 : The read strobe for external fetches is PSEN. PSEN is not activated for internal fetches.
When the CPU is accessing external Program Memory, PSEN is activated twice every cycle
(except during a MOVX instruction) whether or not the byte fetched is actually needed for the
current instruction. When PSEN is activated its timing is not the same as RD.

ALE: The main function of ALE is to provide a properly timed signal to latch the low byte of
an address from P0 to an external latch during fetches from external Program Memory. For that
purpose ALE is activated twice every machine cycle. This activation takes place even when
the cycle involves no external fetch.

(Enable Address): The microcontroller by default starts searching for program from
external.

program memory. PC is higher than FFFH for 8051. By applying logic zero to this pin, P2
and P3 are used for data and address transmission with no regard to whether there is internal
memory or not. It means that even there is a program written to the microcontroller, it will not
be executed. Instead, the program written to external ROM will be executed. By applying logic
one to the pin, the microcontroller will use both memories, first internal then external (if
exists).

Vcc & GND: Standard power supply to connect +5V power supply w.r.t. GND.

RST (Reset): A logic one on this pin disables the microcontroller and clears the contents of
most registers. In other words, the positive voltage on this pin resets the microcontroller. By
applying logic zero to this pin, the program starts execution from the beginning.

1.7.6.1 Port Structures and Operation

All four ports in the 80C51 are bidirectional. Each consists of a latch (Special Function Register
P0 through P3), an output driver, and an input buffer. The output drivers of Ports 0 and 2, and
input buffers of Port 0, are used in accesses to external memory. In this application, Port 0
outputs the low byte of the external memory address, time-multiplexed with the byte being
written or read. Port 2 outputs the high byte of the external memory address when the address
is 16 bits wide. Otherwise the Port 2 pins continue to emit the P2 SFR content.All the Port 3
pins are multifunctional. They are not only port pins, but also serve the functions of various
special features as listed below:

Table 1-4Alternate function of bits of PORT 3

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 Port Pins Alternate Function

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 (external interrupt)

P3.3 (external interrupt)

P3.4 T0 (Timer/Counter 0 external input)

P3.5 T1 (Timer/Counter 1 external input)

P3.6 (external Data memory write strobe)

P3.7 (external Data memory read strobe)

The alternate functions can only be activated if the corresponding bit latch in the port SFR
contains 1. Otherwise the port pin is stuck at 0.

Let’s check the take away from this lecture

1) EA bar is
i) External access ii) Extra access
iii) External and iv) none of the above
2) What is function of port 1
i) I/O ii) only input
iii) only output iv) none of the above

L3. Exercise:
Q.1 Draw Pin configuration of 8051 and state the functions of each pin
Q.2 Explain the functions of Port 3 in detail

Learning from the lecture ‘architecture of 8051 and pin configuration’

Student will able to draw the architecture of 8051 and pin configuration of 8051 explains the
functions of each block. Also able to draw pin configuration of 8051
.

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 Lecture 4
Internal memory organization, Program counter and stack
Learning Objective: In this lecture student will able to learn about RAM and ROM of 8051.

1.7.7 Memory and register organization

The 8051 has a separate memory space for code (programs) and data. We will referhere to on-
chip memory and external memory as shown in figure. In an actual implementation the external
memory may, in fact, be contained within the microcomputer chip. However, we will use the
definitions of internal and external memory to be consistent with 8051 instructions which
operate on memory. Note, the separation of the code and data memory in the 8051 architecture
is a little unusual. The separated memory architecture is referred to as Harvard architecture
whereas Von Neumann architecture defines a system where code and data can share common
memory.

Figure 1-5 8051 Memory representation

1.7.8 External Code Memory

The executable program code is stored in this code memory. The code memory size is limited
to 64KBytes (in a standard 8051). The code memory is read-only in normal operation and is
programmed under special conditions e.g. it is a PROM or a Flash RAM type of memory.

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1.7.9 External RAM Data Memory
This is read-write memory and is available for storage of data. Up to 64KBytes of external
RAM data memory is supported (in a standard 8051).

1.7.10 Internal Memory

The 8051’s on-chip memory consists of 256 memory bytes organised as follows: First 128
bytes: 00h to 1Fh Register Banks20h to 2Fh Bit Addressable RAM 30 to 7Fh General Purpose
RAM

Next 128 bytes: 80h to FFh Special Function Registers

The first 128 bytes of internal memory is organised as shown in figure, and is referred to as
Internal RAM, or IRAM.

Figure 4.6: Organization of Internal RAM (IRAM) memory

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1.7.11 Register Banks: 00h to 1Fh
The 8051 uses 8 general-purpose registers R0 through R7 (R0, R1, R2, R3, R4, R5,R6, and
R7). These registers are used in instructions such as:

ADD A, R2 ; adds the value contained in R2 to the accumulator

1.7.12 Bit Addressable RAM: 20h to 2Fh

The 8051 supports a special feature which allows access to bit variables. This is where
individual memory bits in Internal RAM can be set or cleared. In all there are 128 bits numbered
00h to 7Fh. Being bit variables any one variable can have a value 0 or 1. A bit variable can be
set with a command such as SETB and cleared with a command such as CLR. Example
instructions are:

SETB 25h ; sets the bit 25h (becomes 1)

CLR 25h ; clears bit 25h (becomes 0)

Note, bit 25h is actually bit b5 of Internal RAM location 24h.

1.7.13 General Purpose RAM: 30h to 7Fh

These 80 bytes of Internal RAM memory are available for general-purpose data storage. Access
to this area of memory is fast compared to access to the main memory and special instructions
with single byte operands are used. However, these 80 bytes are used by the system stack and
in practice little space is left for general storage. The general purpose RAM can be accessed
using direct or indirect addressing modes.

1.7.14 SFR Registers

The SFR registers are located within the Internal Memory in the address range 80h to FFh, as
shown in figure 4.7. Not all locations within this range are defined. Each SFR has a very
specific function. Each SFR has an address (within the range 80h to FFh) and a name which
reflects the purpose of the SFR. Although 128 byes of the SFR address space is defined only
21 SFR registers are defined in the standard 8051. Undefined SFR addresses should not be
accessed as this might lead to some unpredictable results. Note some of the SFR registers are
bit addressable. SFRs are accessed just like normal Internal RAM locations.

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 Figure 1-6 SFR register layout

Let’s check the take away from this lecture

1) What is SFR
i) Specific function register ii) Specific function register
iii) Stack function register iv) none of the above
2) Which of the following registers are not bit addressable?
i) Port 0 ii)Port 2
iii) TCON iv) TMOD

L4. Exercise:
Q.1 Write short note on Special function Register
Q.2 Draw internal memory organization of 8051

Learning from the lecture ‘Internal memory organization’

Student will able to draw and explain the internal memory organization of 8051

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 Lecture 5
Input/output ports
Learning Objective: In this lecture student will able to draw and explain the structure of input
output ports.
I/O Port Configuration:
Each port of 8051 has bidirectional capability. Port 0 is called 'true bidirectional port' as it floats
(tri-stated) when configured as input. Port-1, 2, 3 are called 'quasi bidirectional port'.

Port-0 Pin Structure: Port -0 has 8 pins (P0.0-P0.7). The structure of a Port-0 pin is shown in
figure

Figure 1-7 : Port-0 Structure

Port-0 can be configured as a normal bidirectional I/O port or it can be used for address/data
interfacing for accessing external memory. When control is '1', the port is used for address/data
interfacing. When the control is '0', the port can be used as a normal bidirectional I/O port.

Let us assume that control is '0'. When the port is used as an input port, '1' is written to the
latch. In this situation both the output MOSFETs are 'off'. Hence the output pin floats. This
high impedance pin can be pulled up or low by an external source. When the port is used as an
output port, a '1' written to the latch again turns 'off' both the output MOSFETs and causes the
output pin to float. An external pull-up is required to output a '1'. But when '0' is written to the
latch, the pin is pulled down by the lower MOSFET. Hence the output becomes zero.

When the control is '1', address/data bus controls the output driver MOSFETs. If the
address/data bus (internal) is '0', the upper MOSFET is 'off' and the lower MOSFET is 'on'. The
output becomes '0'. If the address/data bus is '1', the upper transistor is 'on' and the lower
transistor is 'off'. Hence the output is '1'. Hence for normal address/data interfacing (for external
memory access) no pull-up resistors are required.

Port-0 latch is written to with 1's when used for external memory access.
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Port-1 Pin Structure: Port-1 has 8 pins (P1.1-P1.7) .The structure of a port-1 pin is shown in
figure

Figure 1-8 Port-1 Structure

Port-1 does not have any alternate function i.e. it is dedicated solely for I/O interfacing. When
used as output port, the pin is pulled up or down through internal pull-up. To use port-1 as input
port, '1' has to be written to the latch. In this input mode when '1' is written to the pin by the
external device then it read fine. But when '0' is written to the pin by the external device then
the external source must sink current due to internal pull-up. If the external device is not able
to sink the current the pin voltage may rise, leading to a possible wrong reading.

Port-2 Pin Structure: Port-2 has 8-pins (P2.0-P2.7). The structure of a port-2 pin is shown in
figure 4.10. Port-2 is used for higher external address byte or a normal input/output port. The
I/O operation is similar to Port-1. Port-2 latch remains stable when Port-2 pin are used for
external memory access. Here again due to internal pull-up there is limited current driving
capability.

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 Figure 1-9 Port-2 Structure

1. Port-3 Pin Structure: Port-3 has 8 pin (P3.0-P3.7). Port-3 pins have alternate
functions. The structure of a port-3 pin is shown in figure 4.11.

Figure 1-10 Port-3 Structure

Each pin of Port-3 can be individually programmed for I/O operation or for alternate function.
The alternate function can be activated only if the corresponding latch has been written to '1'.
To use the port as input port, '1' should be written to the latch. This port also has internal pull-
up and limited current driving capability.

Alternate functions of Port-3 pins are:

Table 1-5 Alternate function of bits of PORT 3

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 Port Pins Alternate Function

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 (external interrupt)

P3.3 (external interrupt)

P3.4 T0 (Timer/Counter 0 external input)

P3.5 T1 (Timer/Counter 1 external input)

P3.6 (external Data memory write strobe)

P3.7 (external Data memory read strobe)

Let’s check the take away from this lecture

1) Port 0 has function of
i) I/O ii) address
iii) data iv) all above
2) Function of Port 1
i i) I/O ii) address
iii) data iv) all above

L5. Exercise:
Q.1 Draw the structure Port 1 and Port 2
Q.2 Draw the structure Port 0 and Port 3

Learning from the lecture ‘lubricants background’:

Student will able to draw and explain the structure of input output ports.

Lecture 6
Counters and timers
Learning Objective: In this lecture student will able to draw and explain counters and timers.

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1.7.15 Timers/Counters Operation:
8051 has two 16-bit programmable UP timers/counters. They can be configured to operate
either as timers or as event counters. The names of the two counters are T0 and T1
respectively. The timer content is available in four 8-bit special function registers, viz, TL0,
TH0, TL1 and TH1 respectively.

In the "timer" function mode, the counter is incremented in every machine cycle. Thus, one
can think of it as counting machine cycles. Hence the clock rate is 1/12 th of the oscillator
frequency.

In the "counter" function mode, the register is incremented in response to a 1 to 0 transition at

its corresponding external input pin (T0 or T1). It requires 2 machine cycles to detect a high to
low transition. Hence maximum count rate is 1/24 th of oscillator frequency

Timer/ Counter control logic:

Table 1-6 Timer/Counter Control Logic

The operation of the timers/counters is controlled by two special function registers, TMOD
and TCON respectively.

Timer Mode control (TMOD): TMOD register is not bit addressable.

Table 1-7 : TMOD Register

Bit Position D7 D6 D5 D4 D3 D2 D1 D0

Bit Definition GATE M1 M0 GATE M1 M0

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Various bits of TMOD are described as follows:

Gate: This is an OR Gate enabled bit which controls the effect of on START/STOP of
Timer. It is set to one ('1') by the program to enable the interrupt to start/stop the timer. If TR1/0
in TCON is set and signal on pin is high then the timer starts counting using either internal
clock (timer mode) or external pulses (counter mode).

: It is used for the selection of Counter/Timer mode.

Mode Select Bits:

Table 1-8 : Mode Select bits

M1 M0 Mode Operation

0 0 Mode 0 13-bit Counter

0 1 Mode 1 16-bit Counter

1 0 Mode 2 8-bit Auto reload

1 1 Mode 3 Two 8-bit counters, split operation

Timer control (TCON): TCON is bit addressable. The address of TCON is 88H. It is partly
related to Timer and partly to interrupt.

Table 1-9 TCON Register

Bit Position D7 D6 D5 D4 D3 D2 D1 D0

Bit Definition TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

The various bits of TCON are as follows.

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TF1: Timer1 overflow flag. It is set when timer rolls from all 1s to 0s. It is cleared when
processor vectors to execute ISR located at address 001BH.

TR1: Timer1 run control bit. Set to 1 to start the timer / counter.

TF0: Timer0 overflow flag. (Similar to TF1)

TR0: Timer0 run control bit.

IE1: Interrupt1 edge flag. Set by hardware when an external interrupt edge is detected. It is
cleared when interrupt is processed.

IE0: Interrupt0 edge flag. (Similar to IE1)

IT1: Interrupt1 type control bit. Set/ cleared by software to specify falling edge / low level
triggered external interrupt.

IT0: Interrupt0 type control bit. (Similar to IT1)

Timers/Counters Modes of Operation:

Timer Mode-0: In this mode, the timer is used as a 13-bit UP counter as follows.

Figure 1-11 Operation of Timer on Mode-0

The lower 5 bits of TLX and 8 bits of THX are used for the 13 bit count. Upper 3 bits of TLX
are ignored. When the counter rolls over from all 0's to all 1's, TFX flag is set and an interrupt
is generated.

The input pulse is obtained from the previous stage. If TR1/0 bit is 1 and Gate bit is 0, the
counter continues counting up. If TR1/0 bit is 1 and Gate bit is 1, then the operation of the
counter is controlled by input. This mode is useful to measure the width of a given pulse
fed to input.

Timer Mode-1: This mode is similar to mode-0 except for the fact that the Timer operates in
16-bit mode.

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 Figure 1-12Operation of Timer in Mode-1

Timer Mode-2: (Auto-Reload Mode): This is a 8 bit counter/timer operation. Counting is

performed in TLX while THX store a constant value. In this mode when the timer overflows
i.e. TLX becomes FFH, it is fed with the value stored in THX. For example if we load THX
with 50H then the timer in mode 2 will count from 50H to FFH. After that 50H is again
reloaded. This mode is useful in applications like fixed time sampling.

Figure 1-13 : Operation of Timer in Mode-2

Timer Mode-3: Timer 1 in mode-3 simply holds its count. The effect is same as setting TR1=0.
Timer0 in mode-3 establishes TL0 and TH0 as two separate counters.

Figure 1-14 Operation of Timer in Mode-3

Control bits TR1 and TF1 are used by Timer-0 (higher 8 bits) (TH0) in Mode-3 while TR0 and
TF0 are available to Timer-0 lower 8 bits(TL0).

Let’s check the take away from this lecture

1) Timer operates in 16 bit mode
i) mode 0 ii) mode3
iii) mode1 iv) none of the above

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2) The address of TCON is
i) 88 ii) 82
iii) 87 iv) 3A

L6,7. Exercise:
Q.1 Explain TMOD and TCON register
Q.2 Explain in brief various timer modes of 8051 .

Learning from the lecture ‘Timers and counters’ :

Student will able to draw and explain functions of TMOD and TCON register

Lecture 7
Serial data input and output
Learning Objective: In this lecture student will able to draw and explain serial
communication of 8051.

Serial Communication:
The serial port of 8051 is full duplex, i.e., it can transmit and receive simultaneously.
The register SBUF is used to hold the data. The special function register SBUF is physically
two registers. One is, write-only and is used to hold data to be transmitted out of the 8051
via TXD. The other is, read-only and holds the received data from external sources via RXD.
Both mutually exclusive registers have the same address 099H.

Serial Port Control Register (SCON): Register SCON controls serial data
communication.
Table 1-10 SCON register format

Bit Position D7 D6 D5 D4 D3 D2 D1 D0

Bit Definition SM0 SM1 SM2 REN TB8 RB8 TI RI

SM1 & SM0: Mode select bits

Table 1-11 Mode select bit format

SM1 SM0 Mode Operation Baud Rate

0 0 Mode 0 8-bit Shift Register 1/12 of the crystal frequency

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 0 1 Mode 1 8-UART Determined by Timer – 1

1/32 the crystal frequency

1 0 Mode 2 9-bit UART
(1/64 the crystal frequency)

1 1 Mode 3 9-bit UART Determined by Timer – 1

• SM2: Multiprocessor communication bit

• REN: Receive enable bit
• TB8: Transmitted bit 8 (Normally we have 0-7 bits transmitted/received)
• RB8: Received bit 8
• TI: Transmit interrupt flag
• RI: Receive interrupt flag
Data Transmission: Transmission of serial data begins at any time when data is written to
SBUF. Pin P3.1 (Alternate function bit TXD) is used to transmit data to the serial data network.
TI is set to 1 when data has been transmitted. This signifies that SBUF is empty so that another
byte can be sent.
Data Reception: Reception of serial data begins if the receive enable bit is set to 1 for all
modes. Pin P3.0 (Alternate function bit RXD) is used to receive data from the serial data
network. Receive interrupt flag, RI, is set after the data has been received in all modes. The
data gets stored in SBUF register from where it can be read.
Serial Data Transmission Modes:
Mode-0 (8-bit Shift Register): In this mode, the serial port works like a shift register and the
data transmission works synchronously with a clock frequency of fosc /12. Serial data is
received and transmitted through RXD. 8 bits are transmitted/ received at a time. Pin TXD
outputs the shift clock pulses of frequency fosc/12, which is connected to the external circuitry
for synchronization. The shift frequency or baud rate is always 1/12 of the oscillator frequency.

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 Table 1-12 Data transmission/reception in Mode-0

1. Mode-1 (standard UART mode): In mode-1, the serial port functions as a standard
Universal Asynchronous Receiver Transmitter (UART) mode. 10 bits are transmitted
through TXD or received through RXD. The 10 bits consist of one start bit (which is
usually '0'), 8 data bits (LSB is sent first/received first), and a stop bit (which is usually
'1'). Once received, the stop bit goes into RB8 in the special function register SCON.
The baud rate is variable.
The following figure shows the way the bits are transmitted/ received.

Figure 4.19: Data transmission format in UART mode

Bit time= 1/fbaud

In receiving mode, data bits are shifted into the receiver at the programmed baud rate. The data
word (8-bits) will be loaded to SBUF if the following conditions are true.

RI must be zero. (i.e., the previously received byte has been cleared from SBUF). Mode bit
SM2 = 0 or stop bit = 1. After the data is received and the data byte has been loaded into SBUF,
RI becomes one.

Mode-1 baud rate generation:

Timer-1 is used to generate baud rate for mode-1 serial communication by using overflow flag
of the timer to determine the baud frequency. Timer-1 is used in timer mode-2 as an auto-
reload 8-bit timer. The data rate is generated by timer-1 using the following formula.

Where,

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SMOD is the 7th bit of PCON register fosc is the crystal oscillator frequency of the
microcontroller

It can be noted that fosc/(12 X [256- (TH1)]) is the timer overflow frequency in timer mode-2,
which is the auto-reload mode.

If timer-1 is not run in mode-2, then the baud rate is,

Timer-1 can be run using the internal clock, fosc /12 (timer mode) or from any external source
via pin T1 (P3.5) (Counter mode).

Example: If standard baud rate is desired, then 11.0592 MHz crystal could be selected. To get
a standard 9600 baud rate, the setting of TH1 is calculated as follows.

Assuming SMOD to be '0'

Or,

Or,

In mode-1, if SM2 is set to 1, no receive interrupt (RI) is generated unless a valid stop bit is
received.

Mode-2 (Multiprocessor Mode): In this mode 11 bits are transmitted through TXD or
received through RXD. The various bits are as follows: a start bit (usually '0'), 8 data bits (LSB
first), a programmable 9th (TB8 or RB8) bit and a stop bit (usually '1').

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 While transmitting, the 9th data bit (TB8 in SCON) can be assigned the value '0' or '1'.
For example, if the information of parity is to be transmitted, the parity bit (P) in PSW could
be moved into TB8. On reception of the data, the 9th bit goes into RB8 in 'SCON', while the
stop bit is ignored. The baud rate is programmable to either 1/32 or 1/64 of the oscillator
frequency.

fbaud = (2 SMOD /64) fosc.

Mode-3 (Multi processor mode with variable baud rate): In this mode 11 bits are
transmitted through TXD or received through RXD. The various bits are: a start bit (usually
'0'), 8 data bits (LSB first), a programmable 9th bit and a stop bit (usually '1').

Mode-3 is same as mode-2, except the fact that the baud rate in mode-3 is variable (i.e., just as
in mode-1).

fbaud = (2 SMOD /32) * ( fosc / 12 (256-TH1)) .

This baud rate holds when Timer-1 is programmed in Mode

1.7.16 Power saving modes:

8051 has two power saving modes. They are:

• Idle Mode
• Power down mode

The two power saving modes are entered by setting two bits IDL and PD in the special function
register (PCON) respectively.

Let’s check the take away from this lecture

1) UART is
i) Universal Asynchronous Receiver Transmitter ii) Unity Asynchronous Receiver
Transmitter iii) both a and b iv) none of the above

L8,9. Exercise:
Q.1 Draw and explain SMOD of 8051
Q 2. Draw and explain SBUFF REGISTERs of 8051

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Learning from the lecture ‘Serial data input and output,
Student will able to draw and explain serial communication of 8051 with SMOD and SBUFF
register

Lecture 8
Interrupts, Power saving modes
Learning Objective: In this lecture student will able to learn about interrupts and power
saving modes.

Interrupts Structure:

8051 provides 5 vectored interrupts. They are:

Sr. No Interrupt Type of interrupt

1 External–0

2 TF0 Timer–0 (Internal)

3 External–1

4 TF1 Timer–1(Internal)

5 RI/TI Serial Port (Internal)

Table 4.9: Interrupts of 8051

Out of these, and are external interrupts whereas Timer and Serial port interrupts are
generated internally. The external interrupts could be negative edge triggered or low level
triggered. All these interrupt, when activated, set the corresponding interrupt flags. Except for
serial interrupt, the interrupt flags are cleared when the processor branches to the Interrupt
Service Routine (ISR). The external interrupt flags are cleared on branching to Interrupt
Service Routine (ISR), provided the interrupt is negative edge triggered. For low level triggered
external interrupt as well as for serial interrupt, the corresponding flags have to be cleared by
software by the programmer.

The schematic representation of the interrupts is as follows:

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 Figure 1-15 8051 Interrupt control system

Each of these interrupts can be individually enabled or disabled by 'setting' or

'clearing' the corresponding bit in the IE (Interrupt Enable Register) SFR. IE contains a
global enable bit EA which enables/disables all interrupts at once.

Interrupt Enable register (IE):

Table 1-13IE register format

Bit Position D7 D6 D5 D4 D3 D2 D1 D0

Bit Definition EA ---- ET2 ES ET1 EX1 ET0 EX0

Table 4.10:

EA: Global interrupt enable/disable:

0 - disables all interrupt requests.

1 - enables all individual interrupt requests.

• ES: Enables or disables serial interrupt:

0 - UART system cannot generate an interrupt.

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 1 - UART system enables an interrupt.

• ET1: Bit enables or disables Timer 1 interrupt:

0 - Timer 1 cannot generate an interrupt.

1 - Timer 1 enables an interrupt.

• EX1: Bit enables or disables external 1 interrupt:

0 - change of the pin INT0 logic state cannot generate an interrupt.

1 - enables an external interrupt on the pin INT0 state change.

• ET0: Bit enables or disables timer 0 interrupt:

0 - Timer 0 cannot generate an interrupt.

1 - enables timer 0 interrupt.

• EX0: Bit enables or disables external 0 interrupt:

0 - change of the INT1 pin logic state cannot generate an interrupt.

1 - enables an external interrupt on the pin INT1 state change.

Priority level structure:

Each interrupt source can be programmed to have one of the two priority
levels by setting (high priority) or clearing (low priority) a bit in the IP (Interrupt
Priority) register. A low priority interrupt can itself be interrupted by a high priority
interrupt, but not by another low priority interrupt. If two interrupts of different
priority levels are received simultaneously, the request of higher priority level is
served. If the requests of the same priority level are received simultaneously, an
internal polling sequence determines which request is to be serviced.

Interrupt Priority register (IP):

Table 1-14 : IP register format

Bit Position D7 D6 D5 D4 D3 D2 D1 D0

Bit Definition ---- ---- PT2 PS PT1 PX1 PT0 PX0

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 • PS: Serial Port Interrupt priority bit
Priority 0

Priority 1

• PT1: Timer 1 interrupt priority

Priority 0

Priority 1

• PX1: External Interrupt INT1 priority

Priority 0

Priority 1

• PT0: Timer 0 Interrupt Priority

Priority 0

Priority 1

• PX0: External Interrupt INT0 Priority

Priority 0

Priority 1

Power Mode control Register:

Register PCON controls processor power down, sleep modes and serial data baud rate. Only
one bit of PCON is used with respect to serial communication. The seventh bit (b7) (SMOD)
is used to generate the baud rate of serial communication.

Table 1-15 : PCON register format

Bit Position D7 D6 D5 D4 D3 D2 D1 D0

Bit Definition SMOD ----- ----- ----- GF1 GF0 PD IDL

SMOD: Serial baud rate modify bit

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GF1: General purpose user flag bit 1

GF0: General purpose user flag bit 0

PD: Power down bit

IDL: Idle mode bit

The schematic diagram for 'Power down' mode and 'Idle' mode is given as follows:

Figure 1-16 Power Saving Modes of 8051

Idle Mode: Idle mode is entered by setting IDL bit to 1 (i.e., =0). The clock signal is gated
off to CPU, but not to the interrupt, timer and serial port functions. The CPU status is preserved
entirely. SP, PC, PSW, Accumulator and other registers maintain their data during IDLE mode.
The port pins hold their logical states they had at the time Idle was initiated. ALE and
are held at logic high levels.

Ways to exit Idle Mode:

Activation of any enabled interrupt will clear PCON.0 bit and hence the Idle Mode is exited.
The program goes to the Interrupt Service Routine (ISR). After RETI is executed at the end of
the ISR, the next instruction will start from the one following the instruction that enabled Idle
Mode.

A hardware reset exits the idle mode. The CPU starts from the instruction following the
instruction that invoked the 'Idle' mode.

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Power down Mode: The Power down Mode is entered by setting the PD bit to 1. The internal
clock to the entire microcontroller is stopped (frozen). However, the program is not dead. The
Power down Mode is exited (PCON.1 is cleared to 0) by Hardware Reset only. The CPU starts
from the next instruction where the Power down Mode was invoked. Port values are not
changed/ overwritten in power down mode. Vcc can be reduced to as low as 2V In Power Down
mode. However, Vcc has to be restored to normal value before Power Down mode is exited.

Let’s check the take away from this lecture

1) IE is
i) Interrupt enable register ii) Input Enable
iii) both a and b iv) none of the above
2) IP is
i) Interrupt prority register ii) Input Priority
iii) Both a and b iv) none of the above

L10,11. Exercise:
Q.1 Draw and explain IE and IP REGISTERRS of 8051

Q2 What is interrupt? Explain interrupt structure in 8051 microcontrollers

Q3 Explain power down mode and ideal mode in 8051 microcontrollers

Learning from the lecture ‘Interrupt and power saving modes of 8051,
Student will able to draw and explain interrupt structure of 8051 with IE and IP register

Multiple Choice Questions

1. 8051 series has how many 16 bit registers?
a) 2
b) 3
c) 1
d) 0

2. When 8051 wakes up then 0x00 is loaded to which register?

a) DPTR
b) SP
c) PC
d) PSW

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3. How many bytes of bit addressable memory is present in 8051 based micro
controllers?
a) 8 bytes
b) 32 bytes
c) 16 bytes
d) 128 bytes

4. The register that may be used as an operand register is

a) Accumulator
b) B register
c) Data register
d) Accumulator and B register
5. The register that can be used as a scratch pad is
a) Accumulator
b) B register
c) Data register
d) Accumulator and B register
6. The registers that contains the status information is
a) control registers
b) instruction registers
c) program status word
d) all of the mentioned
7. The architecture of 8051 consists of
a) 4 latches
b) 2 timer registers
c) 4 on-chip I/O ports
d) all of the mentioned
8. The register that provides control and status information about counters is
a) IP
b) TMOD
c) TSCON
d) PCON
9. The register that provides control and status information about serial port is
a) IP

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 b) IE
c) TSCON
d) PCON and SCON

Answers : 1 - a , 2-c,3-c,4-d,5-b,6-c,7-d,8-b,9-d.

Outcome
This module will help students to understand the difference between microprocessor
and microcontroller, its advanced features which are inbuilt within an integrated chip making
it to be a versatile in any embedded application.

Short Questions:
1. Name three features of the 8051.
2. Give Comparison between microprocessor and Microcontroller
3. What is the major difference between the 8051 and 8052 microcontrollers?
4. Give the size of RAM. Of 8051
5. Give the size of the on-chip ROM. 8051
6. What components are normally put together with the microcontroller into a single chip?
7. Write in the difference between microprocessors and microcontroller?
8. Give and explain the formula for calculating instruction cycle time for 8051.
9. Give the important features of 8051 microcontroller?
10. What is the function of dptr register?
11. Explain the bits of psw register.
12. Explain internal and external memory organization of 8051 microcontroller.
13. What are SFRs? Why are they called as special function registers?
14. How an I/O pin can be both an input and output
15. Which port of 8051 has no alternate functions
16. Why a low address byte latch for external memory is needed?
17. Explain the bits of TCON register
18. Explain the bits of TMOD register
19. Explain the Timer/Counter control logic of 8051.
20. Explain the bits of SCON register.
21. Find the baud rate for the serial port in mode0 for a 6 MHz crystal
22. Explain in short the serial communication in 8051.

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23. Explain the bits of IE and IP register.

Long Questions:
1. Explain the clock timings of 8051 in detail. Also justify the choice of resonator for the
clock generation. Give and explain the formula for calculating instruction cycle time
for 8051.
2. Explain the programmer’s model of 8051 microcontroller with emphasis on I/O port
structures and interrupt mechanism it supports.
3. Explain the pin diagram of 8051 microcontroller.
4. What are the different features available in microcontrollers as compared to
microprocessors? Explain their role in embedded system applications.
5. Explain the working of port 0, 1, 2 & 3 in detail for 8051 microcontroller.
6. Explain in detail SFRs used for controlling the timer operation of 8051 microcontroller.
7. Explain the various modes of operation of timers in 8051.
8. Explain the ‘Timer’ of ‘Counter’ mode operation of 8051 micro controller.
9. Explain in detail SFRs used for controlling the serial communication of 8051
microcontroller.
10. Explain the various modes of operation of serial port in 8051.
11. Explain the interrupt structure of 8051 microcontroller. Explain how single stepping
can be achieved.
12. Suggest the hardware scheme to increase the number of interrupting sources to be
handled by INT0 or INTl pin of 8051 and explain the working of it.
13. Write a short note on Power saving modes in 8051.
14. Justify the choice of microcontroller as against that of microprocessor for the
development of ‘embedded system’
15. Draw and Explain the port1 structure of 8051
16. Draw and Explain the port 0 structure of 8051

Prepared by
Ms Rupali Mane

for internal circulations only