Microelectronics Reliability 53 (2013) 1444–1449

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Microelectronics Reliability
journal homepage: www.elsevier.com/locate/microrel

Statistics and localisation of vertical breakdown in AlGaN/GaN HEMTs on

SiC and Si substrates for power applications
Clément Fleury a,⇑, Rimma Zhytnytska b, Sergey Bychikhin a, Mattia Cappriotti a, Oliver Hilt b,
Domenica Visalli c, Gaudenzio Meneghesso d, Enrico Zanoni d, Joachim Würfl b, Joff Derluyn c,
Gottfried Strasser a, Dionyz Pogany a
a
Vienna University of Technology, Floragasse 7, A-1040 Vienna, Austria
b
Ferdinand-Braun-Institut, Leibniz-Institut für Höchstfrequenztechnik (FBH), Gustav-Kirchhof-Strasse 4, 12489 Berlin, Germany
c
EpiGaN, Kempischesteenweg 293, B-3500 Hasselt, Belgium
d
University of Padova, Via Gradenigo 6/B, 35131 Padova, Italy

a r t i c l e i n f o a b s t r a c t

Article history: We analyse vertical breakdown signatures in normally-off and normally-on AlGaN/GaN HEMTs on Si and
Received 28 May 2013 SiC substrate for power applications. The probability distribution function of the breakdown voltage VBD
Received in revised form 18 July 2013 values shows mostly a bimodal distribution that is characteristic for substrate/epitaxy type and bias
Accepted 25 July 2013
polarity. Different types of distribution functions are tested. The vertical breakdown is found to be a time
Available online 23 August 2013
dependent phenomenon and hypotheses for its initiation are discussed. Using backside infrared micros-
copy, we found that the breakdown occurs in localized spots, related to current filaments. Failure local-
isation under pulsed mode shows better spatial localisation compared to the DC conditions.
Ó 2013 Elsevier Ltd. All rights reserved.

1. Introduction
AlGaN/GaN HEMTs are promising candidates for power switch-
ing applications [1], but there are challenges to improve their reli-
ability [2,3]. For low cost mass production, it is desirable to grow
the III-N epitaxial layers on large area silicon substrates with rea-
sonable quality [4]. For safe system operation under power-off
condition, normally-off transistor operation is usually requested
to reduce the requirements for gate driving circuitry. Normally-
off AlGaN/GaN HEMTs with p-doped GaN gate, fabricated on SiC
substrates, have demonstrated a breakdown voltage of 600 V [5].
It has been shown that the device breakdown voltage VBD of such
power devices first linearly increases with the gate to drain dis-
tance LGD (i.e. lateral breakdown) and then becomes independent
of LGD and saturates [6,7]. In a floating substrate configuration, this
saturation is caused by a vertical leakage current and vertical
breakdown (VB) through the GaN buffer, between the Ohmic con-
tact and the substrate [6,7]. For sufficiently conductive substrates,
the saturation value of VBD is thus a sum of breakdown voltages be-
tween the drain-and-substrate and substrate-and-source [6]. Fur-
thermore, a large spreading in VBD values has been found, which
indicates that the VB path can be due to current filaments related
to extended defects [6,8]. Based on area scaling of statistically dis-
tributed VB data, guidelines for optimal power device contact area
⇑ Corresponding author. Tel.: +43 158801362 31; fax: +43 158801362 99.
E-mail address: clement.fleury@tuwien.ac.at (C. Fleury).
have been determined [8]. The vertical leakage current mechanism
across the GaN buffer was recently attributed to trap-mediated
transport [9,10] and the failure location was analysed from device
top side [10]. In this paper, we report the statistical measures of VB
data and localise the VB spots in normally-off and normally-on
AlGaN/GaN HEMTs on n-type SiC and Si substrates. The cumulative
distribution function (CDF) of VBD values is determined as a
function of device area, substrate and heteroepitaxy. An analogy
with statistics of time dependent dielectric breakdown (TDDB) in
thin gate oxides [11] and off-state degradation of the AlGaN barrier
[12,13] is discussed. The position of VB paths is accurately obtained
by backside infrared (IR) microscopy under DC and pulsed condi-
tions. The mechanisms leading to the initiation of VB are discussed.
2. Experiments
The structures of the investigated devices are given in Fig. 1
and Table 1. Device A is a normally-on HEMT with threshold volt-
age Vth  2.5 V (IDmax = 0.39 A/mm). Its structure is a Schottky-
gate (Ir/Ti/Au) with a 25-nm-thick Al0.25Ga0.75N barrier, and a
2-lm-thick Al0.08Ga0.92N buffer grown on conductive Si substrate.
The Ohmic contact is Ti/Al/Ni/Au/Ti/Pt. Device B is a normally-off
device with Vth  0.5 V (IDmax = 0.35 A/mm). Its structure is a
p-GaN gate with 14-nm-thick Al0.23Ga0.77N barrier fabricated on
a 3.1-lm-thick GaN buffer grown on a conductive n-type SiC
substrate [5]. The Ohmic contact is Ti/Al/Mo/Au. Devices C and
D are test structures with a 13-nm-thick Al0.23Ga0.77N barrier,
with and without a 3-nm-thick GaN cap layer, respectively, and

0026-2714/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved.
http://dx.doi.org/10.1016/j.microrel.2013.07.117
 C. Fleury et al. / Microelectronics Reliability 53 (2013) 1444–1449
Fig. 1. Schematics of a large circular test structure (a), and normally-on (b) and
normally-off (c) devices for vertical breakdown study (2DEG is indicated by green);
(d) schematics of the setup for backside VB spot analysis using a TLP pulser. (For
interpretation of the references to colour in this figure legend, the reader is referred
to the web version of this article.)
with two different thicknesses for the nucleation layer. The statis-
tical behaviour of vertical leakage current and VBD (defined here
as the voltage at current I = 0.1 mA) across the wafer was ana-
lysed in large area circular and more complex two-terminal test
structures with one contact on top (Ohmic contact) and one con-
tact on bottom (back-contacted substrate), see Fig. 1a:
A = 13,105 lm2 for device A, 69,746 lm2 (diameter U = 300 lm)
for B, and 4778 lm2 (U = 80 lm), 17,203 lm2 (U = 150 lm), and
69,746 lm2 (U = 300 lm), for C and D. CDF(VBD) is defined as
the ratio of the number of devices having their breakdown
voltage below VBD to the total number of tested devices on a
wafer. For time-dependent measurements and failure analysis,
the HEMT devices (types A and B, dGD = 2 lm, W = 2  125 lm,
the drain contact length is 30 lm) are contacted by needles
on the drain pad, and by a silver paste on the substrate (see
Fig. 1). The gate and source electrodes of these HEMTs remained
Table 1
Summary of the studied devices and main results.
Device A B
Substrate Si
Normal operation On
Drain bias + +
VBD stat. distr. large structures Normal
No. of modes 1 1
Failure signatures on small HEMTs Channel area Drain + contact pad
1445
floating during the drain contact biasing, so again, the structures
were two-terminal (i.e. one top Ohmic contact and one bottom
substrate contact). Compared to the large area circular devices,
these drain Ohmic contact devices have a much smaller area.
The substrate backside is polished for backside IR imaging using
a microscope objective (50) and an IR camera (see also
Fig. 1c) [14]. IR light, for which Si and SiC substrates are transpar-
ent, is used for backside illumination. For failure analysis, a DC
biasing in current-controlled mode and a pulsed stress biasing
were used. The pulsed IV analysis is performed using a transmis-
sion line pulser (TLP) with 100 ns pulse duration [14]. Notice that
the TLP stress pulse is energetically similar to the human body
model of electrostatic discharge stress [15]. The DC and TLP stress
magnitude in both polarities has been progressively increased
until VB damage became visible from the backside and/or topside.
3. Results and discussions
3.1. Statistical IV analysis
Typical examples of vertical leakage current IVs in voltage con-
trolled mode between the top Ohmic contact and the substrate are
given in Figs. 2a, b, 3a, b and 5a. In positive and negative biases, the
leakage current has different voltage dependence and VB behav-
iour. Potential energy barriers at the 2DEG/GaN buffer interface
(for negative drain), nucleation layer/substrate (for both bias polar-
ities), but also bulk GaN traps can be involved in the transport.
Resistive hopping-like transport, space charge limited currents
and Pool–Frenkel field-assisted conduction via traps have previ-
ously been considered to explain the dependence of the vertical
leakage current on the bias polarity [9,10]. Field-assisted emission
from bulk traps [16] can also be considered. The detailed analysis
of the physical mechanisms of the vertical leakage current, which
can be obtained from temperature dependent measurements
[9,10], is beyond the scope of this paper.
One remarks on the one hand IV curves with high VBD values
and small spreading and on the other hand IVs with lower
(premature) and randomly distributed VBD values. By analogy with
the TDDB terminology [17], we call these breakdown types
intrinsic (i.e. for high VBD) and extrinsic (for premature VB). The
CDFs of VBD values are shown in Figs. 2c, d, 3c–f, 4 and 5b. They
show typically bi-modal (Fig. 3c and d) or sometimes even tri-
modal (with two modes in the extrinsic part, Fig. 4) distributions.
The extrinsic failures indicate a role of large extended defects
(e.g. dislocation related) [8], while the intrinsic ones can indicate
a more homogeneous distribution of simpler (e.g. point) defects.
With increasing of the Ohmic contact area, the probability of
extrinsic failures increases on the expense of the intrinsic ones
(Figs. 3 and 4), since the probability to hit a large defect increases
with the area, similarly as in TDDB of gate oxides [17]. By plotting
the CDF in various coordinate systems we have found out that the
CDF can be of Weibull type in both extrinsic and intrinsic regions at
positive biases in device C (Fig. 4) but it seems to be more normal
(i.e. Gaussian) for device A (Fig. 2d) or more complex for negative
bias voltage (device C, Fig. 3). A summary of the results is given in
C D
SiC, epi1 SiC, epi2 SiC, epi3
Off Off Off
+ +
Weibull (or more complex)
1 2 3 3 3 2
Drain + contact pad
1446 C. Fleury et al. / Microelectronics Reliability 53 (2013) 1444–1449
Fig. 2. IV curves recorded under voltage-controlled mode for negative (a) and
positive bias (b) on the top contact for dev. A. CDF of VBD values for negative bias in
linear scale (c) and in normal coordinates (d).
Fig. 3. IV curves recorded under voltage-controlled mode for negative (a) and
positive bias (b) on the top contact in Dev. D, for the three diameter values. CDF of
VBD values for negative (c) and positive (d) bias in linear scale and in Weibull
coordinates (e and f). The data in the Weibull coordinates shows an area scaling
coefficient [i.e. ln(area2/area1), area2 > area1] in Weibull coordinates in the 0.6–1
range instead of the theoretical value of ln(4)  1.4. The blue and orange ellipses
indicate the intrinsic and extrinsic VB regions, respectively.
Table 1. This indicates different VB mechanisms for different bias
polarities [9], substrates, epitaxies and processes. The possible rea-
son for the Weibull distribution will be discussed in the following
section, since a further study is necessary to analyse the origin of
the other CDF shapes.
3.2. Time to breakdown measurements
Time to breakdown measurements have been performed on
four HEMT structures of the wafer B. The typical drain-to-substrate
leakage current in the small area HEMT device is shown in Fig. 6a.
For comparison, typical IV curves of the complementary circular
large area devices are given in Fig. 5a, showing a linear increase
in the leakage current with the voltage with a large device-to-de-
vice VBD variation. The breakdown voltage values are nearly Wei-
bull distributed (Fig. 5b). One may remark that the breakdown
voltage of the small device is as high as 530 V, while the maximum
VBD of the large devices is about 400 V. Furthermore a strongly
increasing leakage current component is observed at about 450 V
in the small device. The results indicate that the breakdown results
of Fig. 5 can correspond to extrinsic breakdowns (i.e. lower VBD)
while the breakdown of the small device in Fig. 6a is likely related
to intrinsic mechanism.
For the time domain measurements, HEMTs were biased at
fixed voltages at 500 V, 470 V, 400 V and 250 V, and the time evo-
lution of the current was measured. Fig. 6b shows the time evolu-
tion of the vertical leakage current of the device stressed at 500 V.
The current first decreases and stabilises. Then it becomes noisy
and starts to rise. The rise in current is followed by an abrupt in-
crease in the vertical leakage current to a value of about 1 lA
(i.e. soft breakdown). A similar behaviour is observed for the stress
voltage of 470 V with a slightly shorter time to breakdown
(3  103 s). The devices that have been stressed at 400 and 250 V
also exhibited the current decrease and stabilisation phases, but
the pronounced current increase was not observed before one
and two weeks of stress, respectively. The above behaviour is very
similar to degradation of the AlGaN barrier in reverse-bias-stress
experiments [12,13,18]. The decrease of the current with time
can be related to a trapping of electrons in the GaN buffer traps.
The inset of Fig. 6b depicts the situation for positive drain bias,
where the potential barrier for the electron transport from the
SiC substrate across the nucleation layer increases with the capture
of negative charge by the traps. Further, the increase in current and
its noisiness indicates creation of new traps [12,13,19]. We con-
sider that new traps are preferentially created at the positions of
pre-existing extended defects related to dislocations. When a crit-
ical density of traps is created, a percolation leakage path is formed
[12,13]. Diffusion processes [20,21] from the drain contact or
nucleation/substrate region may also play a role in the acceleration
of the VB. The percolation mechanisms is supported by the obser-
vation of a Weibull distribution of breakdown voltage values (see
e.g. Figs. 4 and 5) and (even if not-perfectly scaling) area depen-
dence of CDF distribution (see Figs. 3 and 4 and Ref. [17]).
Our results in Fig. 6b indicate that a higher stress voltage seems
to shorten the time to breakdown, similarly as in [12,18]. However,
a more systematic study, which would take into account the possi-
ble statistical distribution of time to breakdown values [12] and
their relation to the intrinsic or extrinsic breakdown mechanisms
[17], is necessary to investigate this effect. We also do not know
whether the intrinsic and extrinsic mechanisms are independent,
or the extrinsic breakdown is only an accelerated intrinsic VB. It
should also be established whether the VB mechanism is related
to a particular leakage current component (e.g. strongly increasing
current component, such as that for VDSub > 450 V in Fig. 6a). We
believe that the temperature dependence of the IV curves and of
the VB statistics can give an answer.
At this place we would like to comment on a possible relation
between the statistical distribution of the VBD values and the time
to breakdown behaviour. The time to breakdown concept is taken
from the TDDB analysis where the time to breakdown is a dynamic
random variable which is Weibull-distributed [11,17]. But here we
observe a Weibull distribution in breakdown voltage values, where
 C. Fleury et al. / Microelectronics Reliability 53 (2013) 1444–1449
Fig. 4. CDF of VBD values for positive bias in linear scale (a) and in Weibull coordinates (b) in Dev. C, for the three diameter values. The blue and orange ellipses indicate the
intrinsic and extrinsic VB regions, respectively. (For interpretation of the references to colour in this figure legend, the reader is referred to the web version of this article.)
Fig. 5. IVs (a) and CDF of VBD values for positive bias in Weibull coordinates (b) in
Dev. B.
Fig. 6. (a) Vertical IV of HEMTs under voltage-controlled mode. The arrow indicates
the initial points of the TTB measurement. (b) Evolution of the vertical leakage
current at 500 V. Inset: Band diagram for a positive drain-to-substrate bias, with
negative charging of traps and creation of new defects, eventually leading to the
creation of a percolation path.
VBD is a ‘‘static’’ random variable. We therefore consider that dur-
ing the device processing, or even during the epitaxial growth,
there might be a time dependent, but at this stage nonbias-depen-
dent, process (like defect clustering and defect diffusion) which can
1447
Fig. 7. DC IV on silicon substrate (device A) in current-controlled mode (a) and
resulting damage from bottom (b) and top (c).
set an initial distribution of defects, which are revealed by the
vertical leakage IV measurements. The distribution of VBD values
can thus be a fingerprint of such an initial defect distribution.
The application of prolonged constant bias can furthermore
activate the pre-existing defects or create new defects, leading to
the observed time dependent breakdown behaviour.
3.3. Localisation of breakdown spots
In order to visualise the VB damage, we performed failure anal-
ysis. First of all, we would like to notice that, in principle, there can
be differences between the details of failure signatures in large cir-
cular devices and small HEMT devices, as the small devices can
exhibit preferentially the intrinsic breakdown. For full understand-
ing of multi-modal nature of CDFs, it would therefore be necessary
to correlate the breakdown voltage values to particular failure sig-
natures, but this is beyond the scope of this work. The failure
analysis was therefore performed only in a limited number of
HEMT devices. Furthermore, we would like to point out a differ-
ence between the areas which are active in normally-on and
normally-off devices: In the former case the whole mesa area can
be active as 2DEG exists there (see Fig. 1b), whereas in the latter
case, the 2DEG is interrupted under the gate, so a smaller area is
active (see Fig. 1c).
Our main observations, which are valid both for devices on Si
and SiC substrate (dev. A and B), are summarised in the following
(see also Table 1). The VB spots can be distributed randomly inside
the drain contact area, but it can also be visible in the drain pad
area in Si dev. A. A DC current stress creates damage in areas as
wide as 10 lm (Fig. 7b). It is characterised by a sudden jump-down
in voltage, seen in the IV curve recorded in current-controlled
mode (Fig. 7a). This damage can also be visible from the top side
(Fig. 7c). Applying prolonged current in the already damaged area
can further enhance the defect laterally. We suggest that the
visible damage is due to metal degradation at the position of a
1448 C. Fleury et al. / Microelectronics Reliability 53 (2013) 1444–1449
Fig. 8. TLP voltage waveform for a non-destructive pulse (1) and during the
destruction (2) of device B (SiC substrate) (a) and resulting damage from backside
before (b) and after (c) additional DC stress.
GaN-related extended defect where a large energy is deposited.
Even if the total current is limited in this mode, the current density
in the current filament can be large since, at the breakdown, the
device enters the region with a negative differential resistance
with a tendency to current filament formation [22,23]. The
filament can be pinned at the position of an extended defect. The
second effect is that, as the voltage snaps back, a large charge from
connecting coax cables is discharged to the device, which can also
help creating a relatively large area defect in the metallisation,
similarly as in Ref. [10]. A TLP stress produces damage with a smal-
ler area, allowing localising the current path with micrometre
accuracy. Since a TLP stress produces less severe damage
(Fig. 8b) than a DC stress (Fig. 7b and c), the damage it makes
can sometimes only be observed from the bottom. The curves 1
and 2 in Fig. 8a show the transient voltage of a non-damaging
and a damaging pulse, respectively. The creation of the damage
is correlated with a transient voltage decrease during the TLP
pulse, indicating the creation of a permanent low resistance path
(Fig. 8b). A VBD in pulsed operation is often higher than a VBD
observed under DC conditions, which is consistent with the results
of Fig. 6b. Both the above-mentioned trap-related and self-heating
effects can be considered. The breakdown spot created by a TLP
stress can be enlarged furthermore by a prolonged operation in
the DC mode (i.e. post-stress mode, Fig. 8c), being consistent with
the DC observations where the input energy and therefore the
cumulated thermal damage is higher.
Finally, a possible role of the self-heating effect in initiating
permanent damage under the DC conditions was evaluated using
a finite element thermal simulation in cylindrical coordinates. An
infinitesimally thin (i.e. a zero order, worst-case estimate) circular
heat source with a 1 lm radius located at the top of a 3 lm thick
GaN buffer was considered and the top metallisation and AlGaN
layers were neglected. Adiabatic boundary conditions were set
on lateral and top sides, and the bottom side of a 600 lm thick
SiC substrate was set as an ideal heat sink. A thermal boundary
resistance of 4  10 8 m2 K/W and temperature independent
thermal parameters of GaN and SiC were taken [24]. The results
indicate that for a typical power of 50 mW (i.e. 0.1 mA  500 V)
the maximum temperature rise above room temperature can reach
about 130 °C. This indicates that the thermal effects could acceler-
ate the VB in DC measurements, at least for the case where the
substrate leakage current reaches the value of 0.1 mA before the
breakdown. However, for better temperature estimation we will
need to know more exactly the lateral and vertical extent of the
power dissipating region.
4. Conclusions
Our results suggest that the statistical analysis of VB data can
give specific information on the VB mechanism and could be used
to characterise material quality and process technology. A time to
breakdown behaviour has been found in VB. Together with the
time to breakdown behaviour in the degradation of III-nitride
barriers [12,13], TDDB of GaN MIS HEMT dielectric stack [25] and
TDDB of SiN passivation layer [26], this is yet another observation
of time to breakdown behaviour in GaN based HEMTs. The failure
analysis revealed that the VB path is highly localised, confirming
the role of extended defects and the filamentary nature of the
current at failure. Pulsed stress provides a better localisation of
the failure. The similar VB signatures in both studied device types
indicate the similar nature of the buffer extended defects, although
the GaN layers are grown on different substrates.
Acknowledgments
This work was performed within EU Project HiPoSwitch (Grant
agreement no. 287602) and supported by EU.
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