pont gag Maestro-2™ 1" \ Ih far aro ald PCI Audio Accelerator ESS Technology, Inc. Data Sheet DESCRIPTION FEATURES The Maestro-2™ digital audio accelerator is a highly integrated PCI audio solution that brings advanced audio features to notebook and desktop systems. These features include a 64-voice wavelable synthesizer with Downloadable Sample (DLS) and complete DirectSound™ acceleration. The Maestro-2 proprietary technology supports both Microsoft®’s PC97 and PC98 logo requirements and DOS game compatibility. ‘The Maestro-2 device works with any AC'97 compliant CODEC including ESS Technology's own ES1918 AC'97 CODEC. ‘The dual-audio engine Maestro-2 architecture consists of a 64-voice pipelined wavetable synthesizer and a proprietary audio signal processor. Together they can simultaneously handle multiple audio streams of different data types, high quality MIDI synthesis, and voice compression and decompression. Each channel/stream has an independent an, tremolo, vibrato, and tone filter. The synthesizer also performs advanced audio effects such as reverb, chorus, treble, bass, flange, echo, and 3-D spatial enhancement WaveCache™ technology reduces the system cost by storing data (synthesis samples, WAV files, algorithms) in host memory. The data is retrieved using high-speed PCI us cycles during playback or recording. Microsoft's DirectSound API is accelerated by digitally mixing as many as 32 PCM streams of any frequency down to a single output stream of 48 kHz. This “final” buffer can then be piped to any CODEC available to the system. This acceleration frees up the CPU to perform other tasks. ‘The Maestro-2 audio accelerator supports a number of different legacy audio schemes, including Distributed DMA protocol, PC/PCI DMA, and Transparent DMA. This ensures complete DOS game compatibility over the PC! bus. ‘The Maestro-2 power management complies with ‘Advanced Power Management (APM) 1.2, Advanced Configuration and Power Interface (ACPI) 1.0, and PCI Power Management Interface (PPMI) 1.0. ‘The Maestro-2 audio accelerator is available in an industry standard 100-pin Thin Quad Flat Package (TQFP). ‘+ 500-MIPS-equivalent processor performance to accelerate mult-stream PC audio + 64-Voice wavetable synthesizer ‘+ Proprietary WaveCache technology ‘+ HRTF 3-D positional audio under DirectX™ 5.0 + Enhanced effects (reverb, chorus, echo, vibrato, etc.) ‘+ Distributed and PC/PCI DMA, Compaq*/intel® serial IRQ support and Transparent DMA + AC-8 speaker virtualization ‘+ 2-Button hardware master volume control ‘+ FS/Zoomed Video support + AC97 CODEC interface ‘+ Upto 20-bit ADC/DAC audio resolution ‘+ Complies with Microsoft's ACPI 1.0 and PPMI 1.0 (D0~D3) ‘+ 3.3 V power supply, 5 V — input tolerant ‘+ Supports up to 12 GPIO pins ‘+ Secondary CODEC interface + 100-Pin TOFP package BENEFITS ‘+ High-Performance audio ‘+ High-Speed PC! bus cycles when accessing data stored in system memory ‘+ Highest performance engine for DirectSound acceleration ‘+ Enhanced sound images, product differentiation ‘+ Ensures complete DOS game compatibility regardless of core logic legacy support + Scalable for high-end, high-fidelity audio ‘+ Adjusts volume independent of applications ‘+ Zoomed Video MPEG audio playback application ‘+ Flexibility in layout ‘+ Supports OnNiow, Microsott’s design initiative for power ‘management ‘+ Optimal power saving and simplified layout ‘+ Flexibiliy for system management schemes ‘+ Small real estate for economical notebook design ESS Technology, Ine, ‘SANO056-102997 7MAESTRO-2 DATA SHEET ‘CONTENTS CONTENTS DESCRIPTION 1 ASSP 1/0 Mapping 22 FEATURES 1 DMA Contiol Registers... 22 BENEFITS 1 Data Transfer Between ASSP and Host Memories |... 23, MAESTRO-2 BLOCK DIAGRAMS. 3 32-Bit VO Transfer Operation 23 PINOUT 5 DMA Transfer Operation 23 PIN DESCRIPTION 6 Messaging Between the CPU and the ASSP ..... 23 STRAP SELECTED OPTION 8 ASSP Interrupts 24 MULTLFUNCTION PIN ASSIGNMENT 8 VO PORTS 25 FUNCTIONAL PIN GROUPING 9 Port Summary 25 POWER MANAGEMENT 10 Port Descriptions 26 CLKRUN Protocol 10 ELECTRICAL CHARACTERISTICS. 32 PGI Power Management interface (PPI) 10 ‘Absolute Maximum Ratings 32 ‘ACP! Transition Diagram 1 Operating Conditions 32 DISABLING MAESTRO-2 AUDIO 11 POWER MANAGEMENT CHARACTERISTICS 32 PCI CONFIGURATION REGISTERS 12 TIMING SPECIFICATIONS. 33 Register Summary 12 ‘AG-Link Timing Specifications 33 Rogister Descriptions 13 ‘AC-Link Timing Diagrams 33 WAVECACHE 19 ‘AC-Link Timing Characteristics 35 ‘Applicable Registers 19 PCI Bus Timing Specifications 36 WaveCache Configurations 19 PCI Bus Timing Diagrams 36 WaveCache Acooss 19 PCI Bus Timing Characteristics 38 Programming the WaveCache 20 PS Port Timing Specifications 39 CODEGIMIXER INTERFACE 21 PS Port Timing Diagrams 39 ‘Applicable Registers 21 FS Port Timing Characteristics 39 ‘AC97 Interface 21 MECHANICAL DIMENSIONS. 40 AC'97 Serial Interface Timing 21 APPENDIX A: SCHEMATIC EXAMPLES 4“ APPLICATION SPECIFIC SIGNAL PROCESSOR 22 APPENDIX B: BILL OF MATERIALS 45 Applicable Registers 22 [ASSP Memory Mapping 22 FIGURES Figure 1 Maestro-2 Block Diagram 3 Figure 14 PCI Clock Timing 36 Figure 2 Wave Processor Portion 4 Figure 15 PCI Bus VO Read Cycle 36 Figure 3 Maestro-2 Pinout 5 Figure 16 PCIBus VO Write Cycle 37 Figure 4 ACPI Transition Diagram 11 Figure 17 PCI Bus Master Request a7 Figure 5 AC-Link Diagram 21 Figure 18 PCI Bus Master ReadiWrite Cycle 38 Figure 6 Serial Interface Timing 21 Figure 19S Port Timing 39 Figure 7 ASSP Interrupt Map 24 Figure 20 Maestro-2 Mechanical Dimensions. 40 Figure 8 Cold Reset 38 Figure 21 Maestro-2 Schematic 41 Figure 9 Warm Reset 83 Figure 22 CODEC Interface 42 Figure 10 Clocks 83 Figure 23 Host PCI Interface 3 Figure 11 Data Setup and Hold... 34 Figure 24 CDIMIDISection . 44 Figure 12 Signal Rise and Fall Times 34 Figure 13 AC-Link Low Power Mede Timing 34 TABLES Table 1 Power-Management Registers 10 Table 10 ASSP Interrupts . 24 Table 2 PCI Configuration Registers Summary 12 Table 11 Maestio-2 VO Port Summary 25 ‘Table 3 Supported Legacy Audio Addresses 15 Table 12 Digital Characteristics 32 Table 4 WaveCache Indexed Data Registers 19 Table 13 Current Consumption 32 Table 5 WaveCache Top Channel and Physical Address ...20 Table 14 AC-Link Timing Characteristics 35 Table 6 PCM Top Channel and Physical Address 20 Table 15 PCI Bus Timing Characteristics 38 Table 7 ASSP Memory Mapping 22 Table 16 °S Port Timing Characteritios 39 Table 8 ASSP VO Mapping 22 Table 17 Bill of Materials (BOM) 45 Table 9 ASSP Address Map 23 2 ‘SAMOOS6-102097 ESS Technology, IneMAESTRO-2 DATA SHEET MAESTRO-2 BLOCK DIAGRAMS. MAESTRO-2 BLOCK DIAGRAMS System ORAM Chipset cpu aavecr WaveCache SBI legacy audio ‘ROPITO PPMITO é-Channel Wave Processor AC-Link #1 Effect synth DSP intertace Poi sus Digital mx sample rate conver 48K, sav ‘Game port Butler Mgr Control register HW volume MPU-401 Tuaio| signal processor Multiple CODEC] Interface lang, srs covec| OM RAM ESS Technology, Ine, Maestro-2 PEG nuso Avalghiajystck Votup. ot down, mate Figure 1 Maestro-2 Block Diagram ‘AC'97 CODEC ses) Mein ‘Aue (00 a) ‘nue 2 DVD) ‘Ave gs V4 Phos Hesdeet out ‘SANO056-102997 aMAESTRO-2 DATA SHEET MAESTRO-2 BLOCK DIAGRAMS pci |. | Wave Wave covec Interface Cache Looping Interface Command FIFO ¥ 64 Streams Multi-stream Interface Source AP |Emeleney Am) itor JP ots or eases Figure 2 Wave Processor Portion ‘SAMOOS6-102097 ESS Technology, IneMAESTRO-2 DATA SHEET PINOUT PINOUT apis / Pcants #Biepios s iscrk eEaarion / sinae DOT OOOO TOO ScLKt SOFSt soit spi Txo Maestro-2 4 100-Pin TQFP a anise aouc] DOU gee Figure 3 Maestro-2 Pinout @Pios / voLuP GPIo4 / VOLON GPIO3/ ILA GPIO2 / 101 GPIO1 / 100 GPI00/ ISCLK GND CLKRUNE PME® GND ADO Apt ‘aD2 ‘ADS. ADA ‘ADS ‘ADs. AD7 veo ciBeor ADs ‘AD AD10 anit AD2 ESS Technology, Ine, ‘SANO056-102997MAESTRO-2 DATA SHEET PIN DESCRIPTION PIN DESCRIPTION Name Number _| VO | Defition GIBE[:0}#| 1,13.21.37 | VO | Multplexed commandibyie enable, These pins Indloate cycle type during the address phase of @ transaction. They indicate active-low byte enable information for the current data phase during the data phases of a transaction. These pins are inputs during slave operation and ‘outputs during bus mastering operation TOSEL 2 T [1D select, active-high. This pin is used as a chip select during PGI configuration read and write cycles. ‘ADISTO} | 92:99,4:11, | VO | Matiplexed address and data fines 23:30,33:40 FRAMER 14 | VO | Cycle frame, activelow. The current POI bus master dives this pi to indicate the Beginning and duration of a transaction. TROY 15 | UO | Instr ready, actve-low. The current PCI bus master drives ths pinto indicate that as the initiator itis ready to transmit or receive data (and complete the current data phase). TROVE 16 | 00 | Target ready, acive-low. The current PCI bus master drives tis pln to indeate that as the target deviee itis ready to transmit or receive data (and complete the current data phase), DEVSELF | 17 | 10 | Device select, active-iow. The PCI bus target device dives this pinto indicate that has decoded the address ofthe current transaction as its own chip Select range. STOP# 18 | VO | Stop transaction, activevow. The current PGI bus target dives this pin active to Indicate @ request tothe master to stop the current transaction, Locke 19 | ¥O [Look PAR 20 | VO | Parity, active-high. This pin Indleates even pariy across AD[ST-0] and GIBE[S:0}# for both address and data phases. The signal is delayed one PCI clock from either the address or data phase for which patiy i generated. PMER @__| © [Power management enable intrrupt output t wake up the systom GLKRUN® | 43 __| 10 | Input for cock status and output o starlspeed-up clock Gpioo TO | Dua-purpase pin. GPIOO Is general purpose inpuloutput 0. Selected by 7 Macstro2_Base+68h/11:0} Iscuk | ISCLK's the serial shift clock for the DSP serial interface. Selected by setting PGI S2h(4] = 1 and Maestro2_Base+36h(15) 1 al TTO | Duatpurpose pin. GPIOT is general purpose inpwoutput 1. Selected by 6 Maestro Base v68n(t:0) i © | 100 isthe serial data output forthe DSP serial interface. Selected by seting PCI S2H@] = 1 and Maestro2_Bases36h(15] =1 TO | Dual purpose pin. GPIO2 is general purpose inputloutput 2, Selected by Plog a Maestro2_Base+68h(11:0), ol T | IDIis the serial data input for the DSP serial interface, Selected by setting POIS2h(4)= 1 and Maestro? Base+36h( 15} = 1 ean TO | Dual purpose pin. GPIO3 is general purpose inputoutput 3, Selected by e Maestro Base v68n(t 1:0) 14 [ILRI the frame syne signal for the DSP serial interface. Selected by setting PCI S2h(4] = 1 and Macstro2_Base+36h(15] = 1 TO | Dua purpose pin. GPIOM is general purpose inpuVouiput 4. Selected by Cie ‘es Maestro Bases68n(1 1:0) VOLDN T | VOLDN is a volume decrease input, Selected by sating PCI S2H{7'5] t 1x0, Alternatively, the VOLUP/VOLON pair at pins 73 and 74 may be used. é ‘SANO056-102097 ESS Teshnoogy, neMAESTRO-2 DATA SHEET PIN DESCRIPTION iS Name Number _| VO | Definition GPIOS WO | Dua-purpose pin. GPIOS is general purpose inpuoutput 6. Selected by 0 Maestro2_Bases6sh11:0) vowuP T | VOLUP is a volume increase input Selected by setting PCI S2N(7'5]to 1x0. Altematively, the VOLUP/VOLDN pair at pins 73 and 74 may be used. ene , VO | Dust pupere pr GPIG i gereral pupse nputoupit 6 Sete by IScLK TJ ISGLK (FSGLK) isthe FS serial lock, Selected by setting Maestio2_Base+36h(15] = 1 (PSCLK) = . 1 | Buaipupere pr. GPIT is gereral pups npuoupit 7. Sted by LR T_JIUR (PSLRA) ie the FS frame eye, Selected by setting Maestro2_Bases36h(5) = 1 (SLR) —— . 1 | Dus gupose a: GPK i general pups mp 8. Selcnd by IDATA T_JIDATA (FSDATA) Is the FS data input pin. Selected by setting Maestro2_BasevS6h[16] = 1 (ESDATA) ‘soz 55 [VO | Serial data out. Strap pin (with Internal pull-up): 1 = AG-link #2; 0 = Multi CODEC interface. ‘S02 6 1 | Serial data i, SDFS2 a © | Serial data frame syne. ‘SOFS3 38 (© | Serial data frame syne. SOLI2 59 | VO | Serial data clock. Output pin when the mult-CODEC interface is used. Input pin when the AC- link #2 interface is used. Sees co puipupese pn GPIB is genera puposenpuveupu 8, Sci by POGNT# |_| PCGNT# is the PCIPCI grant input. Selected by setting PCI 50h 10:8] = 010. a on 1 | Dus upone ps GPO'0 i gerera prose Mpaupu 10 Selec POREGH (© | PGREGI# is the PCIPOI request output Selected by setting PCIS0R[108] = 010. a VO | Dual-purpose pin. GPIOTt Is general purpose inputloutput 11. Selected by 62 Maestro2_Base+68h(11:0) siRo# VO | SIRG#is the serial interrupt request, Selected by setting PCI 40h(14] osci Cy [49.182 oF 60.000 MHz crystal input. Refer to the Maestro-2 reference decign for an update. ‘O8CO 6 (© [49.152 oF 50.000 MHz crystal output Refer to the Maestro-2 reference design for an update DIS] 70:67 _| VO | Game port data G05) 7271 |__| Game por data Gos T_ | Dual purpose pin. GD6 is a game port data input pin oie 73 |” | VOLUP isa volume increase input. Selected by setting PGI S2h(7'5] = 1x1. Alternatively, the VOLDN/VOLUP pair at pins 49 and 50 may be used. Gor T_ | Dual-purpose pin. GD7 is a game port data input pin pote 7% T | VOLDNis a volume decrease input. Selected by setting PCI S2h{7:5] = txt. Atematively, the VOLDNIVOLUP pair at pins 49 and 50 may be used. ‘SCLKT 76 | Serial clock tn AC'97 configuration, this pin is an input which drives the timing for the ACS? Interface. ‘SOFSi 77 © | Serial data frame sync. In AGS7 configurations, this pins an output which indicates the framing for the AC'97 link, Son 8 [Serial audio data input ESS Technology, Ine, ‘SAMO056-102907 7MAESTRO-2 DATA SHEET ‘STRAP SELECTED OPTION Name Number _| 10 | Definition SDOt 78 © | Serial audio data out, TxD © | MIDI wansmit data XD at 1 [MiDIreceive data C24 Ey (© | 24.576 or 25,000 MHz clock output depending on the XTAL input. For CODEC clock source. RSTe a 1 [Reset INTE 6 © | Interrupt request, active-low. This pin isthe level triggered interrupt pin dedicated to servicing Internal device Interrupt sources. PCICLK 7 T_ | POl bus clock This clock times all POI transactions, All PCI synchronous signals are generated and sampled relative tothe rsing edge ofthis clock GNT# Ey | Bus master grant, acive-low, The system arbiter drives this pinto Indicate to the device that access to the PCI bus has been granted REQH 0 (© | Bus master request, active-low tri-state output Ths pin indicates to the system arbiter that this device is requesting access to the PCI bus. This pin must be trstated when RST is active. vec’ 12,32,54,66, | Pwr] +33 vols. 86,100 GND [3.22,41,44.6| Pwr | Grouna, 3,75,88,91 STRAP SELECTED OPTION Pin Name | Pin Number] Default State at Reset | Condition | Description ‘SDO2 55 Pullup Tow | Multiple CODEC interface Is enabled for pins 59:55 (SCLK2, SDFSS, SDFS2, SDI2, $002) High | AG-Link #2 interface is enabled for pins 69:55 (SCLK2, SDFSS, SDFS2, SDI2, SDO2), MULTI-FUNCTION PIN ASSIGNMENT Function Pin Names | Pin Numbers | Selection Settings DSP Serial interface ISCLKIDOJIDLILR [48:45 | PCIS2h[4) = 1 and Maestro2_Bases36h[15]=1 General-Purpose Interface | GPIO[I1.0] _ | 62:60,53:45 | Maesvo2_Base+ésh(t 10) Hardware Volume Control |_VOLUP,VOLDN 50.49__| POISan{7:6] = 1x0 VOLUPVOLDN 7374 __ | POIS2h7-5]= txt FS Interface TSCLKILRIDATA | 5851 __| Maesto2_BasexS6h{15] Legacy Audio interface | POGNT#POREG#| 61:60 | PCIS0n[108) = 010, SIROH @ PGI a0n(t4]= 1 a ‘SAMOOS6-102097 ESS Technology, IneMAESTRO-2 DATA SHEET FUNCTIONAL PIN GROUPING FUNCTIONAL PIN GROUPING iS Function Fins | Pin Number Function Pine _[PinNumber] [feneten ee te Me PCI Bus Pins IDSEL 2 a " interface Soe se ADp1o) | 9090457, 23:90,83:40 SOFS2 57 orBesoy# | 1.192131 ‘SOFSS 58 FRAMER 1 SCLK2 59 roe is Coax Osi ei TROVE 16 ‘Osco 65 DEVSELF 7 C2 83 Sree a Game Port interface ojo) | 7087 Toc i Gos) |_7a71 PAR 20 G08" 73 CLKRUNE 8 eo7* 74 Ret a Tlardware Volume ContoiPins[VOLDN™ | 49,74 ie 5 vouur* | 5078 POLK a FS ineace iSCLK 31 (rscuK)* NT 8 UR w — 9° (SLR) AGPIPIn PMER 2 a Ss Legacy Audio Inierace PcGNT#™ | 60 (ESDATA)* POREGH | 6t DSP Serial interface ISCLK™ % SIROF @ Do" «6 WPUAOT invertace XD 30 or" a7 RxD. ai ue 4 General Purpose VO Pins [GPIOO™ w Power Fins voc 700,88,58, aE a 54,32,12 oon a Guo [91.88.7568 4443.23, GPIOS. 48 “These pins share more than one function. GPIOe 2 GPIOS™ 2 GPIOS™ 5 GPIOT 2 GPios 3 GROOT 5 aroi | 6t aro [|e CODEC H Interface SCLKI 76 SOFSI 7 Sor 72 S001 73 ESS Technology, Ine, ‘SANO056-102997MAESTRO-2 DATA SHEET POWER MANAGEMENT ‘The Maestro-2 is a high-performance device with low power consumption. Besides the low-power CMOS technology used to process the Maestro-2, various features are designed into the device to provide benefits from popular power-saving techniques. These features and techniques are discussed in this section. CLKRUN Protocol The PCI CLKRUN feature is one of the primary methods ‘of power management on the PCI bus interface of the Maestro-2 for the notebook computer. Since some chipsets do not implement CLKRUN, this is not always available to the system designer, and alternate power- saving features are provided PCI Power Management Interface (PPM) The PCI Power Management Interface (PMI) specification establishes the infrastructure required to let the operating system control the power of PCI functions. This is done by defining a standard PCI interface and operations to manage the power of PCI functions on the bus. The PCI functions can be assigned one of five power management states that result in varying levels of power savings. The five power-management states of PCI functions are: + D0—tull power + D1 and 02 — intermediate states * D3 hot ~ off state; power supply is on * D3 cold — off state; power supply is off POWER MANAGEMENT For the operating system to manage the device power states on the PCI bus, the PCI function should support four power-management operations’ capabilities reporting power status reporting setting the power state system wake-up ‘The operating system identifies the capabilities of the PCI function by traversing the new capabilities list. The presence of new capabilities is indicated by setting bit [4] in the PCI Status register and providing access through a capabilities pointer to a capabilities list. ‘The capabilities pointer provides access to the fist item in the linked list of capabilities. For the Maestro-2, the capabilities pointer is mapped to an offset, COh, indicated in the PCI Configuration register at 34h, The first byte of each capability register block is required to be a unique ID of the capabilly. PCI power management has been assigned an ID of Oth. The next byte is a pointer to the next pointer item in the list of capabilities. There are no more items in the list, so the next lem pointer is set to zero. ‘The registers following the next item pointer are specific to that function's capability. The PPMI capability implements the register block outlined in Table 1 The Power-Management Capabilities register (PCI Configuration register C2h in the Maestro-2) is a static read-only register that provides information on the capabilities of the functions related to power- management, The Power-Management ControlStatus register enables control of power-management states and enables and monitors power-management events. The Data register is an optional register that displays state- dependent power measurements such as power consumed or heat dissipation, Table 1_Power-Management Registers Register Name Offset Power-Management capabilities Next-Rem pointer Capability 1D 0 Data PMCSR bridge support extensions Power Management conto! status (CSA) 0 ‘SAMOOS6-102097 ESS Technology, IneMAESTRO-2 DATA SHEET DISABLING MAESTRO-2 AUDIO ACPI Transition Diagram power-on reset Figure 4 ACPI Transition Diagram DISABLING MAESTRO-2 AUDIO To disable Maestro-2 audio in both notebook and motherboard implementations: 1. Set PCI O4nf2:0] = 000. This disables Maestro-2 response to all inputs and outputs and Bus Master cycles. 2, Set PCI 40h{7] = 1. ‘This disables Maestro-2 response to all legacy audio functions. ESS Technology, Ine, ‘SAMO056-102907 7goc MAESTRO-2 DATA SHEET arma? PCI CONFIGURATION REGISTERS PCI CONFIGURATION REGISTERS Register Summary Table 2_ PCI Configuration Registers Summary 2F 20_1F oO] oftset Device 1D Vendor ‘oh Device capabiiy Sate Command fh Base case code Subcaee code Programming interface eniter Revision 1D ah BIST capabiliy Header pe Taleney timer Cache Tne se OC Fesenved ‘Maesto2 10 space base address 10m) 1a 13m ich 2h 2h 2h ‘Subsystem 1D (RW protected) ‘Subsystem vendor 0 (IW pratocod) 20h Fesened 30h Fesened Gapabiy painter 3h ah Wacker Win art Trierupt pin Trierupt ine 3h Pesenved Legacy audio contol ah Fesered Reserved aah Reserved Reserved ah Reserved Reserved oh Mavato-2 configuration B Macsto-2 configuration A 30h Feserved ‘ACPI coniral eh Reserved Reserved 3h Reserved Reserved 30h Reserved Distributed DA 0h Power Management capabliies Next fem porter Gapabiiy 1D Goh Fesered Power Management conraltatus Ci “ilveserved localons are read-only wih & delaull value of Zev 2 ‘SAMOOS6-102097 ESS Technology, IneMAESTRO-2 DATA SHEET PCI CONFIGURATION REGISTERS: Register Descriptions Vendor ID (00h, Oth, R) Vendor 0 wunenwee7 6s 49270 Bit Definitions: Bits Name Description 15:0 Vendor ID. identifies ESS as the manufacturer ofthis device. The ID for ESS is 125Dh. Device ID (02h, 03h, R) Device 1D 15/2 4}: 19 512/108 1 oetal=a7gu ofS uraioes oles Bit Definitions: ‘Bits Name Description 15:0 Device 1D Identifies Maestro-2 as this device. This 1D 1968h is assigned by ESS Technology, Inc Command (04h, RW) of e pole]. [a [ws |] 768 43a 10 Bit Definitions: Bits Name Description 73 = Read-only, Returns O when read 2 BM Bus Master enablecisabie ‘= Enable bus master. 0-= Not bus master. 1 MS. Memory Space aocess enablelcisable 1 = Enable memory space access. 0. Disable memory space access 0 10 tO Space access enablelisable 1 = Enable 10 space access. 0 Disable YO space access Status (05h, R) Bit Definitions: Bits Name Description 70 ~ Read-only. Returns 00h when read iS Device Capability (06h, 07h, R) Device capably we s8765 4327 0 a 2H Bit Definitions: ‘Bils Name Description 180 DC ‘The device capabilty code is 0290h, Revision ID (08h, R) Revsion 1 7 6 8 4 #3 2 7 0 Bit Definitions: Bits Name Description 70 Revision ID. Identifies the revision ofthis device. The ID (00h is assigned by ESS Technology, Inc. Programming Interface Identifier (09h, R) Programming interlace enifer 7 6 58 4 #3 2 1 0 Bit Definitions: Bits Name Description 7.0 Pll Kdentifes the programming interface ofthis device. ‘The ID Ooh is assigned by ESS Technology, Inc. 2 a default interface. Sub-Class Code (Ah, R) Sub Gass code 7 6 8 4 38 @ 7 0 Bit Definitions: ‘Blts Name Descriotion 7:0 SCC _ Identifies the type of sub-class ofthis device. The ID Oth is assigned by ESS Technology, Inc. as an audio device, Base Class Code (Bh, R) Base dase code 7 6 8 4 3 2@ 7 0 Bit Definitions: Bits Name Description 7:0 BCC identifies the type of base class ofthis device. The ID 04h is assigned by ESS Technology, Inc. as a multimedia deve. ESS Technology, Ine, ‘SANO056-102997 73MAESTRO-2 DATA SHEET PGI CONFIGURATION REGISTERS Cache Line Size (0Ch, RAW) Subsystem Vendor ID (2Ch, 20h, R) Bk Definitions: Bk Definitions: ‘Bits Name Description Bits Name Description 70 CLS ldoniis the cache ne size ofthis dviee as 00h. 1510 SVIDReadiwite protected, Customizable trough register programming Latency Timer (00h, RW) Witabie when PCI S040 Cateye a 76 5 @ 3 2 1 9 SubeystemiD___ en, 2Fh R) Bt Definitions: Bunanwes7Tesesaio Bits Name Description 74 Number of clocks times 16. eee 30 — Read-only. Returns 0 when read. ‘Bis Name Description 150 SID Readiwite protected Customizable through Header Type 0En, F register programming aye ( ) ‘Writable when PCI 50h(0] SH Saturation ape ayo sf e 7 z a zs a i Capability Pointer (34h, R) Bit Definitions: L____Gapabitty pointer___ a a so 7 SM Singlesmukifunction device, The Maeste-2 gu Definitions: supports single funtion operation 0 = Single-function device. Bits Name Description 6:0 CSL Configuration space layout. Read-only. Defines 70 CP _ This register provides a pointer into the PCI con. layout for bytes 10h and up of the PCI configura- figuration header where the PC! power manage- tion space header. Maestro-2 supports a 00h ‘ment register block resides. PC! header race ovolewords at COh and Ch provige the power management (PM) registers. Each socket has sown capably potter register. Tis registers BIST: Cepebalty) (OFh, R) read-only and retums COh when read. Salen ao capa a 6 5 cS 3 2 1 a Interrupt Line (3Ch, RIW) Bit Definitions: Interrupt fe ‘Bits Name Description 79 BIST Bultin st test capabiy i 00h, poy Maestro-2 1/0 Space Base Address (10h, 11h, RW) —_—*BlS. Name Description 79 IL eteruptine outing information. nates which JOsB[15:8) ojojojojojo}o jist ‘system interrupt pin the Maestro-2 is connected Bit Definitions: Bils Name Description 15:8 IOSBI15:8] VO space base address. 256-Byte UO space. to, The POST software writes the routing infor- ‘mation to the Interrupt Line register as the sys- tem is intalized and configured. The value in this register depends on the system architec: ture. In x86-based PC systems, the values of 0 to 15 correspond with IRQ numbers 0 through 7A = Reserved, Always write 0. 15, and the values from 16 to 254 are reserved. 0 Is VO space indicator. Hardwired to 1 The value of 255 (Maestro-2's default power-up vvalue) signifies either “unknown” or "no connec tion” for the system interrupt The default value is FFh. Bits [4:0] are read write. Bits [7:5] = bk (4). % ‘SAMOOS6-102097 ESS Technology, IneMAESTRO-2 DATA SHEET PCI CONFIGURATION REGISTERS: iS Interrupt Pin (30h, R) Bits Name Description Torun 718 DMACH Sound Baster DMA channe! select. 7 e348 BL7 Bit@ DMA Channel Selecton 0-0 Channel BI Definitions: 0 1 Chane (deauty : 1 0 Reserved Bits Name Description 14 Channel 3 7.0. IP Intemuptpin information Indeates wich inter rupt pin the Maestro-2 is using. This register is ed Ge ORabe a ane read-only and returns 01h when read, whic es tenon anra.er Oh wn ra, wh 1 emi aoc als tat Selects 10-0 10 Minimum Grant (Gen) 4 MO MPUMOLRCenabie Minune 1 = Enable MPU-40% IRO (tau, 7 ba 7 bd s bd ‘ ° 3 Mi MPU-401 /O enable. O'=Disable MPU-40' UO. BR Definitions: 1 = Enable MPU-401 UO (default. Bits Name Desoriotion 2 GM ‘Game port enable. 720 MG Min_Gnt.Kenties the burst period needed 0 = Disable game port “This reglster is read-only and returns G2h when 1 = Enable game port (defau read, whieh cortespondst 500s, 1m Eee O'= Disable FM syrthests. Maximum Latency (Fh, R) 1 2 Enable FM synthesis (defau. ‘Maxam ene © SB Sound Blaster enable. fe eee sable Sound Blaster channel Bit Definitions: Bits Name Description 7:0 ML Max Lat. Identifies how often bus access is needed. This register is read-only and returns ‘18h when read, which corresponds to 6 ms. able Sound Blaster channel (default) Legacy Audio Support The Maestro-2 supports the following legacy audio addresses, Table 3_Supported Legacy Audio Addresses Legacy Audio Control (40h, 41h, RW) [Legacy Audio Resources WO Address Base Lalsia] MibIRG | seiRG [OMAGH [wo] miew]rm] se ‘Sound Blaster Pro 22077240 wupenws 87654824 0 FM synthesis 88h on MPU-401 ‘200n/320n/9300/340R sti DMA Ghannelo,1,3 Bils Name — Description 15 LA Legacy audio disable. Ea 57,810 0 = Enable legacy audio. 1 = Disable legacy aucio (default) 14 SIR Serial IRQs enable. (0 = Disable serial IRQs (default. 1/= Enable serial IRQs. 19:11 MIDIIR_ MIDI VO IRQ select. Read-only. Default to 010. 10:8 SBIRQ Sound Blaster IRQ select B10 Bit9 Bit@ [RQ Selection 0 0 0 IROS of Oe ie mnor 0 1 0 Ras o 1 1 IRar0 1 x x Reserved ESS Technology, Ine, ‘SAMO056-102907 15MAESTRO-2 DATA SHEET Maestro-2 Configuration A (60h, 51h, RAW) Reserved [oM[ A | owAP [Pw] A [wan [se] A] S(O wuz e 87654327 0 Bit Definitions: Bils Name Description 18:13 - Reserved. 12 GM High-performance game port mode enable, no 10:8 DMAP ISA DMA poy 0 BLO BLE OMAPotcy a Distributed DMA 0 0 $ Transparent DMA 0 1 0 PCIPCIDMA 0 1 1 Reserved 1 x x Reserved 7 PW EN_PW. Posted write enable, Disable Maestro-2 posted wit. able Maestro-2 posted write 65 = Reserved 4:3 MAD MPU_401_DECODE, BL BRE MPU-A01 LO 0 33x of 20x 1 0 32x 14 34x 2 $2 $8240, Sound Blaster decode. (0 = Sound Blaster decade Is 22x. 11 = Sound Blaster decode is 24x. 1 = Reserved. 0 SID Write-enable bit for PCI subsystem ID (SID) and subsystem vendor ID (SVID). Read-only (default), Readrie, 1 Maestro-2 Configuration B (62h, 53h, RW) PGI CONFIGURATION REGISTERS Bits nS 11 PMG Name Deseription Reserved, Power management control for GLKRUN# enable. 0 = Disable PM control for CLKRUNE. 1 = Enable PM control for CLKRUN#. lock divider select for Sound Blaster, BiLLO BLo Gla Didar Divided by 48 Divided by 49 Divided by 50 Reserved 10:9 CLKSL ot 1 0 ea = Reserves. HWV Hardware volume control enable. sable hardware volume contol. able hardware volume contra, 1 Reduced debounce for hardware volume con- trol enable. 0 = Disable reduced debounce. 1 = Enable reduced debounce. Uptdown nara volume butlon input elect elect input from GPIO[5:4} {Select nat tm GDI? DSP interface enable. 0 = Disable the DSP interface/CH! bus. 1 = Enable the DSP interface/CHI bus. Reserved, 6 DHE 5 HV 30 ACPI Control A (64h, 55h, RW) [Rles[_n_[ecoe[paalpr[ nv fomo]ose salrufpahurofarlwr 6142s liga lomo omer emer eytE TET IEG ‘The ACPI Control A register sets the state (D1 or D2) of the stop clock for each module (24 MHz clocks, GLUE, DAA, PCI interface, hardware volume, modem/GPIO, DSP interface, Sound Blaster, FM, ring bus/AC-link, MIDI. game port, and Wave Processor). Bt Detinitons: fowfrsfoxs[m rua ouxst] A [Hwv[DreAW[DE] Reserved Bis Name Descioion 151413 12 11 109 8 7 6 5 43210 am 15 = Reserved Bi Definitions: 14 24 ACPI stop clock contol for the 24 MHz clock to the G2 outet ‘Bis Name Desarintion = Set stop clock to state D1. 15 [Cx Inlemal cock mulipir enable. 12 Seteep coctto sake D2 0 = Disable intemal ack multi. - 1 = Enable intemal clock multiplier. a Ky on . i eee 11 GLUE ACPI stop clock contol for GLUE. 0 = Select the clack from an external crystal Peace cock ioeee Dt gscilator. ol ‘Set stop clock to state D2. 1 Suiectae clock tom the interalctock «10. DAA_ACP! stop clock control for DAA power-down matpir. conto "Set sto clock o state D1 18 CxS Clock multiplier mode select, et stopcock sa lock muti mo Set stop clock state D2 1 Select mode 6 SANOOSE-100907 ESS Technology, reMAESTRO-2 DATA SHEET PCI CONFIGURATION REGISTERS: Bits Name 9 PIF Description AGP! stop clock control for the PCI interface. (0 = Set stop clock to state D1 ‘Set stop clock to state D2. ACPI stop clock control for hardware volume contro (0 =Set stop clock to state D1 ‘Set stop clock to state D2. ACPI stop clock contol for Modem/GP1O, ‘Set stop clock to state D1 1 = Set stop clock to state D2 [ACPI stop clock control for the DSP interface. (0 =Set stop clock to state D1 ‘Set stop clock to state D2. ‘ACPI stop clock control for Sound Blaster. ‘Sot stop clock to state D1 1 = Set stop clock to state D2. [ACPI stop clack control for FM, (0 = Sot stop clock to state D1 ‘Set stop clock to state D2. ‘ACPI stop clack control for Ring Bus/AC-ink ‘Set stop clock to state D1 1 = Set stop clock to state D2. ‘ACPI stop clock control for MIDI (0 = Set stop clock to state D1. ‘Set stop clock to state D2. ‘ACPI stop clock control for the game port. ‘Set stop clock to state D1 1 = Sot stop clock to state D2. [ACPI stop clock control forthe Wave Processor. (0 = Set stop clock to state D1 ‘Sot stop clock to state D2. 7 @PIO 6 psP 2 MIDI ‘ACPI Control B (56h, 57h, RW) les]_A_[GLveloaApPr[ av [oPto[osP]selrw|aajworjce| wr] 142 1 7 6543210 Toop oearaere ‘The ACPI Control B register enables the clock at the state (01 or 02) set for each module in the ACPI Control A register. Bit Detinttions: Bis Name Do 14 24 Description Reserved ACPI stop clock enable for the 24 MHz clock to the ©24 output. 0 « Stop clock at state D1/D2 disabled, Enable stop clock at state D1/D2. Reserved ‘ACPI stop clock enable for GLUE ‘Stop clock at state D1/D2 cisabled Enable stop clock at state D1/D2, itz 11 GLUE ses) Bits Name 10 DAA Description AGP! stop clock enable for DAA power-down control (0 = Stop clock at state D1/D2 disabled, 1 = Enable stop clock at state D1/D2. ACPI stop clock enable for the PCI interface, 0 = Stop clock at state D1/02 disabled, 1 = Enable stop clock at state D1/D2. ACPI stop clock enable for hardware volume contro (0 = Stop clock at state D1/D2 disabled, 1 = Enable stop clock at state D1/D2. ACPI stop clock enable for Modem/GPIO. (0 = Stop clock at state D1/D2 disabled, 1 = Enable stop clock at state D1/D2. AGP! stop clock enable for the DSP interface. (0= Stop clock at state D1/D2 disabled, 1 = Enable stop clock at state D1/D2. ACPI stop clock enable for Sound Blaster. 0 = Stop clock at state D1/02 disabled, 1 = Enable stop clock at state D1/D2. ACPI stop clock enable for FM. 0 = Stop clock at state D1/02 disabled, 1 = Enable stop clock at state D1/D2. ACPI stop clock enable for Ring Bus/AC-Aink 0 = Stop clock at state D1/02 disabled. 1 = Enable stop clock at state D1/D2. ACPI stop clock enable for MIDI (0 = Stop clock at state D1/D2 disabled, 1 = Enable stop clock at state D1/D2. [ACPI stop clock enable for the game port (0 = Stop clock at state D1/D2 disabled, 1 = Enable stop clock at state D1/D2. AGP! stop clock enable for the Wave Processor. (0 = Stop clock at state D1/D2 disabled, 1 = Enable stop clock at state D1/D2. 9 PIF 7 GPO 6 sp 2 MIDI Distributed DMA Control (60h, 61h, RW) MALTS 4] o[oe [oe ww awnose7 654321 0 Bit Definitions: Bls Name Description 15:4 DMA[15:4] Distributed DMA base adcress, a1 = Always write 0. 0 DE Distributed DMA enable. 0 = Disable distributed DMA, Enable distributed DMA ESS Technology, Ine, ‘SANO056-102997 7