Digital Electronics and Logic Design MCQs [set-22]

526. Consider an up/down counter that counts between 0 and 15, if

external input(X) is “0” the counter counts
upward (0000 to 1111) and if external input (X) is “1” the counter counts
downward (1111 to 0000), now
suppose that the present state is “1100” and X=1, the next state of the
counter will be

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A. 0
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B. 1101
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C. 1011

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D. 1111
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Answer: B
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527. In a state diagram, the transition from a current state to the next state
is determined by

A. current state and the inputs

B. current state and outputs

C. previous state and inputs

D. previous state and outputs

Answer: A

528. is used to simplify the circuit that determines the next state.

A. state diagram

B. next state table

C. state reduction

D. state assignmen t

Answer: D

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529. Assume that a 4-bit serial in/serial out shift register is initially clear.
We wish to store the nibble 1100. What will be the 4-bit pattern after the
second clock pulse? (Right-most bit first.)

A. 1100

B. 11

C. 0

D. 1111

Answer: C
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530. The diagram given below represents
a
A. demorgans law
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B. associative law c
C. product of sum formM
D. sum of product form

Answer: D

531. The operation of J-K flip-flop is similar to that of the SR flip-flop

except that the J-K flip-flop

A. doesn’t have an invalid state

B. sets to clear when both j = 0 and k = 0

C. it does not show transition on change in pulse

D. it does not accept asynchron ous inputs

Answer: A

532. A multiplexer with a register circuit converts

A. serial data to parallel

B. parallel data to serial

C. serial data to serial

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 D. parallel data to parallel

Answer: B

533. A GAL is essentially a .

A. non- reprogrammab le pal

B. pal that is programmed only by the manufacture r

C. very large pal

D. reprogra mmable pal

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Answer: D
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a are either read or written.
534. in , all the columns in the same row

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A. sequential access
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B. mos access M
C. fast mode page access

D. none of given options

Answer: C

535. How many flip-flops are required to produce a divide-by-32 device?

A. 2

B. 5

C. 6

D. 4

Answer: B

536. A reduced state table has 18 rows. The minimum number of flip flops
needed to implement the sequential machine is

A. 18

B. 9

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 C. 5

D. 4

Answer: C

537. Advantage of synchronous sequential circuits over asynchronous

ones is

A. faster operation

B. ease of avoiding problems due to hazard

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C. lower hardware requirement
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D. better noise immunity
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Answer: A

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c of a JK flip flop is
538. The characteristic equation

A. qn+1=j.qn+k.q n
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B. qn+1=j.q’n+ k’.qn

C. qn+1=qnj.k

D. qn+1=(j+k )qn

Answer: B

539. WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP

ARE SET TO LOGIC ZERO -------

A. the flop- flop is triggered

B. q=0 and q?=1

C. q=1 and q?=0

D. the output of flip- flop remains unchang ed

Answer: D

540. In Q output of the last flip-flop of the shift register is connected to the
data input of the first

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flip-flop of the shift register.

A. moore machine

B. meally machine

C. johnson counter

D. ring counter

Answer: D

541. 5-BIT JOHNSON COUNTER SEQUENCES THROUGH STATES

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A. 7
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B. 10
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C. 32
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D. 25
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Answer: B M
542. A 8-bit serial in / parallel out shift register contains the value “8”,
clock signal(s) will be required to shift the value completely out of
the register.

A. 1

B. 2

C. 4

D. 8

Answer: D

543. AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1”. WHAT
WILL BE THE VALUE OF REGISTER AFTER THREE CLOCK PULSES?

A. 2

B. 4

C. 6

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 D. 8

Answer: D

544. The alternate solution for a multiplexer and a register circuit is

A. parallel in / serial out shift register

B. serial in / parallel out shift register

C. parallel in / parallel out shift register

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D. serial in / serial out shift register
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Answer: A
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545. A multiplexer with a register circuit converts
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A. serial data to parallel

B. parallel data to serial

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C. serial data to serial

D. parallel data to parallel

Answer: B

546. A synchronous decade counter will have flip-flops

A. 3

B. 4

C. 7

D. 10

Answer: B

547. In outputs depend only on the current state.

A. mealy machine

B. moore machine

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 C. state reduction table

D. state assignmen t table

Answer: B

548. Given the state diagram of an up/down counter, we can find

A. the next state of a given present state

B. the previous state of a given present state

C. both the next and previous states of a given state

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D. the state diagram shows only the inputs/out puts of a given states

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Answer: A
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549. THE HOURS COUNTER IS IMPLEMENTED USING
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A. only a single mod- 12 counter is required

B. mod-10 and mod-6 counters

C. mod-10 and mod-2 counters

D. a single decade counter and a flip-flop

Answer: D

550. The design and implementation of synchronous counters start from

A. truth table

B. k-map

C. state table

D. state diagram

Answer: D

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