BE-III/New/ESC-CSE302/R/2021-22/UIT/BU

B.E Odd (3rd) Semester Examinations 2021-22

Subject: Digital Logic Code: ESC-CSE 302

Time: 3 Hours Full Marks: 70

Instructions: Answer any four questions from Group A (Q. No. 1 to 6)

and any five questions from Group B (Q. No. 7 to 13).

Send this answer script to the mail id uit.esccse302.newcse.reg@gmail.com (for CSE)

Send this answer script to the mail id uit.esccse302.newit.reg@gmail.com (for IT)

Group A
4X5=20
(Answer any four questions from Q. No. 1 to 6)
Q.NO. QUESTIONS MARKS

1. Convert the following binary numbers N1, N2 & N3 into their equivalent decimal 5
numbers P, Q & R respectively and calculate (P-Q+R) using the 10’s complement
method:

N1 = 11001110

N2 = 11111001

N3 = 10000111

2. ̅̅̅̅ +A𝐶𝐷
Represent AC+𝐵𝐷 ̅̅̅̅ +ABD as its corresponding canonical SOP and POS forms.
5

3. Draw the logic diagram of a 5-bit Magnitude Comparator. 5

4. Implement the following expression using 8:1 Multiplexer:

5
F(W,X,Y,Z) = m(0,1,3,4,7,8,9,13,15)

5. Design a JK Flip-flop using a D Flip-flop, a 2:1 MUX and an inverter. Supplement 5

the design with appropriate conversion tables.

6. Design and implement a mod-5 ripple counter using D Flip-Flops. 5

Semester: III Year: 2021-22 Subject Code: ESC-CSE 302

 Group B
5X10=50
(Answer any five questions from Q. No. 7 to 13)
Q.NO. QUESTIONS MARKS

7. (a) Perform the following conversions: (1756)8 = (?)10 = (?)2 = (?)16 = (?)Gray = (?)BCD 5+5=10

(b) Why do we call Excess-3 (XS-3) code as a self-complementing code? Subtract

108 from 297 in XS-3 code.

8. (a) Without reducing, implement the following expression in AOI Logic and then 5+5=10
̅̅̅̅+ ̅̅̅̅̅̅̅̅̅̅
convert it into NAND Logic: P+PR (P + Q) +P ̅. Q
̅

(b) Minimize the following Boolean expression specifying the laws and rules of
Boolean Algebra and find the dual of the resultant expression:

̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
Y Z̅ + YX
̅̅̅̅ + Z̅ X
̅ + XYZ + XZ

9. Reduce the following expression using Karnaugh Map. Also draw the logic diagram 10
of the obtained expression using any universal gate(s).

Π M(3,6,8,11,13,14).d(1,5,7,10)

10. Describe the operation of a bidirectional universal shift register (with parallel load) 10
using a neat schematic.

11. (a) “Clock skew” and “time race” are considered as potential problems or challenges 5+5=10
while designing digital circuits. Explain these two terms and discuss their mitigation
strategies.

(b) Draw and explain the working of a pulse triggered master-slave S-R Flip-Flop
using logic diagram, truth table and timing diagram.

12. (a) Compare and contrast Synchronous Counter and Asynchronous Counter. 5+5=10
(b) Using suitable illustrations explain the working of a 4-bit Johnson Counter;
constructed using SR Flip-flops.

13. (a) Using the connection abbreviations, implement the following function using
5+5=10
3x4x2 Programmable Logic Arrays: F(X,Y,Z) = ∑(1,3,5,7)
(b) Show how an FPLA circuit can be programmed to implement the sum and carry
outputs of a Full Subtractor.

Semester: III Year: 2021-22 Subject Code: ESC-CSE 302