Received March 13, 2016, accepted April 13, 2016, date of publication April 22, 2016, date of current

version July 7, 2016.

Digital Object Identifier 10.1109/ACCESS.2016.2557843

Dual-Band Waveform Generator With Ultra-Wide

Low-Frequency Tuning-Range
IBTISAM A. ABBAS AL-DARKAZLY AND S. M. REZAUL HASAN, (Senior Member, IEEE)
Center for Research in Analog and VLSI Microsystem Design, School of Engineering and Advanced Technology, Massey University, Albany 0632, New Zealand
Corresponding author: S. M. R. Hasan (hasanmic@massey.ac.nz)

ABSTRACT This paper presents a novel mixed-signal low-power dual-band square/triangular waveform
generator (WFG) chip with a wide low-frequency tuning range for medical bio-electric stimulation therapy.
It consists of a relaxation oscillator comprising a hysteresis Schmitt trigger and a timing integrator, along with
frequency divider (FD) stages and path selector output for driving an electrode from 16 selectable channels.
It was fabricated using Global Foundries 8RF-DM 130-nm CMOS process with a supply voltage of ±1 V
for the oscillator and +1 V for logic circuits. The WFG provides an output of around 1.5 Vp–p at a nominal
low oscillation frequency of 17 kHz using small-size on-chip passive components of values 10 k and 10 pF.
The WFG core (band I) can be tuned in the range 6.44–1003 kHz through bias current adjustment, while a
lower frequency (band II) in the range 0.1 Hz–502 kHz can be provided digitally through a ÷2 stage. The
power consumption was only 0.457 mW for the WFG and 2.1 mW for the FD circuit while occupying a total
silicon area of only 18 426 µm2 .

INDEX TERMS Waveform generator, low-frequency, low-power, hysteresis Schmitt trigger, frequency
divider, multiplexer, path selector.

I. INTRODUCTION controlling parameters [8]. It is possible to consider an

There is a growing demand for technological improvement
of healthcare electronics. Today’s nanometric CMOS
technology enables energy-efficient and low-cost WFG
circuit solutions for biomedical devices. These devices are
important in various implantable, non-invasive, sensing,
wireless signal processing and stimulation procedures for
treating a variety of diseases and disorders [1]. WFG is
required in implantable cardiac pacemaker system [2] that
provides electrical stimulation to enhance the heart beat.
It is also used for micro-power analog stimulation hearing aid
systems for the hearing impaired [3]. WFG as a stand-alone
signal source along-with wide frequency ranges (a high
frequency mode and a low frequency mode) is required for
neurological disorder systems for Patients with Parkinson’s
disease, visual impairment, Deep Brain Stimulation [4]–[6]
as well as for muscles injury [7]. This stimulator circuit can
be designed as either monophasic or biphasic depending on
the application. Biphasic waveform is necessary in order
to ensure that no residual charge is left in the tissue [1].
Generally, WFG generates a prescribed waveform whose
amplitude and frequency can be adjusted using appropriate
bias or component values. There are many parameters
to consider in any WFG design including periodicity,
wave-shape, speed, frequency-determining components and
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enormously wide range of WFGs, all of which are constructed
using a simple core oscillator based on positive feedback
theory [9]. Relaxation oscillators are an important class
of oscillators, mainly used in low power signal processing
systems. WFGs using current mode (CM) technique that
provide an attractive low power design, large dynamic
range with high linearity, implementation simplicity, and
compact structure are dominant over approaches based
on voltage-mode designs [10]–[12]. Consequently, a wide
variety of CM WFG circuits based on hysteresis Schmitt
trigger, has employed building blocks ranging from the
current conveyors (CCII) [13]–[19] through to operational
trans-conductance amplifiers (OTAs). WFG based on CCII
provides good frequency stability controlled by the ratio of
passive devices. Most of these reported CCII realizations
have been implemented employing commercially available
components. For fully on-chip implementation, the passive
component values deviate due to Process, Voltage and
Temperature (PVT) variations which result in loss of
accuracy [9], [20]. Furthermore, tuning passive devices to
obtain accurate frequency response characteristics is difficult
and requires complex tuning circuity [21]. CCII solution is
further complicated due to the fact that extra active CCIIs
and matched passive components are required. In addition,
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 I. A. A. Al-Darkazly, S. M. R. Hasan: Dual-Band WFG With Ultra-Wide Low-Frequency Tuning-Range
one or more floating resistors and capacitors are essential
which is not desirable in IC implementation [18]. Hence,
WFG based on CCII have many constraints which
complicates the design and is not appropriate for low
power applications. However, WFG based on OTA employs
a simple and robust topology that have good frequency
stability and its frequency and amplitude can be controlled
by bias currents [22]–[28]. Of particular interest in this
paper is current-controllable WFG utilizing OTA that
can be realized by a hysteresis Schmitt trigger and an
integrator-based timing circuit. Using an active gm -C
integrator as relaxation timing network, has the advantage
that its transconductance (gm ) can be controlled directly
by the biasing current. Also, it can be implemented using
small gm values in providing low frequency oscillation
and optimized parameters such as DC-gain, output-swing
and linearity [29]. This type of WFG circuit is preferred
for tunable, low-power, low-cost, miniaturized single-chip
design with high functionality [1], [30]. Low frequency
oscillator circuit based on OTAs can be designed to
achieve a wide tuning range with practical area and power
constraints. Low frequency oscillators (several kHz to < Hz)
have distinctive design challenges [31] while having many
interesting applications in biomedical and geophysical
systems [32], [33]. Although many reported designs achieve
low power consumption with narrow frequency tuning range,
many complex applications require wide frequency tuning
range along with compensation for PVT fluctuations. This
work develops a tunable WFG along with FD by cascading
multiple divide-by-two (f ÷2) circuits as shown in Fig. 1,
in order to realize dual-mode wideband oscillations that
satisfies the minimal requirements for electrical stimulation
and biomedical devices. The organization of this paper is
as follows. In section II, the circuit design and topology
are presented, and, WFG circuit operation is discussed
FIGURE 1. Block diagram of the proposed mixed-signal CMOS waveform
generator. Oscillation frequency of WFG core circuit is fWFG (band I) and
the digitally channelized selectable output frequency is f o (band II).
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in section III. Simulation results are provided in section IV,
while, design robustness of the WFG circuit, and, fabrication
with experimental results are provided in sections V and VI
respectively. Finally, conclusions are drawn in section VII.
II. CIRCUIT DESIGN AND TOPOLOGY
The core oscillator can generate a bi-phase square waveform
signal. The overall implementation includes a tunable
WFG, clock (clk) and clk_bar translations, along with
16 stage divide-by-2 frequency divider (FD) in series with
dual 8-1 multiplexers (MUXs) and a path-selector (PS). The
PS output can drive electrodes for electro-medical stimulation
using the chosen frequency.
FIGURE 2. The core square/triangular waveform and clock generator
circuit.
A. WFG
Schematic of the proposed WFG with clk and clk_bar
circuit is shown in Fig. 2. Its operation is characterized
by a positive feedback hysteresis Schmitt trigger along
with a timing network in a negative feed-back loop
formed by an integrator. This configuration exhibits good
linearity and relatively low temperature sensitivity using
only four amplification stages along with one resistor and
one capacitor. The circuit generates square and triangular
waveforms at the VWFG and VINT terminals respectively, with
a target frequency of around 17 kHz and peak-to-peak output
voltage of around 1.5V. It’s amplitude and frequency can
be linearly controlled by bias current through simple tuning
gate-voltage (V_tune). The three stage hysteretic Schmitt
trigger is a device-size modified version of that in [28].
The first stage (STG1) employs an NMOS differential
input pair (M1, M2) along with a PMOS active current
mirror load (M3, M4). It is followed by two simple PMOS
common source M5 and M6 (inverter amplifier) gain stages
(STG2) and (STG3) respectively. STG1, STG2, STG3 along
with resistor R are configured as voltage amplifier which
are connected in positive feedback to form a hysteresis
Schmitt trigger that determines the amplitude of the generated
square waveform signal (the saturation output). Tunable gm -C
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integrators have found wide applications in many analog

building blocks. For low power applications, gm -C integrators
can be designed for a wide frequency and tuning range
[1], [20]. In this waveform generator a first order gm -C
integrator building block (STG4) has been employed as
part of the timing circuit. The integrator forms a relaxation
timing network in a negative feed-back loop with the
inverting terminal of STG1 and controls the waveform
frequency. The NMOS M15 realizes a voltage-controlled bias
current (IB4 ) to control the oscillation frequency through
wide-range gm variation. The single ended gm -C topology
offers the desired characteristics of high input impedance,
wide bandwidth, high slew-rate and low power consumption.
The most important aspect of the gm -C integrator is the
transconductance design. The transfer function of the gm -C
integrator (in Fig. 2) can be deduced using a two-path analysis
to be given by,

gm7,8 (ro8 //ro10 ) (2 + s gCmE )

9
H(s) = (1)
(1 + s gCmE ) [1 + sCL (r08 //r010 )]
9
FIGURE 3. The TGMSDFF for divide-by-2 frequency division circuit,
Where, CE is the total capacitance at the drain node of (a) block diagram, (b) circuit implementation.
M7, ro8 and ro10 are respectively the output impedances of
M8 and M10 respectively. Also, gm9 is the transconductance
of M9. The transfer function has two poles and a zero. divide-by-2 Flip-Flops. Transmission-gates (TGs) are used
The dominant pole is at 1/CL (r08 //r010 ) compared to the to realize master–slave D-Flip-Flops (TGMSDFF). Energy
gm consumption and area is optimized by appropriate device
non-dominant mirror pole at CE9 . Hence at low frequencies
sizing. The ÷2 Toggle-Flip-Flop (T-FF) was implemented by
the transfer function is given by,
connecting the Q’ output of a MSDFF to its D input, while
2gm7,8 Q output is used as the data output. Fig. 3 (a) and (b)
H (s) = (2)
sCL respectively shows the schematic diagram and the implemen-
Putting s = jω (translating to Fourier domain), the unity tation of the designed TGMSDFF for divide-by-2 frequency
2gm7,8 division circuit. Two 8-to-1 Multiplexers (MUX1 and MUX2)
gain frequency, ωugf = CL with the corresponding
along with a Path Selector (PS) are used to select FD outputs
time-constant,
as shown in Fig. 4.
CL
τ= (3)
2gm7,8 III. WFG CIRCUIT OPERATION
Equation (3) shows that the time-constant of the integrator Fig. 5 shows the transfer characteristic of the hysteretic
goes up as gm7,8 decreases and CL increases. By substituting Schmitt trigger with respect to the integrator relaxation
gm7,8 into (3) a proportionality can be established between IB4 timing and the waveforms. The circuit toggles between
and the integrator time-constant which is given by, two quasi-stable states Vsat+ and Vsat− in a free-running
s oscillation mode through regenerative feedback. The
CL L7,8 charging and discharging of the gm -C integrator’s capacitor
τ= √ (4)
2 µn Cox W7,8 IB4 produces the trigger voltage VINT to toggle the circuit
between these two states. The component values as
Where, µn is the electron mobility, Cox is the oxide
per (3) sets the state transition periods. The ramp output
capacitance per unit area, and, W7,8 and L7,8 are respectively
voltage VINT is an integration (temporal-accumulation) of the
the width and length of the devices (M7, M8). A wide
voltage VWFG . The Schmitt trigger switches to its saturated
frequency-range can thus be achieved by tuning the gm7,8
high positive level Vsat+ when VINT dips below its saturated
of the integrator using IB4 . It also provides an avenue to
low negative level VINTL and remains in that state until VINT
compensate any PVT variations.
exceeds its saturated high positive level VINTH , at which
point it switches to the saturated low negative level Vsat− .
B. FREQUENCY DIVIDER AND DIGITAL BLOCK
It remains in that state until VINT once again sinks
Two series connected inverters are employed as shown in
below VINTL , so that,
Fig. 2 to generate the complementary rail-to-rail clock (clk)  
and clock_bar (clk_bar) signals required to feed the FD. Vsat+ if VINT ≤ VINTL
VWFG (VINT ) = (5)
The FD circuit is implemented by cascading 16 stages of Vsat− if VINT > VINTH

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FIGURE 4. Multiplexers and path selector along-with output driving
circuit.
FIGURE 5. Transfer characteristic of the core Schmitt trigger (LHS), in
relation to the square and triangular wave-shapes of the waveform
generator (RHS).
The Schmitt trigger output VWFG is a square waveform
signal, while the integrator output VINT is a triangular
waveform. The characteristic of the first order nonlinear
oscillator system based on the gm -C integrator can be
given by,
dVINT
CL + VWFG (VINT )gm7,8 = 0 (6)
dt
The circuit operation is based on the differential pair
switching voltages. The OTA operates as a linear amplifier
with positive feedback in switching from one quasi-stable
state to another. The operation of the circuit can be
described by considering the two linear regions of the
triangular waveform which consists of two integration
intervals T1 and T2. Initially the output VWFG at t0 = 0
is assumed to be Vsat+ at the integrator input, and is integrated
for the period T1. The integrator’s output VINT starting
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from its low negative level increases linearly with a constant
positive slope IB4 /CL towards its high positive level. The
non-inverting terminal at the gate of M1 (Vin1+ ) is also
held at Vsat+ for this duration. The capacitor CL is initially
discharged and the gate potential Vin2− of M2 in STG1 of
the Schmitt trigger is at its minimum low level VINTL . It is
assumed that the input to M2 is a positive rising triangular
(ramp) waveform from low to high VINT L-to-H , while the gate
potential Vin1+ of M1 remain at its maximum positive level.
With the difference between Vin1+ and Vin2− sufficiently
large, M1 conducts most of the bias current IB1 , so that
M2 is off, driving M4 into deep triode region with zero
current, and the output voltage of the OTA in STAG1 is
then equal to VDD. With M4 in deep triode, the gate of
PMOS M5 is then at high potential and almost turned-off
resulting in the bias current IB2 becoming a constant charging
current contributing electrons to the gate of M6 and bringing
its potential down near the negative supply voltage. M6 is
thus acting as a switch operating in the deep triode region,
resulting in the maximum output voltage (Vsat+ ) being near
the positive supply voltage VDD. The drain current iM6_L-to-H
of the switch M6 is then the sum of the bias current IB3 ,
gate pull-up current of M7 (supplying holes to the gate
of M7) and the current through the resistor R. The Vsat+ also
causes M7 to absorb large part of the bias current IB4 . The
output current of the integrator (mirrored by M9 and M10),
IOINT ≈ IB4 , charges CL to raise VINT from VINTL to
VINTH . This causes the output of the integrator to linearly
increase with a slope of +IB4 /CL , providing a positive linear
ramp voltage VINT L-to-H at the inverting input terminal Vin2−
of M2. The current charging CL is constant and independent
of the input level, thus the output level VWFG remain
constant. But as VINT rises, the difference between Vin1+
and Vin2− in STG1 reduces, M2 turns on drawing part
of IB1 . Eventually VINT is saturated at its high positive level,
VINTH causing the square waveform voltage VWFG to switch
state (through positive feed-back) and saturate at its low
negative level Vsat− . At t = t1 , the negative half-cycle of the
output (period T2) begins with VWFG at Vsat− and VINT at
VINTH . Also, CL is fully charged and the gate potential Vin2−
of M2 has its maximum positive level with M2 conducting
most of the bias current IB1 . Therefore, most of IB1 becomes
a charging current bringing the gate of M5 lower towards
the negative supply voltage by supplying electrons to the
gate. As a consequence, M5 is behaving almost as a closed
switch resulting in the gate of M6 being near the positive
supply. Now, with M6 almost off, the continuity of the bias
current IB3 requires that large (significant) part of it will
now flow through the resistor R. Consequently, the minimum
output voltage Vsat− achieved by the circuit can be then given
approximately by −IB3 × R. With the output of the Schmitt
trigger saturated at low negative level, Vsat− , the integrator
discharges CL by a current −IB4 , lowering VINT from VINTH
towards VINTL . This causes the output of the integrator
to linearly decrease with a slope of −IB4 /CL , providing
a negative linear ramp voltage VINTH−to−L at Vin2− .
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As VINT voltage decreases, the gate potential Vin2− up by the square root of W × L, and also by reducing
eventually approaches the gate potential Vin1+ , M1 then the drain current ID . Using small DC drain bias current
turns on drawing part of IB1 . The VWFG remains negative also significantly improves power consumption. Hence bias
until VINT reaches its low negative value VINTL . Eventually, current sources M12, M13 and M14 are designed to have high
the output switches and VWFG become Vsat+ again. Based output impedance, and in relation to this design, the values
on the above description, design equations can be developed for L12, L13 and L14 should be made 2 times longer than the
for the period (T) and the frequency (f ) of the generated minimum length. The maximum output swing for the circuit
waveform. The voltage at the integrator output VINT at any being near the positive supply voltage (Vsat+ = VDD) is
time (t) is the initial capacitor voltage plus the incremental limited by M6 going into triode region, which is ON as a
voltage due to the accumulation of charge for the transition switch with very small drain-to-source drop. M6 thus requires
period. The time expression for the output voltage VINT (t) in a very small RDS(ON) using a reasonably wide PMOS device.
the charging and discharging periods can then be given by, The minimum output value (Vsat− = −IB3 × R) is limited
( ) by the gate voltage of M14 and the regenerative positive
VINT (t0 ) + ICB4L (t1 − t0 ) feedback resistor R. In order to bring the minimum output
VINT (t) = (7)
VINT (t1 ) − ICB4L (t2 − t1 ) voltage closer to the negative supply voltage, the drain voltage
Then the overall period (T) is easily derived to be, VD14 of M14 may not go below the gate voltage of M14 by
more than VTHN , hence,
2CL (VINTH + VINTL )
T= (8) VD14 = VSS + VGS14 − VTHN (13)
IB4
Where the VINT limit values of −VINTL and +VINTH can Substituting for (VGS14 - VTHN ), gives,
be given with standard notations (using (8) and (24) in s
2IB3
reference [28]) as follows: VD14 = VSS + (14)
µn Cox W 14
L14
−VINTL = − |VSS| + VDS12 + VGS2L-to-H
s s Hence, to improve the swing, the value of VGS14 must be
2IB1 0.2IB1
= − |VSS| + + +VTHN made small, resulting in large value of W14/L14. Using an
W12
µn Cox L12 µn Cox W
L2
2
appropriate resistor R can also enhance the output swing.
(9) However, the size of M1 and M2 are more important in
the design which dominate the overall circuit performance.
And, For proper operation of the three stage operational amplifier
VINTH of the Schmitt trigger, the gate potential at the inputs
Vin1+ and Vin2− of STG1 should be within a limited
= − |VSS| + VGS2H-to-L (0+) + VOD12
range. If the input voltage goes beyond this range, the
0.9IB1
= −|VSS| + operational amplifier gain drops and the WFG circuit
W2 
µn Cox L2 · VD2H-to-L (0+) + |VSS| −VOD12

cannot function properly. The maximum input VG 1,2 (MAX)
+ VTHN + VOD12 (10) is limited by M1 and M2 going into triode region, and hence,
VG 1,2 (MAX) = VDD−|VGS3 | +VTHN . Substituting for VGS3
The overall frequency of the waveform is given by,
the maximum input for M1 and M2 can thus be given by,
IB4 "s #
fWFG = (11) IB1
2CL (VINTH + VINTL ) VG1,2(MAX) = VDD− + VTHP + VTHN (15)
µn Cox W 3
The oscillation frequency is proportional to the integrator bias L3
current and inversely proportional to the timing capacitor as Where |VGS3 | is written in terms of its drain current
well as the integrator output swing. ID3 ≈ IB1 . The minimum input voltage VG1,2(MIN) is
limited by M12 driven near the edge of saturation, hence,
COMPONENTS SIZING FOR LOW VG1,2 (MIN) = VSS +|VDS12 | +VGS1,2 . Since the overdrive
FREQUENCY WFG DESIGN VOD12 ≈ VDS12 ,
For an appropriate design that reduces power consumption s
2IB1
and optimizes silicon area, it is important to analyze the VDS12 ≈ VOD12 = − VTHN (16)
controllable parameters. The loop gain of the core oscillator µn Cox W 12
L12
can be given by [28], So,
A+ = gm1,2 · (ro2 //ro4 ) · gm5 · ro5 · gm6 · (ro6 //R) (12) s v
v 2IB1
u
IB1
VG1,2(MIN) = VSS +
u
+t (17)
Where gm1,2 , gm5 and gm6 are the trans-conductances of µn Cox W12
L12
W
µn Cox L1,2
1,2

(M1, M2), M5 and M6 respectively. Also, ro2 , ro4 , ro5 and

ro6 are respectively the output impedances of M2, M4, M5 Equations (15) and (17) shows the variables for improving
and M6. Equation (12) shows that the open-loop gain goes VG1,2 (MAX) and VG 1,2 (MIN) of the pair (M1, M2) of STAG1.

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 I. A. A. Al-Darkazly, S. M. R. Hasan: Dual-Band WFG With Ultra-Wide Low-Frequency Tuning-Range
To make VG1,2 (MAX) as large as possible, IB1 and L3 should
be made as small as possible while W3 is made as large as
possible. On the other hand, to make VG1,2 (MIN) as small
as possible, L12 , IB1 , and L1,2 should be made as small as
possible while increasing W12 and the pair W1,2 to as wide
as possible. The oscillation frequency can be varied linearly
over a wide range through a choice of W7,8 as per (4). The
design value of CL can be approximately determined from the
bandwidth specification in (4) through iterative incremental
selection of W7,8 and IB4 values and solving for CL .
IV. SIMULATION RESULTS AND DISCUSSIONS
The proposed waveform generator in Fig. 2 with amplitude
and frequency tuning was simulated in 130 nm CMOS
process technology on Mentor Graphics Pyxis version 10 [35].
The component values and device sizes of the different
stages are chosen based on specific low frequency operation
and power consumption constraints. To enable better
headroom (and device matching) 2.5V NMOS (Dgnfet)
and PMOS (Dgpfet) with minimum channel length of
0.24 µm with dual-supply-voltage of ±1V was utilized
for the core oscillator. The basic 130 nm node-size was
used for the digital blocks (logic gates and flip-flops)
using single-supply-voltage of only +1V. In order to
achieve micro-power consumption, low bias currents and
constrained device widths was employed. Following the
analysis presented earlier, optimum design values were
considered for the active and passive components of the
Schmitt trigger in STG1, STG2 and STG3, and for the gm -C
integrator in STG4. The key factors that control the gain
of the Schmitt trigger circuit are the bias currents and the
W/L ratios of the input differential pair (M1, M2) and the
common-source gain stages M5 and M6. The (M1, M2) input
pair in STG1 which dominate overall circuit performance
are matched for equal transconductances. Using an iterative
technique optimal dimensions for the MOSFET devices and
minimized bias currents was achieved. A larger channel width
for mirror devices, W3 = W4 = 12 µm is chosen to
minimize VGS3,4 , resulting in higher output swing and a bias
current of around 66 µA for STG1. The output resistance
of the current source loads M13 and M14 is designed to
be much larger than M5 and M6 output resistances. The
bias currents of around 26 µA and 33 µA was drained for
the STG2 and STG3 respectively. However, M14, which
provides bias current IB3 is also utilized for the realization
of an amplitude control technique. Suitable design values
for the active and passive elements of the gm -C integrator
in STG4 are also investigated thoroughly with the size of the
input pair (M7, M8) being the most critical. Relatively longer
channel length provides this OTA high output resistance and
high voltage gain, while the width of (M7, M8) is selected
to enable enough current drive for the chosen CL . The
purpose of the small mismatch between the PMOS mirror
devices of the gm -cell is to control the duty cycle of the
integrator. The duty cycle of the WFG can then be controlled
by adjusting the width of PMOS load M9, the wider the
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device the larger the duty cycle. The size of M15 was chosen
not only to provide the bias current IB4 for the integrator,
but also for ultra-low-power realization of an appropriate
tuning technique to adjust the bias current IB4 , thereby
tuning the cut-off frequency (time-constant) of the integrator.
After iterative simulations, bias current Iref = 132 µA for
Rref = 15k was achieved to optimize the constant power
consumption for the OTA stages. The WFG provides a
peak-to-peak output voltage of around 1.5 V for R = 10 k.
The circuit can source a considerable amount of current at
the output stage, being around 164µA (peak-to-peak output
current) which can be useful in current source applications.
A load capacitor (CL ) of only 10pF is utilized to reduce the
chip area and create an oscillation frequency in the kHz range.
The circuit generated a typical square waveform as shown in
Fig. 6, with an oscillating frequency, fWFG = 17 kHz and
duty cycle of 50%. Fig. 7 represents the spectrum-analysis
indicating its odd harmonics with reducing amplitudes
(f1 = 51 kHz, f2 = 85 kHz, f3 = 119 kHz, and
f4 = 153 kHz). A triangular waveform (VINT ) is generated
across CL , as shown in Fig. 8 with variable tuning range. The
proposed WFG thus performs satisfactorily with integrated
passive component values ≤10k, and capacitance ≤10pF
and is tunable using the gm -C integrator. The clock and
clock_bar signals are generated from the single-ended +1V
supply using the cascade of a level-shifting inverter and a
regular inverter. The level shifting inverter has a 2.5V PMOS
device as the voltage across it can be as high as 2V for low
logic input from the VWFG of the Schmitt trigger. These
signals are shown in Fig. 9.
FIGURE 6. Simulated transient square waveform output of the WFG.
The FD circuit also utilizes a +1V supply and its critical
delay path was scaled for satisfactory performance. The
main avenue of power dissipation in the implemented digital
2 ).
circuits is the dynamic power drain (Pdynamic = fclk CL VDD
Scaling supply voltage and lowering CL can substantially
reduce power dissipation. Generally, power consumption as
well as silicon area of the FD circuit depends on appropriate
FlipFlop topology and the device W/L ratios. All of the
TGMSDFFs utilized were identical copies. To optimize
the FD, the circuit was investigated for various widths of the
N-MOS and P-MOS devices for both the Inverter (INV) and
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FIGURE 7. Spectrums analysis of the square waveform signal

(fWFG = 17 kHz).

FIGURE 10. The 16 channel output square waveforms digitally selectable

through MUX1, MUX2 and PS.

FIGURE 8. Simulated transient triangular waveform at the integrator

output.
TABLE 1. The power and area versus generalized transistor width for the
designed FD circuit.

FIGURE 9. Simulated transient response of the clock and clock_bar

generator.

L = 39.36µm2 , whileP the total active

TG elements using the same channel length. Accordingly, an
iterative process was employed to optimize all the FlipFlop
stages for low power P budget. The P active area for each
D-FF(D-Latch)
P was W INV L + WTG L = 4.32 µm2 ,
where, WINV P is the sum of the widths of all the inverter
devices and WTG is the sum of the widths of all the TG
devices. The overall active area of the 16 TGMSDFFs is then
equal to 138.24 µm2 . The inverter sizing for MUX, PS and
the output stage were based on standard P approach. The
P total
active area for the two MUXs was WTG L + WINV
P area for the PS and
the output stage was WTG L + WINV L = 4.32µm2 .
The total active area of the digital block was approximately
184 µm2 . Fig. 10 shows the 16 channel output square
waveforms digitally selectable through MUX1, MUX2
and PS. Since the FD circuit is relatively simple and
symmetrical it was easy to express all transistor widths as
function of one variable WN (WP = 3WN for INV and
WTG = 2.5WN for TG) for the purpose of optimization.
The optimum FD device-width WN vs. power and area was
then determined through simulations. Table 1 summarizes

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 I. A. A. Al-Darkazly, S. M. R. Hasan: Dual-Band WFG With Ultra-Wide Low-Frequency Tuning-Range
FIGURE 11. Power versus generalized width WN .
these results. WN , WP and WTG are thus the weight
factors for area and power consumption. The optimal design
was achieved by constraining these weight factors without
impairing circuit performance. In terms of area consumption,
obviously circuit with small W consumes small silicon area,
while using small W can also reduce power consumption,
but the circuit may not functional properly. Fig. 11 shows
the proportionality relationship between power consumption
and WN . However, values of W that are too small leads
to increase in the effective switching resistance of the
logic gate and decreases the inverter gain. Consequently,
for optimum operation and to improve the inverter gain,
slightly oversize WN was chosen. High gain logic gate
also enhances the resolution of any metastability in the
logic signals. The effect of supply-voltage scaling on the
power dissipation of the FD circuit was also investigated.
To evaluate low-power performance, the supply-voltage is
varied from 0.6V to 1.2V yielding the power and frequency
variations shown in Fig. 12 and Fig. 13 respectively.
FIGURE 12. Power dissipation versus supply voltage of the FD circuit.
FIGURE 13. WFG frequency versus supply voltage.
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FIGURE 14. The simulated speed-power trade-off of the FD circuit.
The FD circuit dissipates 0.45mW at input frequency
of 10.3 kHz with VDD = 0.6V, 1.1mW at input
frequency of 13.5 kHz with VDD = 0.8V, 2.1mW at
input frequency of 17 kHz with VDD = 1V and,
3.6mW at input frequency of 20 kHz with VDD = 1.2V.
The input frequency is the WFG frequency at a particular
supply-voltage. Fig.14 shows the simulated speed
(WFG frequency)-power trade-off of the FD circuit. The
symbol ‘‘’’ represents the point of the best (optimal)
power and accurate functionality trade-off. Using VDD of
+1V indicates acceptable power-frequency trade-off. The
simulation results thus indicate that the designed WFG core
is able to generate up to 17 kHz with a power consumption of
only 0.457mW (using ±1V), while the FD circuit consumes
2.1mW (using +1V), resulting in total power dissipation of
only 2.557mW. The effect of the tuning range (using V_tune)
of the gm -C integrator on the overall power dissipation of
the proposed circuit with CL = 10pF was also investigated.
Fig. 15 displays the result for frequency and power vs. V_tune
varied in the range ±0.9V. The proposed circuit dissipates
2.5mW at 5.8kHz (with V_tune = − 0.9) and 5.8mW at a
high frequency of 1003kHz (with V_tune = 0.9).
FIGURE 15. The simulation result for power and frequency versus V_tune.
The optimal transistor dimensions and passive component
values for the proposed analog WFG are displayed in Fig. 2,
while, for the FD WN = 2µm (so that, WP = 6µm and
WTG = 5µm) was chosen with L = 130 nm. The optimal
performance is presented in Table 2. For the TG, PMOS and
NMOS devices have same device-size and hence identical
layout geometry.
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I. A. A. Al-Darkazly, S. M. R. Hasan: Dual-Band WFG With Ultra-Wide Low-Frequency Tuning-Range
TABLE 2. Simulation results for the outputs of the designed circuit.
V. ROBUSTNESS OF THE WFG CIRCUIT
A. TEMPERATURE VARIATION
The temperature dependence of the circuit was investigated to
test the frequency stability. For the set bias currents, and fixed
values of Rref = 15 k, R = 10k and C = 10pF, varying
the temperature in the range −50◦ C to 120◦ C, the change
in frequency is plotted in Fig. 16. The results indicate that
the oscillation frequency stability is maintained within −5◦ C
to +100◦ C, with small positive and negative deviations in
the 100◦ C to 120◦ C and −5◦ C to −50◦ C ranges respectively
compared to the value at 27◦ C.
FIGURE 16. Analysis of the frequency stability with temperature
variations.
B. EYE DIAGRAM ANALYSIS
An eye diagram provides useful graphical quality analysis of
a generated (source) signal and the transfer of digital data
streams. Eye diagram was employed on Mentor Graphics
platform for the time-domain simulations to examine the
variations in amplitude and timing errors (jitter) of the
oscillations. Fig. 17 shows the eye diagram of the proposed
WFG output. Eye height (the vertical opening) can be
determined from the bit amplitude and the eye noise as,
Eye Hight = (VH − 3σ ) − (VL + 3σ )
Also, the eye width (the horizontal opening) can be
determined from the bit period and the eye jitter as,
Eye Width = (tcros sin g2 − 3σcros sin g2 )
− (tcros sin g1 + 3σcros sin g1 )
VOLUME 4, 2016
Where σ is the standard deviation for the eye height and
eye width events, ‘‘3-sigma’’ (3σ ) represents the abnormal
variations, while tcrossing1 and tcrossing2 are the time-base
crossing points. As seen in Fig. 17, eye height and eye width
are equal to the amplitude and bit period respectively of the
simulation results which indicate ideal circuit performance.
FIGURE 17. Eye diagram simulation results for the designed WFG.
FIGURE 18. Chip photo-micrograph of the mixed-signal waveform
generator.
VI. FABRICATION AND EXPERIMENTAL RESULTS
A prototype of the proposed waveform generator was
fabricated in 130 nm 8RF-DM IBM (now GF) CMOS
through MOSIS. The microphotograph of the chip is shown
in Fig. 18. The analog and digital sub-blocks and the
significant passive component (load capacitor) are labelled
on the photo with an overall chip-area of 18426 µm2
(includes all interconnects). Separate supply and ground
bond-pads are used for the analog and digital circuits in
order to prevent noise and spikes that may affect the output
signals. In addition, digital circuit blocks are isolated by
high-resistance substrate enclosures to eliminate the substrate
crosstalk. The experimental set up using the fabricated chip
is shown in Fig. 19. For undertaking measurements, the
(18) chip was mounted using a 15 × 15 matrix PGA kit socket,
while the wiring connections were made through solder-less
breadboard. Transient measurements were carried out using
the Tektronix TBS1102B-EDU digital storage oscilloscope
to evaluate signal quality and to calculate important signal
(19) characteristics. The on-chip current mirror resistor Rref
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 I. A. A. Al-Darkazly, S. M. R. Hasan: Dual-Band WFG With Ultra-Wide Low-Frequency Tuning-Range

E1 and LY metal layers. Metal layers QY and LY constitute

FIGURE 19. Experimental measurement set up for the fabricated
oscillator.
and the positive feedback resistor R are fabricated on a
reasonably small silicon area employing high sheet resistance
p+ polysilicon (OPRRP) resistors (with sheet resistance of
1700/). The load capacitor of the gm -C integrator was
implemented as a metal-insulator-metal (MIM) capacitor to
reduce thermal and parasitic effects. It is built between the
respectively the top and bottom plate layers while FT via is
used for access to separate E1 interconnect metal layers. The
size of the capacitor was calculated using estimates in [34]
for the capacitance of a mimcap given by:
Cmim = (CA . L . W) + [CP . 2 . (L + W)] (20)
Where, CA is the plate-area capacitance in fF/mm2 and
Cp is perimeter (fringing) capacitance in fF/mm which are
provided in the CMOS8RF Design Manual [34]. L and W are
the designed length and width of the top-plate on QY layer
in µm.
Oscilloscope trace of the output square waveform is
presented in Fig. 20 (a), while, Fast Fourier Transform (FFT)
of the time domain waveform is also performed simul-
taneously and displayed in Fig. 20 (b). The triangular
waveform signal, and the clk with clk_bar signals (with
rail-to-rail swing) is shown in Fig. 20 (c) and (d) respectively.
For analog WFG measurement the supply rail of ±1V
was used, while all digital measurements are performed
using +1V. The measured amplitude (P-P) and frequency for
the core oscillator circuit are around 1.49 V and 16.85 kHz
respectively, which closely matches the simulated values.
The small variations between simulated and measured results
are mostly due to slight process related deviation of passive

FIGURE 20. Measured chip outputs, (a) square waveform of the core oscillator, (b) FFT spectrum analysis of the generated square waveform signal,
(c) triangular waveform of the integrator, and (d) clock and clock_bar translation outputs.

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I. A. A. Al-Darkazly, S. M. R. Hasan: Dual-Band WFG With Ultra-Wide Low-Frequency Tuning-Range
component values and OTA (and/or gm -cell) bias current
imbalances. Usually, the frequency of most CMOS oscillators
may diverge by a factor of two after fabrication, hence,
the design step requires an adequate tuning range to ensure
that the output frequency can be adjusted to the desired
value. Amplitude and frequency of the proposed WFG can
be controlled independently, by adjusting R or through
variation of the OTA bias current IB3 , and by variation of
the gm -cell bias current IB4 respectively. Hence appropriate
amplitude and frequency tuning range can be achieved to
accommodate process and temperature variation as well as
for the requirement of a specific application.
A. AMPLITUDE CONTROL
The chip was tested to determine the amplitude control
behavior. The peak-to-peak output voltage can be
monotonically controlled by either the bias current IB3 or the
resistor R as per the theoretical analysis. Fig. 21(a) and (b)
shows the results of the measured amplitude control and
its comparison with the simulation. For measurements IB3
variation is achieved through gate-voltage V_tune and the
variation of R through external resistance at accessible
terminal (I/O pad) to form composite variable R element.
The amplitude (P-P) of the measured square waveform
varies from 1.2 V to 1.8 V (for fixed R = 10k) with
FIGURE 21. Amplitude (P–P) variation comparing measured results and
simulation, (a) with V_tune bias current IB3, and, (b) with R.
VOLUME 4, 2016
IB3 variation between 20 µA to 60 µA (equivalent V_tune
variation between −0.88V to −0.695V). On the other hand,
amplitude (P-P) variation of 1.1V to 1.8V (for fixed IB3 =
33µA) can be achieved with R variation between 1 k to
20 k. The simulated and measured profiles are almost
co-incident. The results confirm that the output voltage of the
waveform generator is controllable by the bias current IB3 as
well as by the resistor R.
B. FREQUENCY CONTROL
The circuit was also tested to determine the frequency
tunability. The output signal frequency can be controlled
independently by adjusting the bias current IB4 of the gm -cell
through tuning voltage (V_tune) of the bias device M15. In
particular, the bias voltage (V_tune) for the integrator (STG4)
is pre-set to – 0.808V, with the on chip load capacitor of the
integrator fixed at 10 pF. The WFG in this setting generated
a square/triangular waveform with oscillation frequency of
around 17 kHz. In order to verify the tunability, with respect
to the gm -C tuning, simulations and measurements have been
performed with different load capacitors. As V_tune is varied
in the range ±0.9V, tuning ranges of 5.3 kHz - 1003 kHz,
0.58 kHz - 94 kHz and 58 Hz - 10.6 kHz can be achieved
for 10pF, 100pF and 1000pF respectively. The variation of
CL is achieved using external capacitor at the accessible
terminal (I/O pad) to form composite variable CL element.
Fig. 22 (a), (b) and (c) depicts the plot of the oscillation
frequency vs. V_tune. These results validate the design in
a wide frequency range with good linear range between
−0.6V to +0.6V. The small variations between simulated
and measured results are attributable to fabrication process
related deviation of passive components and also due to the
output (and/or bias) DC current imbalances of the OTAs.
For a bias voltage beyond ±0.6V the gm of the integrator’s
differential pair (M7, M8) saturates since the tail device
M15 enters the ohmic or the weak inversion region [9].
Hence the frequency variation also tends to saturate for
V_tune beyond ±0.6V. On the other hand, a bias voltage
above ±0.9V heralds the onset of signal distortions. These
results indicate that a small DC bias current along with small
W7,8 /L7,8 device ratio of the integrator, can accommodate
a wide linear frequency tuning range along-with low power
consumption. Since the integrator frequency characteristic is
determined by the gm /CL ratio, a wide tuning range can be
achieved, and in addition, process variation and temperature
dependencies can also be compensated by tuning the gm of
the integrator. Further, a much wider frequency range can
also be provided through the FD digital block at the output
of the PS circuit. For C = 10pF the core WFG can be tuned
from 6.44kHz-to-1003kHz, and, in addition a tuning range of
8.5 kHz to 0.24Hz can be generated through the divide-by-2
FFs for the preset V-tune of −0.808V. As a result, the
WFG along with FD circuit provides two bands with a wide
range of frequencies distributed from 6.44kHz-to-1003kHz
(band I) and 0.1Hz to 502kHz (band II) which is extremely
large. Table 3 summarizes the oscillator frequencies of the
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 I. A. A. Al-Darkazly, S. M. R. Hasan: Dual-Band WFG With Ultra-Wide Low-Frequency Tuning-Range
FIGURE 22. WFG tuning for (a) C=10 pF, (b) C=100 pF and (c) C=1000 pF.
WFG core (band I) for C=10 pF with V_tune varied from
−0.9V to +0.8V and the corresponding frequencies of
the divide-by-2 FD circuit which can be digitally selected
from 16 channels through the PS circuit (band II). Other
output wave shapes including sinusoidal waveform may be
generated by feeding the output of the integrator (triangular
waveform) into a low pass filter [36].
Finally Table 4 shows a comparison of the proposed
design with other reported works. The comparison clearly
indicates that the proposed design achieves the widest
frequency range as well as the lowest frequency which is
digitally selectable. Also, the proposed design is fully CMOS
integrated, achieving the most optimized power dissipation
compared to the other designs in the table.
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TABLE 3. Tuning range of the WFG core (band-I) and the FD path selector
(band-II).
TABLE 4. Comparison of proposed design with other reported works.
VII. CONCLUSION
A low-power mixed-signal waveform generator IC with
dual-band wide-range low-frequency oscillations, utilizing
analog gm -C tuning along with digital Frequency-Divider
have been presented. The circuit provides square/triangular
waveforms along-with its complementary signal for
low-frequency electrical stimulation applications. This low
power generator is particularly important for battery-operated
biomedical devices, enabling the reduction of the overall
system cost. Bio-electric stimulation experimentation using
this ultra-wide waveform generator can be carried-out
through an active electrode in contact with low-resistance
skin surface.
ACKNOWLEDGMENT
The authors wishes to acknowledge chip fabrication support
from MOSIS, USC.
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IBTISAM A. ABBAS AL-DARKAZLY received
the master’s degree in engineering from the
Auckland University of Technology, in 2005.
She is currently pursuing the Ph.D. degree in
electronics and computer engineering with Massey
University, Auckland, New Zealand. She is a
member of the Centre for Research in Analog and
VLSI Microsystem Design. Her research interests
include the design of biomedical integrated
circuits.
S. M. REZAUL HASAN (SM’02) received
the Ph.D. degree in electronics engineering
from UCLA, in 1985. From 1983 to 1986,
he was a VLSI Design Engineer with Xerox
Microelectronics, El Segundo, CA, where
he worked in the design of CMOS VLSI
microprocessors. In 1986, he moved to the
Asia-Pacific region and served several institutions,
including Nanyang Technological University,
Singapore (1986-1988), the Curtin University of
Technology, Australia (1990-1991), and Universiti Sains Malaysia, Malaysia
(1992-2000). At University Sains Malaysia, he was an Associate Professor
and a Coordinator of the Analog and VLSI Research Laboratory. He spent the
next four years (2000-2004) with the United Arab Emirates, where he served
as an Associate Professor of Microelectronics, Integrated Circuit Design and
VLSI Design with the Department of Electrical and Computer Engineering,
University of Sharjah. While in Sharjah, he received the Sharjah Award
for outstanding publication in IC design. He leads the Analog and VLSI
Design Research Group with Massey University, New Zealand, where he is
serving as a Senior Faculty Member in Computer Engineering. He has so
far published 62 journal and 100 conference papers in the areas of analog,
digital, RF and mixed-signal IC design, MEMS sensors, bioelectronics, and
VLSI design. His current areas of interest include analog integrated circuit
and VLSI microsystem design, CMOS MEMS sensors, and biological circuit
design.
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