A SystemC cycle-accurate Simulator for On-Chip Networks

Shruthi R
Assistant Professor
Dept of ECE
NIE,Mysuru
 Performing Modifying Source
Simulations Code

• Design Space Exploration • New Routing Algorithms

• Effect of Traffic Patterns • Different topologies
• Power Estimation • Power Saving Strategies
• Comparison Analysis
 4.22
4.12 4.09 4.12

3.41 3.47
3.23 3.31
3.21
N/w throughput

2.98 3.06
2.96

0.1 0.2 0.3 0.4

XY ODD-EVEN DyAD
Packet injection rate
 6
5.69 5.65 5.67

5 5
4.99 5
4.99 5

4.5
4.16
4
N/w throughput

3.38
3 3.07

0
Random Transpose1 Transpose2 Bit reversal
Traffic type XY ODD-EVEN DyAD
 5

4.5

3.5
N/W THROUGHPUT

2.5

1.5

0.5

0
4*4 8*8 16*16 32*32 64*64
PACKET SIZE XY ODD-EVEN Dyad