Language Elements

• Identifiers
• identifier names consist of letters, digits,
_ (underscore), and $ character
• first character in an identifier name must be
a letter or _ (underscore)
• keywords (reserved identifiers) are lower case

• Comments
• // for single line comments
• /* and */ for multi-line comments

EE 310 1
 Language Elements

• Format
• Verilog HDL is case sensitive
• Verilog HDL is free format
• statements are terminated with ;

• System Tasks
• built-in system tasks begin with $ character
• $display(“Hi”); (displays the specified message)
• $time (returns the current simulation time)

EE 310 2
 Compiler Directives
• `define (text substitution)
`define MAX_BUS_SIZE 32
reg [`MAX_BUS_SIZE - 1 : 0] AddReg;

• `ifdef, `else, `endif (conditional compilation)

`ifdef WINDOWS
parameter WORD_SIZE = 16;
`else
parameter WORD_SIZE = 32;
`endif

• `include (include content of a file)

`include “primitives.v”

• `timescale (specify time unit and precision)

`timescale 1ns / 100ps
5.22 → 5.2ns, 6.17 → 6.2ns

EE 310 3
 Value Set (Four Valued Logic)

• 0 (logic 0)
• 1 (logic 1)
• Z (high impedance)
• a wire that is not driven to 0 or 1, e.g. tristate driver
• X (unknown)
• the simulator cannot decide the value, e.g. initial state
of flip-flops
• a wire that is being driven to 0 and 1 simultaneously

EE 310 4
 Parameters

• Three types of parameters

• Integer, Real, String

• Integer
• parameter size = 32;

• Real
• parameter pi = 3.14;

• String (sequence of characters within double quotes)

• parameter message = “Error !”;

EE 310 5
 Integers
• Simple Decimal Format
• A negative number is represented in two’s complement form
• 6 00000000000000000000000000000110
• -6 11111111111111111111111111111010

• Base Format
• [size] ’ [signed] base value
• size (decimal specification of number of bits)
• signed (if specified, the number is signed)
• s or S → sign
• base (arithmetic base of the number)
• d or D → decimal
• h or H → hexadecimal
• b or B → binary
• value (value in the specified base)

EE 310 6
 Integers

6’d6 000110
6’b010_111 010111
if (select == 00)
6’h3A 111010 e = 2;
else if (select == 01)
-6’h3A 000110
e = 4;
else if (select == 10)
6’sh3A 111010 e = 6;
-6’sh3A 000110 else
e = 8;
3’b10011 011
3’sb10011 011

EE 310 7
 Data Types
• Net
• it represents a physical connection.
• its default value is Z.
• if a net is not declared in a Verilog model, by default,
it is implicitly declared as a 1-bit net.
• it cannot be assigned in an initial or always block.

• Net Types (wire, …)

• Syntax wire [signed] [msb : lsb] net1, net2, …, netN;

• Examples
wire Start, Ready;
wire [2:0] Addr;
wire signed [7:0] pwdata, prdata;

EE 310 8
 Data Types
• Variable
• it represents an abstract data storage.
• its default value is X.

• it can only be assigned in an initial or always block.

• Variable Types (reg, integer, …)

• Reg Variable
• Syntax reg [signed] [msb : lsb] reg1, reg2, …, regN;
• Examples
reg Cnt; reg [3:0] Sat;
reg signed [3:0] rsp;

• Integer Variable
• it contains a 32-bit signed integer.
• Syntax integer integer1, integer2, …, integerN;
• Examples
integer a, b;
EE 310 9
 Data Types

reg signed [31:0] a, c, e, g;

reg [31:0] b, d, f, h;

a = 6; // binary 0000...00110 , decimal 6

b = 6; // binary 0000...00110 , decimal 6

c = -6; // binary 1111...11010 , decimal -6

d = -6; // binary 1111...11010 , decimal 4294967290

e = 4’b1001; // binary 0000...01001 , decimal 9

f = 4’b1001; // binary 0000...01001 , decimal 9

g = 4’sb1001; // binary 1111...11001 , decimal -7

h = 4’sb1001; // binary 1111...11001 , decimal 4294967289

EE 310 10
 Data Types
reg [31:0] a, b, c, d;

a = 58 * 58; // 3364
reg [3:0] a; b = 6’h3A * 6’h3A; // 3364
reg signed [3:0] a_signed;
reg signed [3:0] b_signed; c = -6 * -6; // 36
reg signed [7:0] c; d = 6’sh3A * 6’sh3A; // 36
reg signed [7:0] d;

a = 6; // binary 0110 , decimal 6

a_signed = 6; // binary 0110 , decimal 6
b_signed = -6; // binary 1010 , decimal -6

c = b_signed * a_signed; // binary 11011100 , decimal -36

d = b_signed * a; // binary 00111100 , decimal 60

EE 310 11
 Data Types
• Array

reg [msb : lsb] array_name [upper_address : lower_address];

reg [msb : lsb] array_name [lower_address : upper_address];

reg [15:0] My_Ram [7:0];

reg [15:0] My_Ram [0:7];

reg [3:0] my_rom [4:1];

my_rom = 16’hA8F2; // (Not allowed)
my_rom [2:1] = 8’hAF; // (Not allowed)
my_rom [1] = 4’hA;
my_rom [1][1:0] = 2’b11;
my_rom [1][2] = 1’b0;

EE 310 12
 Data Types

• Array

parameter WORD_LENGTH = 8, NUM_WORDS = 64;

reg [WORD_LENGTH-1:0] mem_a [NUM_WORDS-1:0],
mem_b [NUM_WORDS-1:0];
integer i;

// mem_a = mem_b (Not allowed)

for (i = 0; i < NUM_WORDS; i=i+1)
mem_a [i] = mem_b [i];

EE 310 13
 Expressions

An expression is formed with operands and operators.

result_value = operand operator operand operator operand … ;

EE 310 14
 Operands

• Parameter (constant)

• Net (both scalar (1-bit) and vector (multi-bit))

• Variable (both scalar (1-bit) and vector (multi-bit))

• Bit Select (vector[bit_select_expr], e.g. State[1])

• Array Element (memory[word_address], e.g. Sram[10])

EE 310 15
 Operands

• Part Select

vector [msb_const_expr : lsb_const_expr], e.g. State[4:1]

vector [base_expr +: const_width_expr]

vector [base_expr -: const_width_expr]
integer mark;
wire [31:0] gpio_data;
gpio_data [0 +: 8] // same as gpio_data [7:0]
gpio_data [31 -: 16] // same as gpio_data [31:16]
gpio_data [mark +: 4] // selects bits mark + 3, mark + 2, mark + 1, mark
gpio_data [mark -: 4] // selects bits mark, mark - 1, mark - 2, mark - 3

EE 310 16
 Operators
• Arithmetic ( +, -, *, /, %, ** )
• Relational ( <, <=, >, >= )
• Equality ( ==, !=, ===, !== )
• Logical ( !, &&, || )
• Bitwise ( ~, &, |, ^, ~^ )
• Reduction ( &, ~&, |, ~|, ^, ~^ )
• Logical Shift ( >>, << )
• Arithmetic Shift ( >>>, <<< )
• Conditional ( ? : )
• Concatenation ( {,} )
• Replication ( {integer{ }} )

EE 310 17
 Operator Precedence
and Associativity
In the following table, operators are listed from the highest
precedence (top row) to the lowest precedence (bottom row).
Operators in the same row have identical precedence.

All operators associate left to right except for the conditional

operator that associates right to left.
A + B – C is evaluated as (A + B) – C
A ? B : C ? D : F is evaluated as A ? B : (C ? D : F)

Parentheses can be used to change the order of precedence.

a = b << 2 + c << 4 + d;
a = (b << 2) + (c << 4) + d;

EE 310 18
 Operator Precedence Table

EE 310 19
 Operator Precedence Table

EE 310 20
 Operators

• Arithmetic Operators ( +, -, *, /, %, ** )
• if any bit of an operand is an x or z, the result is x.
• Examples
7/4 (result = 1)
7 % 4 (result = 3)
2 ** 10 (result = 1024)

reg [3:0] Arc, Bar, Crt;

reg [4:0] Frx;
Arc = Bar + Crt; (4-bit result, overflow)
Frx = Bar + Crt; (5-bit result, no overflow)

EE 310 21
 Operators

• Relational Operators ( <, <=, >, >= )

• the result is 1 (true) or 0 (false).
• if any bit of an operand is an x or z, the result is x.
• Examples
23 > 45 (result = 0)
52 < 8’hxF (result = x)

• Equality Operators ( ==, !=, ===, !== )

• for (==, !=), if any bit of an operand is an x or z, the result is x.
• for (===, !==), x and z are compared as values, the result can
never be x.
• Examples
Data = 4’b11x0; Addr = 4’b11x0;
Data == Addr (result = x)
Data === Addr (result = 1)

EE 310 22
 Operators

• Logical Operators ( !, &&, || )

• the result is 1 (true) or 0 (false).
• non-zero vector operand is treated as 1.
• Examples
A = 4’b0110; B = 4’b0100; C = 4’b0000;
A && B (result = 1)
!C (result = 1)

• Reduction Operators ( &, ~&, |, ~|, ^, ~^ )

• they operate on all bits of a single operand and
produce a 1-bit result.
• Examples
A = 4’b0110; B = 4’b0100;
| B (result = 1)
~& B (result = 1)
~^ A (result = 1)

EE 310 23
 Operators
• Bitwise Operators ( ~, &, |, ^, ~^ )
• they operate bit-by-bit on corresponding bits of
the vector operands and produce vector result.
• Examples
A = 4’b0110; B = 4’b0100;
A | B (result = 0110)
A ^ B (result = 0010)

• if the operands are unequal in length and either operand

is an unsigned operand, the smaller operand is zero-filled
on the most significant side. if both operands are signed,
then the smaller operand is sign-extended to the width of
the largest operand before the operation.
4’b0110 ^ 5’b10000 (result = 10110)
5’b00110 ^ 5’b10000 (result = 10110)
4’sb1010 & 8’sb01100010 (result = 01100010)
8’sb11111010 & 8’sb01100010 (result = 01100010)

EE 310 24
 Operators
• Logical Shift Operators ( >>, << )
• they shift the left operand by the right operand number of times.
• Examples
reg [7:0] Qreg, Preg;
Qreg = 8’h17;
Preg = Qreg >> 2; (result = 00000101)
Preg = Qreg << 2; (result = 01011100)

• Arithmetic Shift Operators ( >>>, <<< )

• left shift fills the vacated bits with 0’s. in case of right shift,
if the left operand is unsigned, the vacated bits are filled
with 0’s, else it is filled with the sign bit (most significant bit).
• Examples
reg signed [3:0] sqreg, spreg;
sqreg = 4’b1011;
spreg = sqreg >>> 2; (result = 1110)
spreg = sqreg <<< 2; (result = 1100)
Preg = Qreg >>> 2; (result = 00000101)
Preg = Qreg <<< 2; (result = 01011100)
EE 310 25
 Operators
• Conditional Operator ( ? : )
• cond_expr ? expr1 : expr2
• Example
D = A > 24 ? B : C;

• Concatenation Operator ( {,} )

• { expr1, expr2, …, exprN }
• Examples
wire [7:0] Dbus;
Dbus = {Dbus[3:0], Dbus[7:4]}; // swap lower and upper 4 bits

• Replication Operator ( {integer{ }} )

• { repetition_number { expr1, expr2, …, exprN } }
• Examples
{3{1’b1}} (result = 111)
{{4 {Dbus[7]}}, Dbus}; // sign extension
EE 310 26