Microprocessor [ECC15101]

Maximum mode 8086 System

• In the maximum mode, the 8086 is operated by strapping the MN/MX to ground.
• Minimum mode generates control signals itself.

•There are not enough pins on the 8086 for bus control during maximum mode, so it requires addition of the
8288 bus controller.
•Maximum mode used only when the system contains external co-processors such as 8087.

•In this mode, the processor derives the status signal S2, S1, S0.
Bus controller (8288) derives the control signal using this status information.

•The other components in the system will remain same.

•Status inputs
are connected to
the status output
pins on 8086/8088.

–three S2, S1, S0

signals decoded to
generate timing
signals

MRDC/MWTC: Memory Read/Write Command, AMWC/AIOWC: Advance I/O Write

Command/Advance Memory Write Command
Maximum mode 8086 System

•The clock input provides internal timing. –must be connected to the CLK output pin of the 8284A clock
generator.
•The address latch enable (ALE) output is used to de-multiplex the address/data bus.
•The data bus enable (DEN) pin controls the bidirectional data bus buffers in the system.
•Data transmit/receive (DT/R) signal output to control direction of the bidirectional data bus buffers.
•The address enable (AEN) input causes the 8288 to enable the memory control signals.

•The control enable (CEN) input enables the command output pins on the 8288.
•The I/O bus (IOB) mode input selects either I/O bus mode or system bus mode operation.
•Advanced I/O write (AIOWC) is a command output to an advanced I/O write control signal.

•The I/O read command (IORC) output provides I/O with its read control signal.
•The I/O write command (IOWC) output provides I/O with its main write signal.
•The advanced memory write (AMWTC) control pin provides memory with an early/advanced write
signal.memory write (MWTC) control pin provides memory with its normal write control signal.
•The
•The memory read (MRTC) control pin provides memory with a read control signal.
•The interrupt acknowledge (INTA) output acknowledges an interrupt request input applied to the INTR pin.
•The master cascade/peripheral data (MCE/PDEN) output selects cascade operation for an interrupt controller
if IOB is grounded, and enables the I/O bus transceivers if IOB is tied high.
Maximum mode 8086 System
Maximum mode 8086 System

Bus status code

AIOWC/AMWC (Advance I/O Write Command/Advance Memory Write Command) [Similar to Tw]:
These signals are similar to IOWC and MWTC except that they are activated one clock pulse earlier. This
gives slow interfaces an extra clock cycle to prepare to input the data.

Wait states, called Tw (in minimum mode), can be inserted in a bus cycle to help the processor to interface
with slow memory or I/O devices
Maximum mode 8086 System
Maximum mode 8086 System