B.M.

S College of Engineering
P.O. Box No.: 1908 Bull Temple Road,
Bangalore-560 019

DEPARTMENT OF INFORMATION SCIENCE & ENGINEERING

Course –Digital Logic Design

Course Code –19IS3PCDLD
AY 2021-22

Title:
[Write your title here]

Submitted to – Dr V Shubha Rao

Submitted by -
M G Aditya C S Prithvi Raghavan
1BM18IS051 1BM18IS072

B.M.S College of Engineering

P.O. Box No.: 1908 Bull Temple Road,
Bangalore-560 019
 DLD Tutorial-4 [LOGISIM]
1. To Study the operation of logic gates – AND, OR, NOT, NAND, NOR, EX-OR.

2. To design and setup a half adder and full adder using

i) EX-OR gates and basic gates

Half Adder
 Full Adder
ii) NAND gates only

Half Adder
 Full Adder

3. To design and setup a half subtractor and full subtractor using

i) EX-OR gates and basic gates

 Half Subtractor

Full Subtractor
ii) NAND gates only

Half Subtractor
 Full Subtractor

DLD Tutorial-5 [LOGISIM]

1. Realize the given 4-variable expression using 8:1 MUX and 4:1 MUX.

i) f(a,b,c,d)= Σm (0,1,2,3,4,6,7,11,12,15)
ii) f(a,b,c,d)= πM (2,3,5,12,14) + dc(0,4,8,10,11)
2. To design and setup a full adder and full subtractor using 3:8 decoder
3. To realize and illustrate the working of a 1-bit comparator.
 DLD Tutorial-6 [LOGISIM]

1. Realize a J-K Master Slave Flip-Flop using NAND gates and verify its truth table.
2. Realize SR Flip-Flop, D Flip-Flop and T Flip-Flops and verify its truth table.
3. Design and implement a ring counter using 4-bit shift register
4. Design and implement a Johnson counter using 4-bit shift register

DLD Tutorial-7 [LOGISIM]

1. Design and implement a mod-5 synchronous up counter using J-K Flip-Flops.

2. Design and implement a 3-bit synchronous up counter.
3. Design and implement a 3-bit asynchronous down counter.

DLD Tutorial-8 [LOGISIM]

1. Design and implement a synchronous sequential circuit using Moore model to detect
a sequence of 110.

2. Design and implement a synchronous sequential circuit using Mealy model to detect
a sequence of 110.