1t can be programm ea as u 1- uiu.., v ..

~•·-·
• d witn 01 vv - - ·----~ " 's 1c11 : 1

C3 ·rco ).
lllJ V ~ • · · -··
· output port, an
• Port B can be pro arammed as mput or (P ·t c upper) and P - (Port C low
• Port C is aro upe; in two 4 bit ports : pC4- PC7 . Co1lines can be individually set or reset tir}-----ca~h
o . . tput port. Port gene .
can be proara mmed as input 01 ou . rc1t~
control sia1~a ls for contro lling ex tema l J/O devices .
e,

0~' 8~:5:i..t\.
1~ C I I I~., E ( ri.., lJ 1~ I_ti
;i

9 .2 111 .1 \ 1
1

F. .
.
I (a) and pm diagram of 8255A is h
_
. . . , .. shown 111 ig. 9
55A 15 .. C . ct s own .1
The mternal organ1sat1on of tht: 82 p t B two 4 bit ports- Po~ uppei _a n P011 Clower ct n
Fig. 9. 1(b) . It has two 8 bit ports- Port A 311d or ' . rammed to fun ct10n as an mput or an outp ' ata
bu~ buffer and read/write con trol logic. Port can be p;°g When the ports are defined as input the;t Pon.
When the 'ports are defined as output, th ey act as latcdlGes . UIJ B controls p01i Band lower port
ort C an ro
act a\ C.
d
buffers. Group A contro ls port A an upper P '
-------7
Group A 1/0
Port A PA7- PAQ
Group A
(8)
Control

Bi-directional Group A
Data Bus 1/0
Port C
Data PC7- PC4
Upper
D7-D0 Bus (4)
Buffer

Group B
1/0
8 bit Port C PC3- PCC
Internal Lower

RD
Data Bus
l __(_4 )_ ___,

WR
Read
Write
A1 Control 1/0
Group B
Logic PB7- PBO
AO Group B Port B
Control (8)
RESET

cs - - --~

Figure 9.l(a) Block diagram of Intel 8255A programmable peripheral interface

Read/ write control logic bas six lines. Their functions are as fo11ows :
• CS Signal is the master select- when this pin is low, it selects the entire ch ip .
• A] and AO select th e specific ports and control register as shown in Table 9 . 1.
 C hapter 9
- _ _.::_ fi ')'---;c:-l ,r::.., / \ I' I"( )II
•
- - - - ,.., 1.i1111 n, il,l 1• I',1 1··'I 1 IH 'r, ii I 1 , I 1 · 1 I. w1 • 229 : :

/ Selection o.f s ,--11 LLI

,, ·,··I C J101 ts , 11 I 1' 0 11 I · I
. .. ' ' ·
1:\1/ '" l'l'\ 1s t,,r
.·
{
--
cs A I I\O
(

l'o rl
() 00 I\
Ll 01 I\
Ll 10 l'
0 ll Conlrol l~egislC'r

PA3 1 40 PA4
PA2 2 39 PA5
PA1 3 38 PA6
PAO 4 37 PA?
RD 5 36 WR
cs 6 35 RESET
GND 7 34 DO
A1 8 33 01
AO 9 32 02
PC7 10 31 03
8255 04
PC6 11 30
PCS 12 29 05
PC4 13 28 06
PCO 14 27 07
PC1 15 26 vcc
25 PB7
PC2 16
24 PB6
PC3 17
23 PB5
PBO 18
22 PB4
PB1 19 PB3
PB2 20 21

Figure 9.l(b) Pin dingra111 of 8255A

' RD, an active low control signal, is input to the 8255A and enables the read operation. When the
signal is low, the microcontroller reads the data from a selected I/0 port.
' IVR, an active low control signal, is input to the 8255A and enables th e write operation. When the
signal is low, the microcontroller writes the data into a selected 1/0 port or control register.
1
RESET is an active high signal; when this signal goes high , it clears the control register and all ports
(port A, port B and port C) are defined as input.
C:mtroI Register
"'.~ register is an g bit register, and its content is called control word. Control register controls the over
1
"?:rations of the 8255A Control register is divided into two blocks-Group A control and Group B
'.. rol, (',ioup
. A control controls
. the port A and upper port C, and gioup B control, controls the port B and
r •

1,.,,h, ·
er Port C F1gure
· 9.2 ' shows the functt0n· s of contro I word , an d contro I regi.ster must be programmed to
lfD7aoperalto ns or Port A, Band C. The 8255 operates m BSR mode or 1/0 mode as shown in Fig. 9 .2.
1,, O, port C operates in the bit set/reset (BSR) mode. In this mode, any of the eight bits of port C is
··. ""-ed
1 by " ·ng D3, D2 and DJ bits and 1t · set or reset bY DO b.I t as s hown m
· 1s . F,g.
. 9.3 . These can be used
s1
- er;ite st - be signals
· 10 · ·
for co ntrolling ex terna l d ev1ces
· .
 v_ /\
_j _
>l l___
li cc1_lion s
•• 230
•• t)()_r:i l l'vl inol'1H1trn ll (•1': 11 ,H( I w
·,
,ii t , ·
1 ;(1 ! [ \ V, ) l"l ' N
_ ---

Cn1111,1I Wrn d

1 1) j 1\, I I l ,, I I l, I I
1 l ,1 \ I 1.· \ 111 I >o I
1
(,ro1Jp U
--------
-- ·r;n,1 <; (lowur I 'C ~-PGO)
1. inpul
0 (Jill i-J UI

- -1'o;i I~
-- --- --------
1 = input
o output
Mode selection
o = mode 0
1 = mode 1

Group A

Port C (lower PC7-PC4)

1 = input
O = output
Port A
1 = input
0 = output

Mode selection
00 = mode O
01 = mode 1
1X = mode 2

i = 1/0 Mode
0 = BSR Mode

Figure 9.2 Control word format of 8255A (Courtesy In tel)

07 06 05 04 03 02 01 00
0 X X X Bit Select SiR

BSR Mode
Set = 1
Not Used Reset == O
Generally set =0
000 == Bit 0
001 == Bit 0
010 == Bit 0
011 == Bit O
100 == Bit 0
101 == Bit O
110 = Bit o
111 = Bit O

Figure 9.3 Co11/rol word_f<Jm111/ in BS R mode (Courtesy l ntel)

rr , ' IS 1;0 runctions, then bi ls D(i - 1)() I , , . . . . . .
_- I sckccl · ock ,.,_ ..
D1 • 1 an I11
. . ..
ds s 110\\ 11 Ill 1• ti.!. 9 ,
l i:lt:i11 1111c 1/0 lu 11cl10 11 opcrnt 10 11 11 1 1lircc ''""le':,
p11 dc ..... ·-·
1110
J' 1).
1,, 0 , are used ror simple input •rncJ O t . . •
11111" 11 J· ports b ' · I r·0 1· I/
ll put operations. No ha11dslia k111g 1~ require(
\ 1L1 (.;, • A and B can c program1ncd • , .· I · d
11~ .
11 . po1t < . els Simp c 1nput/output 8 bi t port, an port C can be
•r:111ons- . simple input/output 4 or 8 bit port.
•L
i ,'I icd as
,,,f•111111
,:

,1ode 1 port A and B can be use~ as input or output port in handshake mode, and port C is used _to
. i11l1d~ I. ccept these handshake signals. Po1t A uses three bits on port C, and port B uses three bits
.1 1• or a 01· accept I,andshake signals.
· eral
.·11t:r.1 ~C to z:,aenerate The remaininob two bits on port C are used as gen '
'. f1L1fl
• ·e 1,0.
~~
·'
1
l1 ut When po1i A and B are configured as input port, as shown in Fig. 9.4, port A uses P
cs ,
\{tidr J
-~and P '
23
and port B uses PC2 ,
/0 Th fi
PC 1 and PCO for handshake signals. The remaining PC6 and PC 7 are
.
;'l, i 'asgene ral purpose 1 • e unctions of the handshake signals are as shown in Fig. 9.5 .
.,u 8255

Port A input

INTEA
Control word-fllode 1 input
~ - STBA 0 7 06 Ds 0 4 03 D2 0 1 Do

t--- lBFA 0 1/0 1 1 X

Port B input
1/0 Mode
Port A mode 1 ~___,_. Port B mode 1

Port A input - - - ~ PC5-7

INTE9 1 = input
o = output
~ - ST89

r-------- 1BF8

RD
Port B input
PC 6_7 ~-- 1/0

Figure 9.4 8255A Mariel: Input co1Zftg11mtio11 (Courtesy Intel)

0-.

t
~TB ~S robe Input) This is an active low signal. When the buffer is not full , an input device generates
,'ftgnal.
8
The input device places the data on input p01t and then pulses the STB signal. In response to
'llie 255 generates IBF and INTR as shown in Fig. 9.5.