Dissertation On

HIGH SPEED DESIGN OF FPGA BASED GOLAY

ENCODER AND DECODER

Submitted in partial fulfillment of the requirement for the award of Degree of

Master of Technology
In
VLSI Design

Submitted to

Rajiv Gandhi Proudyogiki Vishwavidyalaya Bhopal (M. P.)

Submitted By

AMIT SHRIVASTAVA

Enrollment No.-0187EC13MT19

Under the Supervision of

Assistant Prof. Mohd. Abdullah

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.

SAGAR INSTITUTE OF SCIENCE AND TECHNOLOGY,
GANDHI NAGAR, BHOPAL (M. P.)
JANUARY 2019
 SAGAR INSTITUTE OF SCIENCE AND TECHNOLOGY
Bhopal -M.P.

Department of Electronics and Communication

CERTIFICATE

This is to certify that the work embodies in this dissertation titled ‘High Speed
Design of FPGA Based Golay Encoder and Decoder ’ being submitted by
„Amit Shrivastava Enrollment No. – 0187EC13MT19 for partial fulfillment of
the requirement for the award of „Master of Technology in VLSI Design
discipline to Rajiv Gandhi Proudyogiki Vishwavidyalaya, Bhopal(M.P.) during
the academic year 2013-15 is a record of bonafide piece of work, undertaken by
her under the supervision of the undersigned.

Supervised by

Prof. Mohd. Abdullah Department of EC

Forwarded by

Prof. Paresh Rawat Dr. Keshvendra choudhary

Head of Department Principal
Electronics and Communication SISTec, Bhopal SISTec,
Bhopal

i
 SAGAR INSTITUTE OF SCIENCE AND TECHNOLOGY
Bhopal -M.P.

Department of Electronics and Communication Engineering

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SAGAR INSTUTUTE OF SCIENCE AND TECHNOLOGY

Bhopal –M.P.

DECLARATION

I hereby declare that the work, which is being presented in this dissertation
entitled ‘High Speed Design of FPGA Based Golay Encoder and Decoder’ for
fulfillment of the requirements for the award of degree of ‘Master of
Technology in VLSI Design’ submitted in the Department of Electronics and
Communication, Sagar Institute of Science and Technology, Bhopal (M.P.), is an
authentic record of my own work carried under the guidance of Assistant Prof.
Mohd. Abdullah, I have not submitted the matter embodies in this report for the
award of any other degree.

I also declare that “A Check for Plagiarisms has been carried out on this
Dissertation and it is found within the acceptable limit and report of which is
enclosed herewith”.

Amit Shrivastava
Enrollment No.: 0187EC13MT19

Prof. Mohd. Abdullah Dr. Keshvendra choudhary

iv
Supervisor Principal
Electronics and Communication SISTec, Bhopal
SISTec, Bhopal

v
 SAGAR INSTITUTE OF SCIENCE AND TECHNOLOGY
Bhopal -M.P.

CERTIFICATE OF APPROVAL

This dissertation entitled „High Speed Design of FPGA Based Golay Encoder
and Decoder’ being submitted by „Amit Shrivastava’ Enrollment No. –
0187EC13MT19 has been examined by us and is hereby approved for the award
of „Master of Technology in VLSI Design’, for which it has been submitted. It
is understood that by this approved the undersigned do not necessarily endorse or
approve any statement made , opinion expressed or conclusion drawn there in ,
but approve the dissertation only for the purpose for which it has been submitted .

Internal Examiner External Examiner

Name: Name:

Designation: Designation:

Address: Address:

vi
 SAGAR INSTUTUTE OF SCIENCE AND TECHNOLOGY

Bhopal –M.P.

Department of Electronics and Communication Engineering

APPROVAL CERTIFICATE

VLSI DESIGN

This is to certifty that thesis/dissertation part IV of Amit Shrivastava Enrollment

No.- 0187EC13MT19 has undergone through plagiarism check and found within
prescribed limit as suggested by RGPV. The Thesis/Dissertation of the mentioned
student is approved for uploading at RGPV Portal.

Name & Signature of Guide – MD.Abdullah

Name & Signature of HOD of the Department - Dr. Paresh Rawat

Name & Signature of the Principal of the Instutute – Dr. Keshavendra

Choudhary

vii
 SAGAR INSTUTUTE OF SCIENCE AND TECHNOLOGY

Bhopal –M.P.

Department of Electronics and Communication Engineering

PLAGIARISM CERTIFICATE

I, here by declare that the work, which is being presented in this dissertation
entitled’ high speed design of fpga based golay encoder and decoder’ for
fulfillment of the requirements for the award of degree of ‘Master of Technology
in VLSI DESIGN’ submitted in the department of Electronics and
Communication, Sagar Institute of Scence and Technology, Bhopal (M.P.) is an
Authentic record of my own work carried under the Guidance of Associate Prof.
Md. Abdullah. I have not submitted the matter embodies in the report for the
award of any other degree.

I also declare that” A check for plagiarisms has been carried out on this
dissertation and it is found within the acceptable limit and report of which is
enclosed herewith”.

Name of Candidate : Amit Shrivastava Dr. Paresh Rawat

Enrollment No. – 0187EC13MT19 HOD, ECE
SISTec. Bhopal SISTec, Bhopal

Dr, Keshavendra Choudhary

Principal
SISTec, Bhopal
viii
 ACKNOWLEDGEMENT

I would like to express my deep sense of respect and gratitude towards my advisor and guide
Assistant Prof. Mohd. Abdullah, who has been guiding behind this research work. I am
greatly indebted to him for his constant encouragement, invaluable advice and for propelling
me further in every aspect of my work.
I would like to express my humble respects to Dr. Keshavaenda Choudhray (Principal,
SISTec, Bhopal), Prof .Paresh Rawat (Head of Department of E.C.E.) for extending all
possible help in carrying out the dissertation work directly or indirectly. I would like to thank
my institution and all teaching and non- teaching staff of E.C.E. for their help and guidance.
They have been great sources of inspiration to me and I thank them from the bottom of my
heart. I would like to thank all my friends and especially my classmates for all the thoughtful
and mind stimulating discussions we had, which prompted us to think beyond the obvious.
I am especially indebted to my family and their love, sacrifice, and support. Finally, I extend
my gratefulness to all those who are directly or indirectly involved in this project work.

Amit Shrivastava

Enrollment No.: 0187EC13MT19

ix
 fg

ABSTRACT

In today’s communication environment it is very important to have an error free and speedy
communication. Thus we need to have a Communication system that is able to first detect the
error and then able to correct it. As in most of the communication the media or the channel is air
which is full of distraction and many losses could occur. Thanks to digital communication
nowadays the losses and distraction occur in terms of bit error or losses of bits, which can be
detected or corrected with the help of various methods. There are numerous methods to detect
and correct the bit error but when the length of communication is very long or distance between
the transmitter and the receiver is very large these methods fail to provide a efficient result. One
More characteristics the receiver should have is the ability to provide speedy result because in
today’s era of communication where even a small lag in communication is not tolerable, we
must need a system equipped with a software that provide efficient and speedy results. In this
brief a Field Programmable Gate Array (FPGA) based design and simulation of Golay Code
(G23) and Extended Golay Code (G24) Encoding scheme are presented. Proposed methodology
is relied on the Reduction of the time delay of the circuit to encode a data packet using the
Golay Encoder, and optimize Hardware Utilization when Applying the Proposed Golay Encoder
Algorithm. Goaly encoder with the help of identity matrix encoded the data and transmits at the
receiver end. At the receiver side transmitted data with the help of transpose of identity matrix
and parity checker identify the error and if the bit error is 3 or less than three this algorithm
corrects the error.

x
 LIST OF FIGURES

Figure No. Title Page No.

Figure 1.1 Process of Error Control 4
Figure 1.2 Introduction of Error 5
Figure 1.3 Burst Error Introduction 14
Figure 1.4 Even Parity Checking 16
Figure 1.5 Two Dimension Parity Check 17
Figure 1.6 (a) Sender end of Calculation of Checksum 18
Figure 1.6 (b) Receiver End of Checking Checksum 18
Figure 1.7 Cyclic Redundancy Check Example 20
Figure 1.8 Position of Redundancy in hamming Code 21
Figure 1.9 Hamming Code Error Correction 22
Figure 3.1 Project Navigator Interface 23
Figure 3.2 Project Navigator Desktop icon 24
Figure 3.3 New Project Wizard(Create New Project Page) 25
Figure 3.4 New Project Wizard(Device Properties Page 26
Figure 3.5 New source Wizard (Select source Type Page) 26
Figure 3.6 New Source Wizard (Define module Page) 27
Figure 3.7 VHDL File in ISE Text Editor 27
Figure 3.8 Specifying Synthesis Tool 28
Figure 3.9 Create RTL Symatic Start Page 28
Figure 3.10 RTL Symatic (Example) 29
Figure 3.11 VHDL Text Bench 31
Figure 3.12 Simulation Waveform 32
Figure 4.1 Flow Chart of Proposed Methodology 34
Figure 4.2 Design Flow of the Circuit 35
Figure 4.3 Filter Bank structure of the Wavelet Encoder 36
Figure 5.1 Design Properties of Xilinx 14.5 virtex 4 Device Family 37
Figure 5.2 Hardware Utilization of Encoder 38
Figure 5.3 Modelsim Waveform of Encoder 39
Figure 5.4 RTL Diagram of Encoder 40

ix
 LIST OF TABLES

Table No. Title Page No.

Table 1.1 Possible 4 Bit Data word and corresponding Codeword 04
Table 2.1 Summary of Literature Review 16
Table 4.1 Examples of Wavelet and Golay Encoding Schemes 42
Table 4.2 Examples of Wavelet and Golay Decoding Schemes 42
Table 4.3 Specification 44

x
 LIST OF ABBREVIATIONS

CRC Cyclic Redundancy Check

APP A Posteriori Probability

BPSK binary Phase Shift Keying

MSK Minimum Shift Keying

FPGA Field Programmable Gate Array

ML Maximum Likelihood

GF Galois Field

BPTC Block Product Turbo Code

VHDL VHSIC Hardware Description Languag

VLSI Very Large Scale Integration

VHSIC Very High Speed Integrated Circuit i/p Input o/p Output

PTAR Peak to Average Ratio

HDL Hardware Descriptive Language

 INDEX

CERTIFICATE i
AFFIDAVIT ii
DECLARATION iii
PRAPATRA iv
CERTIFICATE v
APPROVAL CERTIFICATE vi
CERTIFICATE OF APPROVAL v ii
ACKNOWLEDGEMENT v iii
ABSTRACT ix
LIST OF FIGURES x
LIST OF TABLES xi
LIST OF ABBREVIATIONS x ii

CHAPTER 1 INTRODUCTION…………………………………………..16-24

Introduction……………………………………………………………………1 6
T y p e o f E r r o r … ................................................................................................................1 9
Error Detection Code………………………………………………………….21
Error Correction Code………………………………………………………..23

CHAPTER 2 LITERATURE REVIEW……………………………. 26-28

L i t e r a t u r e r e v i e w ..................................................................................................................2 6
S u m m a r y o f L i t e r a t u r e R e v i e w ......................................................................................2 6
P r o b l e m I d e n t i f i c a t i o n .......................................................................................................2 7
R e s e a r c h O b j e c t i v e .............................................................................................................2 8

CHAPTER 3 DESIGN TOOL AND PROGRAMMING

LANGUAGE………………………………………………………………….23-33
Technical Detail……………………………………………………………….23
A panel Description ………..………………………………………………..24
Selected Programming Language…………………………………………. 33

CHAPTER4 PROPOSED METHODOLOGY AND FLOW CHART35-47

P r o p o s e d M e t h o d o l o g y ........................................................................................................3 5
Encoding and Decoding Funtionality Chip………………………………..42

DesignApproach……………………………………………………………… 43
RTLDescription……………………………………………………………….43
Wavelet Encoder………………………………………………………………44
Coset Decoding……………………………………………………………… 46

C H A P T E R 5 R E S U L T S A N D D I S C U S S I O N . ....................................................5 2 -
56
S i m u l a t i o n A n d S y n t h e s i s R e s u l t ..................................................................................5 3
Encoder………………………………………………………………………….53
Decoder……………………………………………………………………,,,,,,,55
CHAPTER 6 CONCLUSION AND FUTURE WORK 58-58
C o n c l u s i o n o f E n h a n c e m e n t m e t h o d s ..........................................................................5 8
F u t u r e S c o p e ...........................................................................................................................5 8
R E F E R E N C E S .................................................................................................................6 1 - 6 3
A P P E N D I X I V H D L C O D E .......................................................................................6 4 - 6 9
A P P E N D I X I I P U B L I C A T I O N ..................................................................................7
 CHAPTER-1
INTRODUCTION
 CHAPTER-1
INTRODUCTION

Communication is important in our daily life. Communication can be done through a proper
channel by using phone, satellites and computers. Unfortunately the communication systems
are prone to the noise especially when length of the channel is more, that noise is responsible
for the error generated in the system. So for better communication system we need to have a
system which reduces the occurrence of error in the system. That’s why Coding system is
introduced. The basic idea behind the coding is to make sure the message sent is same as the
massage received. The error detecting codes is useful is identifying the error if present and
error correcting codes is to remove those errors. We introduce redundancy bits in the
transmitted signal that is useful in indentify the error and correct them. Redundancy bits have
special pattern that they follow the same pattern must occur at the receiver end. This paper
presents error-correcting codes, Golay code G23 and the extended Golay code G24. The
extended Golay code was used for NASA for different satellite communication. There are three
steps first the source sends the data channel transmits it and receive the data. There is
possibility of occurrence of error in the channel that’s why we use error correcting codes at the
receiver end. Figure 1 show that a message is encoded into a codeword, it is sent to the receiver
through a channel, in this channel the possibility exists that errors occur, and the receiver tries
to obtain the original message by decoding the word.

Encoding Sending Decoding

Message Codeword Received Message

Information
Figure. 1.1 Process of Error Correction Code

1.1 Types of error

If the signal is analog signal noise can change the timing and shape of the signal but if the
signal is binary signal noise can alter the meaning of the data represented by the signal. These
errors can be divided into two types: Single-bit error and Burst error.

15
Single-bit Error- The term single-bit error means that only one bit of given data unit (such as
a byte, character, or data unit) is changed from 1 to 0 or from 0 to 1 as shown in Figure

0 1 0 1 1 1 0
Sent data
(error)

0 1 1 1 1 1 0
Receive data
Figure 1.2 Introduction of Error
Single bit errors occur very rarely in serial data transmission. Suppose a sender sends data at 20
Mbps that means each bit lasts only for 0.05 microseconds. That’s why for a single bit error
noise should occur in this duration only that is very rare. However, in parallel data transmission
a single-bit error can occur.

Burst error- The burst error means the error in two or more no of bits but it does not mean
that error occur in consecutive no of bits. it may or may not occur at consecutive no of bits.
The length of the burst error is measured from the first corrupted bit to the last corrupted bit.
Some bits in between may not be corrupted.

0 0 1 1 1 0 1
Sent data

0 1 0 1 1 1 0
Receive data
Figure 1.3 Burst Error Introductions

As the duration of the noise is likely to happen in more no bits or duration of noise is more
then the duration of single bits which effects the set of bits and the no of bits effected is depend
upon the data rate and duration of noise. it affects a set of bits as shown in Figure 1.3

16
 1.2 Error detecting codes

The basic idea behind error detection codes is to add redundancy bits to the data bits which
have certain parity model which needs to be check at the receiver end for error detection and
then error correction. Types of error detection techniques are as follows
 Simple Parity check
 Two-dimensional Parity check
 Checksum
 Cyclic redundancy check

1.2.1 Simple Parity Checking or One-dimension Parity Check

The very common and less costly technique for error detection is the simple parity check. In
this methods redundancy bits called parity bits is added to data bits redundancy bits is the no of
bits which maintain the even no of bits in the data .the source data is divided in to blocks and
this blocks of data is subjected to parity bit generator form.1 is added to the block if block
contain odd no of one ,and 0 is added if block contain even no of 1. Now receiver is calculated
the parity bit and compare from the received parity bit. This method is called even parity
checking since it make total no of 1 Even. It is also possible to have odd parity checking where
no of 1 in the block should be odd. Considering a 4-bit word, different combinations of the data
words and the corresponding code words are given in Table

Figure 1.4 even parity checking

Table 1.1 (possible 4 bit data word and corresponding code words)
Decimal value Data Block Parity bit Code word
0 0000 0 00000
17
 1 0001 1 00011
2 0010 1 00101
3 0011 0 00110
4 0100 1 01001
5 0101 0 01010
6 0110 0 01100
7 0111 1 01111
8 1000 1 10001
9 1001 0 10010
10 1010 0 10100
11 1011 1 10111
12 1100 0 11000
13 1101 1 11011
14 1110 1 11101
15 1111 0 11110

Performance
In this method of error detection every set of code word should have a minimum hamming
distance of 2 as showed in the table. It means receiver that has the knowledge of code word set
can detect single bit error in the code word but if two error occur in the code word it becomes
another valid cade and cannot detect the error thus error of more than one bit cannot be
detected if error is in even no of bits and can be detected if error is in odd no of bits.

1.2.2 Two-dimension Parity Check

Performance of single bit parity check can be improved by using two-dimensional parity
check, in this data is organized in the form of table and one parity check bits are calculated in
Row and Column wise and these two parity checks bits sent along with the data. At the
receiving end these check bits compared with Parity bits calculated on the received data. This
is illustrated in Figure

18
 Figuer 1.5 (two dimension parity check)

Performance
Two- Dimension Parity Check method is useful in detecting burst errors. N bit 2-D parity
checking is useful to detect n bit burst error as we have shown in Figure 3.2.4. A burst error of
more than n bits is also detected by 2-D Parity check. But if two bits in one data unit are
damaged and two bits in exactly same position in another data unit are also damaged, the 2-D
Parity check checker will not detect an error. For example, if two data units: 11001100 and
10101100. If first and second from last bits in each of them is changed, making the data units
as 01001110 and 00101110, the error cannot be detected by 2-D Parity check

1.2.3 Checksum

In checksum scheme the data is first divided into l segments each of n bits. In the transmitter
side the segments are added using 1’s complement method and then complemented to get the
checksum. The checksum segment is sent along with the data segments as shown in Figure
3.2.5 (a). At the receiver side all received segments are added using 1’s complement method to
get the sum. The sum is complemented. If the result is zero, the received data is accepted;
otherwise discarded, as shown in Figure 3.2.5 (b).
Performance
The checksum detects all error which involves even or odd no of bits.

19
 Figure1.6(a) sender end of calculation of checksum Figure1.6(b) receiver end of checking checksum

1.2.4 Cyclic Redundancy Checks (CRC)

Cyclic Redundancy Check is based upon the binary division method. In CRC cyclic
redundancy check bits are appended to the end of the data so that the resulting data unity is
exactly divisible by the predefined binary number.CRC is the most powerful and easy to
implement technique. At the receiver end, the received data is divided by the same predefined
binary no and if the reminder is to be zero received data to be accepted if reminder is not zero
the incoming data is to be discarded. The generalized technique can be explained as follows.

For a k bit message to be transmitted r bit frame check sequence generated by first appending r
zeroes to the message and the divide it by the predetermine no(which is r+1 length)
predetermine no is also called Generator polynomial reminder of this division process is FCS
of r bit. this r bit is append at the end of original message and this k+r bit is transmitted. On
receiver side received k+r data is divided by the same predefined no and if there is no reminder
means no error has occurred. Operations at both the sender and receiver end are shown in
Figure 1.7

20
 Figure1.7 ( cyclic redundancy check example)

Performance

CRC is a very effective error detection technique. If the divisor is chosen according to the
previously mentioned rules, its performance can be summarized as follows:
 CRC can detect all single-bit errors
 CRC can detect all double-bit errors (three 1’s)
 CRC can detect any odd number of errors (X+1)
 CRC can detect all burst errors of less than the degree of the polynomial.
 CRC detects most of the larger burst errors with a high probability.
 For example CRC-12 detects 99.97% of errors with a length 12 or more.

1.3 Error Correcting Codes

The error detection techniques can detect the error but cannot correct them we need to have
techniques which can correct the error which can be done in two ways.
One technique is when error is detected receiver can inform the sender that error is occurred
and requests the receiver to send the data again. This process is known as backward error
correction. In the other technique receiver uses the error correction technique to correct the
received data this is known as forward error correction
In paper it is possible to correct any number of error but practically it is limited to one two or at
most three bit error because error correction code require more no of redundant bits then error
detection code require so the no of redundant bits require for burst error is so high that it is
inefficient to use these correction methods.
1.3.1 Single-bit error correction

The simplest form of error correction is single bit error correction. Single bit error can be
detected by adding a parity bit with the data but by doing this we can only detect error we
cannot correct the error for which we need to know the position of the error. For this have to
add some additional redundant bits.To know the no of redundant bits there is a relationship
between r and d d+r is the total no bit transmitted so r must be able to indicate d+r+1 different
values one of these values indicate no error and remaining d+r values indicate the position of
the error. So, d+r+1 state must be distinguishable by r bits, and r bits can indicate 2r states.
21
Hence, 2r must be greater than d+r+1.
2r >= d+r+1
In the fig given below we discuss how we use these bits to find out which bit is in error. A
technique developed by R.W.Hamming provides a practical solution. The solution or coding
scheme he developed is commonly known as Hamming Code. Hamming code can be applied
to data units of any length and uses the relationship between the data bits and redundant bits as
discussed

Figure1.8 Positions of Redundancy in Hamming Code

Figure 1.9 Hamming Code Error Correction

1.3.2 Golay code

Golay code is an linear error correcting code. Golay code is very efficient and fast method
which is used to detect at most 7 bit of error and correct at most three bit of error. Golay code

22
can be represented by[23,12,7] where 23 is the total no bit 12 bit of message and 7 bit distance
between the respective golay code. Golay code can be converted to extended golay code by
adding a parity bit in the LSB of golay code makes it to [24,12,7].
Let us see how to generate golay code. First we have generator matrix which is G=[I12/B].
Where I12 is the 12*12 identity matrix and B is 12*12 matrix which is shown below.

Binary matrix generated from the generator polynomial is called extended Golay code. There
are some special properties of golay code are as follows.
1. G24 is a self dual code
2. Weight of every code word in G24 is a multiple of 4
3. The minimum distance in G24 is 8
4. Extended golay code is exactly 3 bit error detection code
The goaly is very usefull in communication nowadays specially in settellite communication.
USA nasa using goaly code for there settelite mission.

23
 CHAPTER-2
LITERATURE
REVIEWAND
PROBLEM
IDENTIFICATION
 CHAPTER-2
LITERATURE REVIEW AND PROBLEM
IDENTIFICATION

2.1 Literature Review

The Reference 1 details about the CRC based encoding scheme. CRC means cyclic
redundancy check which is simple and efficient method of encoding in FPGA for both Golay
code and extended golay code. This brief is for high speed and low latency architecture
implemented in vertex 4 without linear feedback shift register. This paper also presents
maximum likelihood decoding scheme with low latency and less area occupation. The
Encoder operated on frequency 238.575 Mhz and decoder runs at 195.028Mhz.
Reference 2 is about The 4 bit Galois Encoder and Decoder in FPGA. Here paper proposed
the Galois field which deals with the binary numbers and having properties like mathematical
field and are of finite scope. Galois operation perform Addition (Ex-or) and multiplication and
sometimes logarithmic operation for checking multiplication result. Galois multiplier used for
cryptography and coding.
Reference 3 is about Algorithm and hardware The purpose of this paper is to present a soft
decoding algorithm orienting to hardware implementation for the (24,12, 8) Golay code, and
implement such an algorithm in Field Programming Gates Array (FPGA). The soft decoding
algorithm devised by Lin’s et al. for the (24, 12, 8) is not suitable for hardware
implementation because of involving many arithmetic operations, such as multiplications and
divisions. To remove the complexity arithmetic operations, the absolute value of the channel
information instead of the bit-error probability is employed to indicate the channel confidence.
Moreover, the architecture developed for realizing the proposed algorithm is verified in a
FPGA prototype. The BER performance obtained by the proposed decoding algorithm equals
to the one obtained by Lin’s algorithm. At the same time, 25% of additions, 100% of
multiplications, and 100% of exponents are reduced for computing the channel confidence. In
addition, 1-db coding gain can be obtained by Lin's algorithm at the cost of the double of
hardware complexity compared to Elia's algorithm..
25
Reference 4 Talks about golay code use in the medical field. In the medical field the clinical
data have large amount of data having information about the patients. this data is about patient
medical condition there drugs and drugs side effects. This data is very large and complex. A
effective tool is required to cluster the data and analyze it for proper use of it. This paper uses
error correcting golay code for clustering the data. It is better than all other conventional
technique because this method has linear time complexity and does not impose predefine
cluster labels. This method uses the process of predicting patterns.
Reference 5 proposes algorithm for extended golay code for soft decoder for error up to 4
errors. this algorithm is performed in FPGA. Lin’s soft algorithm is not useful in hardware
implementation because it involves many multiplication and division. this algorithm improves
the complexity of arithmetic’s uses absolute value of channel information’s instead of taking
BER.
Reference 6 is about designing and implementation of galois encoder and decoder on FPGA.
This paper presents the theory of galois field that deals with numbers that are binary in nature.
By using galois fields we can perform all mathematical operations and also includes ex-or
additions. we can use galois field multiplications in coding theory and cryptography.
Reference 7 discusses about decoding mechanism of a BPTC (block product turbo code). This
study first uses hamming block channel code to construct a BPSK modulation and BPTC
coding. They are using turbo feedback structure. This study also uses a combination of MSK
modulation with golay channel code. Simulation of this method indicates that MSK golay is
less robust than BPSK golay. This study can be useful in wireless communication.
Reference 8 is the paper talks about the searching techniques improvement using golay code.
This introduces a new technique for hash searching which is design for approximate matching
problem of the multi attribute objects which enhance the performance of searching specially
when search criteria is not specified . This technique reverses the conventional scheme og
golay code maps 24 bit vector in to 12 bit vector.
Reference 9 talks about the quadratic residue codes and its decoding. this is done by one to
one mapping between syndrome and error pattern. This method identified the error location
by lookup tables without multiplication over a finite field. Shift search algorithm is used to
reduce the memory requirement for decoding.

26
Reference 10 talks about Doppler resilient golay complimentary wave forms.it are a sequence
of phase coded wave forms.

Reference 11 is about construction of binary Golay code using two array golay code using
direct sum operation.

27
2.2 Problem Identification

The existing designs are a guide line for the proposed work to be carried out in the direction of
following design problems and issues:

1. Design and Synthesis of high speed VLSI based Golay code encoder
2. Design and Synthesis of high speed VLSI based Extended Golay code encoder
3. Design and Synthesis of high speed VLSI based Extended Golay code decoder
The Golay code decoder is one among the perfect decoder that can correct up to 3-bit of error
from the data symbol. Design of such codec with low power architecture is a good design
option to effectively implement in high speed circuits.
In previous work there have been designs with encoder using CRC (with shift and OR method)
And then generating check bits this method takes more clock cycle and less maximum
frequency can be used. LUT utilization is also less. This is one problem that is indentified.
In our proposed work we are utilizing the properties of generator matrix to reduce the no of
logic operations. So decreases the no of clock cycle, maximum frequency used increases LUT
and slices utilization increases.
In previous work there was no provision of introducing error so it is problematic to introduce
error and confirms the result obtain is right. In this proposed work we introduce the provision
12of introducing error and make more convenient to check the result authenticity.

2.3 Research Objective

The main objective of the work is to obtain Two product array codes are used to construct the
(24, 12, 8) binary Golay code through the direct sum operation. This construction provides a
systematic way to find proper (8, 4, 4) linear block component codes for generating the Golay
code, and it generates and extends previously existing methods that use a similar construction
framework. The code constructed is simple to decode.
Objective of research is to make an efficient high speed golay encoder and decoder which can
identify and correct the bit error up to 3 bit. From previous work we modified the algorithm to
increase speed and increase the hardware utilization.
Extended Golay Code is also known as Golay code (24, 12, 8), where we have codeword’s of
length 24 bits describing the original 12-bit message. The minimum Hamming distance
18
between any two codeword’s is 8.
The 24 Golay code is an extension of the 23 Golay code. Golay code (24, 12, 8) guarantees
retrieving the original data if the error occurred is three bits or less
[4, 8]. If errors occurred in four bits there is no guarantee to recover the original data, however,
it is possible, due to the fact that the decoding may result in having the original words relate to
a group or another with, perhaps, the same probability. This will benefit the approximate
matching and similarity measures to study a new approach to the matching problem of multi-
attribute objects. In addition, we will study the possibility of near matching by changing one bit
at a time of all the 24 bits and see the effect of this. This technique can be used to improve
Information Retrieval when the multi-attribute objects are partially distorted or when the
searching criterion is not specified properly.

19
 CHAPTER-3
DESIGN TOOL
AND
\

PROGRAMMING
LANGUAGE
 CHAPTER 3
DESIGN TOOL AND PROGRAMMING
LANGUAGE

3.1. TECHINICAL DETAIL

In this section a detail description is given on design tool and programming

language.
DESIGN TOOL

The design tool used in this work is Xilinx ISE 14.7, ISim.

PROGRAMMING LANGUAGE

The programming language on which the proposed work is implemented is –

VHDL

DESIGN TOOL DESCRIPTION

Xilinx ISE 14.7, ISim

21
 Figure.3.1Project Navigator interface (refer from Xilinx data sheet)
The proposed work is implemented on the ISE Design Suite that controls all aspects of the
design flow and this thesis uses 14.7 versions. Figure 8 shows the Project Navigator
interface, this gives the detail that how all the design entry and design implementation tools
can be access. The files and documents associated with the proposed work are also access.
3.2 A PANEL DESCRIPTION
Design Panel
The Design panel provides right to use the Hierarchy, View, and Processes panels

View Panel
The View panel is a radio buttons that allow you to examination the basis modules
associated with the Implementation or Simulation Design that can be view in the Hierarchy
panel.
Hierarchy Panel
Files related to a particular design view like target device, user documents, project name,
and design source files can be displayed through a Hierarchy panel.

22
B WORKSPACE
The Workspace is the area where all the details related to the ISE Text Editor,
Design Summary/Report Viewer, Constraint Editor, RTL and Technology Viewers,
Schematic Editor, and Timing Analyzer can be viewed.
C THE ISE PROJECT FILE
.xise extension is used to open the ISE project file and that is an XML file that
restores all main work data for the project as follows:
• Information related to the ISE version of design suite
• Information related to the file containing the project
The ISE project file includes the following uniqueness, which are well-matched
with
Environments control source: environment
• All essential source settings and input data for the project.
• The updating or modification is only done when a source-level change is done in
the project.
• Read-only is the only state of the Project Navigator
• Can be kept in a directory separate from the generated output directory (working
directory).

SELECTED PROGRAMMING TOOLS (VHDL)

To work on this thesis VHDL language is used as a software tool.
A Starting the ISE Design Suite
To start the ISE Design Suite, double-click the Project Navigator icon on your
desktop, or select shown in the figure 9:
1) Start
2) All Programs
3) Xilinx ISE Design Suite
4) Xilinx Design Suite 14
5) ISE
6) Design Tools
7) Project Navigator.

23
 Figure 3.2 Project Navigator Desktop Icon
3.3 Creating a New Project
To create a new project using the New Project Wizard, following steps taken in to
account:
1. Start with Project Navigator, select File > New Project.
The New Project Wizard appears on the screen.
2. Select the project from the location field or from the directory where the project is
installed the project.
3. In the Name field, enter IVM_vhd.
4. Select HDL for the Top-Level Source and click Next.

Figure3.3 New Project Wizard—Create New Project Page

The New Project Wizard—Device Properties page appears

24
 Figure 3.4 New Project Wizard—Device Properties Page
5. Device Properties page is shown by figure 11 in this figure we have to select the
following details.
• Product Category: All
• Device: XC3S700A
• Package: FG484
• Family: Spartan3A
• Speed: -4
• Synthesis Tool: XST (VHDL)
• Simulator: ISim (VHDL)
• Preferred Language: VHDL for this work.
6. Click next, and then finish completing the project creation.

Creating an HDL-Based Module

ISE design suite create module with a preferred language HDL correlated .de by
performing this a new source wizard and ISE text editor is opened. And create a file
using the New Source wizard; name the program as the requirement and ports of the
component. Consequential HDL file is then modified in the ISE Text Editor.
Source file can be created by performing the following steps and shoen by figure 12
and 13 :
1. Select Project > New Source.

25
2. In the Select Source Type page, select VHDL Module.
3. In the File Name field, enter denounce.
4. Click Next.
5. In Next Module page, enter _in and clk as two input ports and output port as
sig_out for the debounce component as follows:
a. Enter sig_in, clk and sig_out to first three port.
b. Input for sig_in and clk and to output for sig_out is set for direction field.
sc. Click Bus designation boxes unchecked.
6. Click Next to scrutiny a description of the module.
7. Click Finish to open the empty HDL file in the ISE Text Editor.

Figure 3.5. New Source Wizard—Select Source Type Page

26
 Figure 3.6. New Source Wizard—Define Module Page
 After a new source wizard open a ISE text editor file is open by enter some
of the details .and also called VHDL file.

27
 Figure3.7. VHDL File in ISE Text Editor
Synthesizing the Design

To Synthesis the design following steps performed with the help of synthesis tool to
create the net list:
• Analyze/Check Syntax
Check the syntax of the source code.
• Compile
28
Translates and optimizes the HDL code into the language so that a set of
components can recognize the synthesis tool.
Map
During the design flow the design can be change at any time. The following steps
performed to change the synthesis tool:
1. Select the targeted part.
2. Select Design Properties.
3. In the Design Properties dialog box, select the Synthesis Tool shown by figure
15.Selects the desired synthesis tool from the list.

Figure 3.8. Specifying Synthesis Tool

Synthesizing the Design Using XST

Steps for synthesis using XST are as follows:

View RTL Schematic and simulation waveform

The step generates a schematic view of your RTL net list.

29
 Figure 3.9. Create RTL Schematic Start Page
View Technology Schematic
This step generates a schematic view of your technology net list.
Check Syntax
Check the syntax to verify the HDL code.
Generate Post-Synthesis Simulation Model
This step creates HDL simulation models based on the synthesis net list.
30
 Figure 3.10. RTL Schematic (example)
VHDL Simulation
To simulate the work proposed first add the tutorial VHDL test bench to the project,
to perform this go with the steps given below:
1. Select Project > Add Source in the project navigator.
2. Select the test bench file stopwatech_tb.vhd.
3. Click Open.
4. Make sure that Simulation is selected for the file.
5. Click OK.
Figure 18 shows the VHDL test bench window to understand how it will work. And
figure 19 shows the example of simulation waveform.

Figure 3.11. VHDL Test Bench

31
Figure 3.12. Simulation Waveform (example)

32
 CHAPTER-4
PROPOSED
METHODOLOGY
AND FLOW
CHART
 CHAPTER-4
PROPOSED METHODOLOGY AND FLOW CHART

4.1Proposed Methodology
The steps and the methodology that would be used to perform the proposed work are shown in
the block flow chart
Study Architecture of Golay Code Encoder and
Decoder

Enter the VHDL code of the design using “Xilinx

ISE Tool”

Perform simulation of the design for functional

verification of the proposed design using
“Xilinx ISIM Tool”

Perform Synthesis on FPGA for Hardware

Utilization and Operational Delay

Comparative Analysis of the design for speed

performance

Represent the observed simulation results using

Table

23
 Figure 4.1: Flow Chart of the proposed Methodology

Extended (24, 12) Binary Golay Code: Encoding and Decoding Procedures

The extended (24, 12) binary Golay code [1] considered in this submission can correct three or
fewer errors. Due to the 11 x 11 matrix  Bc, having a cyclic structure and being a component of
both the generator and the parity check matrices of this code, its decoding procedure is very
simple 

Generator and Parity Check Matrices of (24, 12) Golay Code 

    Let 

be the 11 x 11 matrix over GF(2), where 

 

 , 

b2 is obtained from b1 by shifting cyclically the sequence b1 one position to the left ,the third
row of Bc is obtained from the second in the same way, and so on. Thus
24
 

The (24, 12) Golay code has the following generator and parity check matrices,
correspondingly: 
 

,    ,  

where I - identity matrix 12 x 12,  

 

and  
 

.  
25
Therefore 
 

26
  

It can be seen that BT=B, BBT =I, B2 =I  

Encoding and Decoding of (24, 12) Golay Code 

As in the case of any linear code, to generate a code vector it suffices to multiply the vector i,
containing 12 information symbols   
27
 i = [i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12] 

by the G matrix:  

v=iG 
wherefrom 
 

v=[i1+i2+i3+i4+i5+i6+i10+i12,i1+i3+i4+i9+i11+i12,i2+i3+i4+i8+i10+i11+i12,i1+i2+i3+i7+i9
+i10+i11+i12,i1+i2+i6+i8+i9+i11+i12,i1+i5+i7+i8+i10+i11+i12,i4+i6+i7+i9+i10+i11+i12,i3
+i5+i6+i8+i9+i10+i12,i2+i4+i5+i7+i8+i9+i12,i1+i3+i4+i6+i7+i8+i12,i2+i3+i5+i6+i7+i11+i12
,i1+i2+i3+i4+i5+i6+i7+i8+i9+i10+i11,i1,i2,i3,i4,i5,i6,i7,i8,i9+i10+i11+i12]

  The decoding algorithm of the extended Golay code, shown below, consists in determining the
error pattern u=v+w, where w denotes the vector received and v  the nearest to w code vector.
In the content of the algorithm  wt(x)  denotes the weight of the vector x, (i.e. the number of
"ones" contained in x), bi -  i-th row of the matrix B,ei- the word of length 12   with 1 in the i-
th  position  and 0 elsewhere. After determining u we assume that the corrected received vector
will be v=w+u.  Here are the steps of the algorithm [1]: 

Step 1. Compute the syndrome s=wH ^T

Step 2. If wt(s)<=3 u = [s, 000000000000]. 

Step 3. If wt(s+bi)<=2 for some bi of B   then u = [s+bi,ei]. 

Step 4. Compute the second syndrome sB 

Step 5. If  wt(sB)<=3 then u = [000000000000, sB]. 

Step 6. If wt(sB+bi)<=2 for some bi of B    then u = [ei,sB+bi]. 

Step 7. If u is not yet determined then request retransmission. 

ENCODING/DECODING FUNCTIONALITY OF THE CHIP

28
 Table I presents examples of wavelet and wavelet-based golay encoding schemes [1], in which
we put a comma after every 4 digits to enhance readability. The decoding of wavelet and golay
codes with one bit error and three bit errors, respectively, have been shown in Table II.

TABLE 4.1 Examples of wavelet and golay encoding schemes

Message Code
Wavelet 00,0001 0100,1101,0011

Golay code 0000,0000,0001 1010,0011,0011,1100,0001,0011

TABLE 4.2 Examples of wavelet and golay decoding schemes with bit errors

Code Message
Wavelet 0100,1100,0011 00,0001

Golay code 1010,0011,0111,0101,0001,0011 0000,0000,0001

The design achieves the encoding/decoding functionality in combinational logic. It has been
found that all blocks, except the golay decoder, can be simplified to a single stage
combinational logic block. This simplification has helped us achieve higher clock speeds of
approximately 150 MHz and data transfer rates of the order of 900 Megabit/sec using a 0.25
µm CMOS library provided by Artisan, Inc. [2].
DESIGN APPROACH
The design has been achieved using a typical design flow for designing an Integrated Circuit (IC).
Figure 1 illustrates this design flow and the tools that have been used to implement the various steps.
The following subsections present more details of each of these steps.

29
 Figure 4.2

TABLE 4.3 Specifications

30
 Input/output Input size (bits) Output size (bits)
Register Transfer
Wavelet 6 12
Level (RTL) description
encoder
using Verilog
Wavelet 12 6
decoder
The RTL description of
Golay 12 24
the circuit has been done
encoder
using Verilog and the
corresponding Golay 24 12 data flow is
shown in decoder Figure 2. The
design is fully synchronous and positive edge triggered.The core of the design consists of four
modules – wavelet encoder, wavelet decoder, golay encoder and golay decoder. The
input/output specifications of the four modules are shown in Table III. The first three modules,
i.e., wavelet encoder, wavelet decoder and golay encoder are single stage combinational blocks
and take one cycle to compute the output. The last module, the golay decoder, is a multi-stage
combinational block and takes 12 cycles to compute its output.

The total number of inputs and outputs in Figure 2 is 26. The number of data input bits (six)
and output bits (twelve) is chosen to optimize the wavelet encoder case; another motivation in
choosing only 26 inputs and outputs is to keep packing costs low.

Wavelet encoder
The four encoder and decoder modules shown as shaded blocks in Figure 2 are implemented
based on the algorithm structure explained in [9]. Since this report focuses on the hardware
implementation of the four encoders and decoders, the detailed algorithmic derivations are not
fully described. Interested readers may refer to [9] for an in-depth explanation of the algorithms
used.

Figure 4.3 Filter bank structure of the wavelet encoder

Figure shows the encoder of an (N, M, d) wavelet code that maps the message block m(n)
of size M = N/2 to the codeword c(n) where n indicates the nth sequence (0 < n < N-1). ‘d’ is
the hamming distance. The wavelet encoder uses (N=12, M=6, d=4). In Figure 3, x0(n) and
x1(n) are wavelet coefficients. The synthesis filters go(n) and g1(n) are the scaling sequence
31
and mother wavelet, respectively. In [9], the relationship and values for the wavelet encoder
of synthesis filters are given as follows.
go((n)) = g1((-n-1))N (1)
go(n) = {10101001001}, g1(n) = {100010010101} (2)
where ((⋅))N denotes a modulo-N operation. The filter bank structure of the wavelet encoder
shown in Figure 3 is expressed as follows:
c(n) =(Goxo)(n) + (G1x1)(n), (3)
in which G0 and G1 are 2-circulant matrices (in an n-circulant matrix, each row is identical
to the previous row but n-position shifted and wrapped around). The up sampling of periodic
signals by a factor two followed by a filtering operation can be represented by the algebra of
2-circulant matrices. The 2-circulant matrix Gj can be derived from following equations.

Gj=HjT (4)

gj(0) gj(1) gj(2) ………….gj(N-1)

Hj = gj(N-2) gj(N-1) gj(0)……………gj(N-3) j=0,1 (5)

gj(2) gj(3) gj(4)…………….gj(1)

In Equation 3, x1(n) is αZ-I ⋅ m(n) (i.e., αZ-I⋅ x0(n)), in which the product of the parameter
αand the delay z-l can be expressed as Π . Π is a one-circulant matrix, in which each element of
the first row is zero except for the (I+1) position. The delay l can be chosen any value from the
set {1, 2, 4, 5} to satisfy the required hamming distance of four. It may be noted that codes
generated by different choices of I are all equivalent. We use I+5 for the wavelet encoder and
decoder. As a result, Equation 3 can be expressed as follows. c(n) = (G0+G1 Π )(x0(n)) (6)
Because we use one-bit operation, operation a + b is equivalent to a XOR b (i.e., a ⊕ b).
Finally, the codeword c(n) is expressed with message block m(n) as in Equation 7.

c(0) = m(0) ⊕ m(3) ⊕ m(4)

c(1) = m(0) ⊕ m(2) ⊕ m(3)
c(2) = m(1) ⊕ m(4) ⊕ m(5)
c(3) = m(1) ⊕ m(3) ⊕ m(4)
c(4) = m(0) ⊕ m(2) ⊕ m(5)
c(5) = m(2) ⊕ m(4) ⊕ m(5)
c(6) = m(0) ⊕ m(1) ⊕ m(3)
c(7) = m(0) ⊕ m(3) ⊕ m(5)
c(8) = m(1) ⊕ m(2) ⊕ m(4)
c(9) = m(0) ⊕ m(1) ⊕ m(4)
c(10) = m(2) ⊕ m(3) ⊕ m(5)
c(11) = m(1) ⊕ m(2) ⊕ m(5)

32
2.4 Coset Decoding

To apply MLD decoding, what we must do, given a received word w, is search through all the
codewords to find the codeword c closest to w. This can be a slow and tedious process. There
are more efficient methods, assuming the code is built in a manner similar to that of the
Hamming code. We will assume that we have a code C of length n such that there is an m × n
matrix H with C = {v 2 Zn2 : Hv = 0}. We will fix the symbols C and H in this
section.Definition 2.1. Let w be a word. Then the coset C + w of w is the set {c + w : c 2
C}.We point out two facts about C. First, by the definition of C, the zero vector 0 is an element
of the code, since H0 = 0. From this we see that w 2 C + w, since w = 0 + w. Second, if u, v 2
C, then we have u + v 2 C, since H(u + v) = Hu + Hv = 0 + 0 = 0; we are using Hu = Hv = 0
since u, v 2 C. Therefore, u + v 2 C since H(u + v) = 0. We now see an important property of
cosets: we claim that two cosets are either equal or are disjoint. To do this we show that they
are equivalence classes for an appropriate equivalence relation. To define this relation, we say
that two words x and y are related if x + y 2 C. We write x _ y when this occurs. To see that
this is an equivalence relation, we must verify the three properties. To show reflexivity, we
have x _ x since x + x = 0, which is an element of C. Next, suppose that x _ y. We must show
that y _ x. The assumption that x _ y means x + y 2 C. However, x + y = y + x; therefore, since
y + x 2 C, we have y _ x. Finally, to see transitivity, suppose that x _ y and y _ z. Then x + y 2
C and y + z 2 C. If we add these codewords, we will get a codeword, by the previous
paragraph.However, (x + y) + (y + z) = x + (y + y) + z = x + 0 + z = x + z, by the properties of
vector addition. since the result x+z is an element of C, we have x _ z, as desired. So, we have
an equivalence relation. The equivalence class of a word x is {y : y _ x} = {y : x + y 2 C} =
{y : y = c + x for some c 2 C}= C + x. The third equality follows since if x + y = c, then y = c +
x.
Proposition 2.2. If x and y are words, then C + x = C + y if and only if Hx = Hy. Proof.
Suppose first that C + x = C + y. Then x _ y, so x + y 2 C. By definition of C, we have H(x + y)
= 0. Expanding the left hand side, we get Hx + Hy = 0, so Hx = Hy. Conversely, suppose that
Hx = Hy. Then Hx + Hy = 0, or H(x + y) = 0. This last equation says x + y 2 C, and so x _ y.
From this relation between x and y, we obtain C +x = C +y, since these are the equivalence
classes of x and y, and these classes are equalsince x and y are related.

33
Example 2.3. Let

H= 1111
1100

.
A short calculation shows that C = {0000, 1100, 0011, 1111}. The cosets of C are then seen
to be
C + 0000 = {0000, 1100, 0011, 1111} ,
C + 1000 = {1000, 0100, 1011, 0111} ,
C + 0010 = {0010, 1110, 0001, 1101} ,
C + 1010 = {1010, 0110, 1001, 0101} .

We also point out that C = C + 0000 = C + 1100 = C + 0011 = C + 1111; in other words, C = C
+ v for any v 2 C. Each coset in this example is equal to the coset of fourvectors, namely the
four vectors in the coset. For some coding theory terminology, we call Hx the syndrome of x.
We can make use of syndromes to more quickly decode. Suppose that a word w is received. If
c is the closest codeword to w, let e = c + w. Then e is the error word, in that e has a digit equal
to 1 exactly when that digit was transmitted incorrectly in c. Note that e is the word of smallest
possible weight of the form v + w with v 2 C since wt(e) = D(c,w). If we can determine e, then
we can determine c by c = e + w. To see how to do this, if we take the equation
e = c + w and multiply both sides by H, we get
He = H(c + w) = Hc + Hw = 0 + Hw
= Hw.
We then can compute He by computing Hw. The proposition says that C + e = C + w; in other
words, e 2 C + w. Since c is the closest codeword to w, the word e is then the word of least
weight in the coset C + w. We then find e by searching the words in C + w and finding the
word of least weight; such an element is called a coset leader. To do decoding with cosets, we
compute, for each coset, the coset leader.
Example 2.4. Let

34
 H= 11000
10110
10101

Then C = {00000, 11100, 00111, 11011}. We see that the distance of C is 3, so C is 1-error 2.5.
The Golay Code correcting. The cosets of C are

{00000, 00111, 11011, 11100},

{01110, 10010, 01001, 10101},
{00010, 00101, 11001, 11110},
{11111, 11000, 00011, 00100},
{01111, 01000, 10100, 10011},
{01101, 10110, 01010, 10001},
{01100, 10000, 10111, 01011},
{11010, 00001, 11101, 00110}.

By searching through each of the eight cosets, we can then build the following syndrome table:

Syndrome Coset Leader

000 00000
101 10010
010 00010
011 00100
100 01000
110 01010
111 10000
001 00001

To see how we use the syndrome table to decode, we give an example. Suppose that w = 10010
is received. If we calculate Hw, we get 101. First of all, since Hw 6= 0, the vector w is not a
codeword. By looking at the syndrome table, 101 is the second syndrome listed. The
corresponding coset leader is e = 10010. We then decode w as c = w + e = 00000. Similarly, if
we receive the word w = 11111, we calculate Hw = 011. The corresponding coset leader is e =
00100, so the correct codeword is e+w = 11011. Using the syndrome table required much less
computation than checking the distance between w and all 16 codewords to find that the closest
codeword is 00000.

The Golay Code

In this section we discuss an example of a code which is called the extended Golay code. This
code is the set of solutions to the matrix equation Hx = 0, where H is the 12 × 24 matrix iv
whose left half is the 12 × 12 identity matrix and whose right half is

35
 110111000101
101110001011
011100010111
111000101101
110001011011
B= 100010110111
000101101111
001011011101
010110111001
101101110001
011011100011
11 1 1 1 1 1 1 1 1 1 1 0

.
This length 24 code was used by the Voyager spacecraft to photograph Jupiter and Saturn
between 1979 and 1981. The photographs were made using 4096 colors. Each color was
encoded with a codeword from the Golay code. By solving the matrix equation Hx = 0, we can
see that there are indeed 4096 codewords. Furthermore, a tedious check of all codewords shows
that the distance of the Golay code is d = 8. Thus, the code can correct b(8 − 1)/3c = 3 errors.
Thus, up to three out of the 24 digits of a codeword can be corrupted and still the original
information will be retrievable. Because this code can correct more than 1 error, any decoding
procedure is bound to be more complicated than that for the Hamming code. We give here a
decoding procedure. It is based on some simple facts about the matrix B. Its validity is left to a
series of homework problems. To make it more convenient to work with with this code, we
write a word u = (u1, u2), where u1 consists of the first 12 digits and u2 the remaining 12.
Since H = [I : B], we see that u 2 C if and only if Hu = 0, which is true if and only if u1 + Bu2
= 0. If we have a received word w, we perform the following steps to decode w. We write v for
the codeword to be determined from w. Finally, we write ei for the 12-tuple with i-entry 1 and
all other entries 0, and bi for the i-th row of bi.

1.Compute s = Hw. If s = 0, then w is a codeword.

2. If 1 _ wt(s) _ 3, then v = w + (s, 0).

3. If wt(s) > 3 and wt(s + bi) _ 2 for some i, then v = w + (s + bi, ei).

4. If we haven’t yet determined v, then compute Bs.

5. If 1 _ wt(Bs) _ 3, then v = w + (0,Bs).

6. If wt(Bs) > 3 and wt(Bs + bi) _ 2 for some i, then v = w + (ei,Bs + bi). 2.5. The Golay Code

7. If we haven’t determined v, then w cannot be decoded.

Example 2.5. Suppose that w = 001001001101101000101000 is received. We calculate
s = Hw, and we get s = 110001001001. We see that wt(s) = 5. We see that wt(s + b5) = 2.
36
Therefore, by Step 3, we decode w as v = w+(s+b5, e5) = w+(000000010010, 000010000000)
= 001001011111101010101000.

37
CHAPTER-5

RESULT AND
DISCUSSION
 CHAPTER-4
RESULT AND DISCUSSION

This chapter presents the expected results and the discussion in two stages. First section
presents the results of the irreversible signed and unsigned multiplier. And second section
presents the result of the proposed reversible signed and unsigned multiplier along with
comparison with existing methods.
All the designing and experiment regarding algorithm that we have mentioned in this thesis is
being developed on Xilinx 14.5i updated version. Xilinx 14.5i has couple of the striking
features such as low memory requirement, fast debugging, and low cost.
It is a hardware description language that can be used to describe the structure and/or behavior
of hardware designs and to model digital systems. VHDL is very adaptive, owing to its
architecture, allowing designers, electronic design automation companies and the
semiconductor industry to experiment with new language concepts to ensure good design tolls
and data interoperability.

Figure 5.1: Design Properties of Xilinx 14.5 virtex4 Device Family

52
 SYNTHESIS AND SIMULATION RESULT

In the following section, we have described the VHDL simulation of the proposed structure
 Golay Encoder
 Golay Decoder
Golay Encoder

Figure shows the Table of implementation result . it uses to consider the hardware
implementation

Figure 5.2 Hardware utilization of encoder

Simulation result in a model sim shows the step wise output with time . for Encode waveforms
of clock , reset,info,txcode ,clk period shown

53
 Figure 5.3 modelsim waveforms of Encoder

RTL Synthesis diadgram shows the gate level diagram

Figure5.4 RTL diagram of Encoder

54
Golay Decoder

Figure5.5 Hardware utilization of Decoder

Figure5.6 Model sim waveform of Decoder

55
Figure5.7 RTL diagram of Decoder

56
 CHAPTER-6
CONCLUSION
AND FUTURE
SCOPE
CHAPTER-5
CONCLUSION

Hardware architecture for extended binary Golay encoder and decoder for High speed
Implementation are designed and simulated in the proposed work. The results obtained from
the design synthesis for encoder and decoder supersedes the reference schemes in term of the
operational frequency. This makes the proposed design a good option to be used in the high
speed application based configurable circuits. In future there is a great scope to further
optimize the performance of the proposed algorithm. In future the scholars may undertake the
challenge to reduce the ratio of overhead bits versus data bits in the encoded codeword. Or the
researchers might increase the length of the data word that can be encoded using the same
algorithm with the same or better error detection and correction ability
Efficient hardware architecture for both binary Golay encoder and extended binary Golay coder
have been designed and implemented after verifying the proposed algorithm. The results
obtained from simulation state that the proposed hardware architecture for encoder supersedes
the conventional LFSR-based CRC generation schemes. Similarly, the proposed hardware
module for decoder shows better performance to some of the recent publications considering
various performance metrics. These hardware modules for encoder and
decoder can be a good candidate for various applications in highspeed communication links,
photo spectroscopy, and ultrasonography

FUTURE SCOPE

NASA deep space missions

The Voyager 1 and 2 spacecraft needed to transmit hundreds of color pictures
of Jupiter and Saturn in their 1979, 1980, and 1981 fly-by's within a constrained
telecommunications bandwidth.

Color image transmission required three times the amount of data as black and white images,
so the Hadamard code that was used to transmit the black and white images was switched to
the Golay (24,12,8) code. [8]

This Golay code is only triple-error correcting, but it could be transmitted at a much higher
data rate than the Hadamard code that was used during the Mariner mission.
Radio communications
The new American government standards for automati clink establishment in high
frequency radio systems specify the use of an extended (24,12) Golay block code for forward
error correction (FEC).

The Extended (24,12) Golay Code specified is a (24,12) block code.

This code encodes 12 data bits to produce 24-bit code words.

58
It is furthermore a systematic code, meaning that the 12 data bits are present in unchanged form
in the code word.
The minimum Hamming distance between any two code words (the number of bits by which
any pair of code words differs) is eight.

59
REFERENCES
 REFERENCE

[1] SatyabrataSarangi and Swapna Banerjee, “Efficient Hardware Implementation of

Encoder and Decoder for Golay Code”, IEEE Transaction on very large scale Integration
(VLSI) system, Vol.23 Issue No.9, pg.1965-1968, September 2015.

[2] Marcel J.E.Golay, “Notes on Digital Coding”, Reprinted from proc. IRE, Vol.37, pg-
657 June 1949.

[3] Jon Hamkins, “The Golay Code Outperforms the Extended Golay Code”, IEEE
Transactions on Information Theory, February 19, 2016.

[4] Faisal Alsaby, KholoodAlnoowaiser and SimonBerkovich, “Golay code

Transformation for ensemble clustering in application of medical Diagnostics”,
International Journal of Advanced Computer Science and Applications (IJACSA), Vol.6
No.1, pg.49-53, 2015.

[5] DongfuXie, “Simplified algorithm and hardware implementation for the (24,12,8)
Extended Golay soft Decoder up to 4 Errors”, The International Arab Journal of
Information Technology, Vol.11 No.2, pg.111-115, March 2014.

[6] Dr. Ravi Shankar Mishra, Prof PuranGour and Mohd. Abdullah, “Design and
Implementation of 4 bits Galois Encoder and Decoder in FPGA”, International Journal of
Engineering Science and Technology (IJEST), Vol.3 No.7, pg.5724-5732, July 2011.

[7] Yihua Chen, Juehsuan Hsiao, PangFu Liu and Kunfeng Lin, “Simulation and
Implementation of BPSK BPTC of MSK Golay code in DSP chip”, Communications in
Information Science and Management Engineering, Vol.1 No.4, pp.46-54, Nov.2011

[8] Eyas El-Qawasmeh, Maytham Safar and TalalKanan, “Investigation of Golay code
(24,12,8) Structure in improving search techniques”, The International Arab Journal of
Information Technology, Vol.8, No.3, pg.265-271, July 2011.

[9] Yan-Haw Chen, Chih-Hua Chine, Chine-Hsiang Huang, Trieu-Kien Truong And
Ming-Haw Jing, “Efficient Decoding of schematic (24,12,7) and (41,21,9) Quadric
Residue codes”, Journal of Information science And Engineering Vol.26, pg.1831-1843,
December 2010.

[10] Ali Pezeshki, A. Robert Calderbank, William Moran and Stephen D. Howard,
“Doppler Resilient Golay Complementary Waveforms”, IEEE Transaction on Information
Theory, Vol. 54, NO. 9, SEPTEMBER 2008.

[11] Xiao-Hong Peng and Paddy G. Farrell, “On Construction of the (24, 12, 8) Golay
Codes”, December 2005.
APPENDIX-I
APPENDIX-I

VHDL coding:-
Encoder coding
use IEEE.std_logic_arith.all;
use IEEE.numeric_bit.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity encoder is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
in1 : in STD_LOGIC_VECTOR (11 downto 0); -- "A27" msg
tx_code : out STD_LOGIC_VECTOR (23 downto 0);

tx_done : out std_logic

);
end encoder;

architecture Behavioral of encoder is

signal mult_b : std_logic_vector(11 downto 0) := "110111000101";

signal b_shift : std_logic_vector(11 downto 0):= "110111000101";
signal n : integer range 0 to 12 := 12 ;
signal tx1,rx1 : std_logic := '0';

begin

process(clk,rst)

begin
if(rst = '1') then
n <= 12 ;
mult_b <= "110111000101";
tx_code1 <= (others => '0');
tx1 <= '0';
elsif rising_edge(clk)then
if(n = 1)then
res(0) <= in1(11) xor in1(10) xor in1(9) xor in1(8) xor in1(7) xor in1(6) xor in1(5) xor
63
in1(4) xor in1(3) xor in1(2) xor in1(1);
mult_b <= "110111000101";
n <= 0;
elsif (n=0)then
tx_code1 <= res & in1 ;
tx1 <= '1';
else

mult_b(11 downto 1) <= mult_b(10 downto 1) & mult_b(11) ;

n <= n - 1;
end if;
end if ;
end process;

tx_done <= tx1;

tx_code <= tx_code1;

end Behavioral ;

Decoding Coding

library IEEE;

library work;
use work.pack1.all;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_bit.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity decoder is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
rx_code : in STD_LOGIC_VECTOR (23 downto 0);
rec_info : out std_logic_vector(11 downto 0);

64
 err_out : out std_logic_vector(23 downto 0);
synd1_out : out std_logic_vector(11 downto 0);
synd2_out : out std_logic_vector(11 downto 0);
done : out std_logic
);
end decoder;

architecture Behavioral of decoder is

signal mult_rx,b_shift : std_logic_vector(11 downto 0):= "110111000101";

signal rx_n : integer range 0 to 50 := 0 ;
signal sb1,sb2: std_logic_vector(11 downto 0):= (others => '0');
signal s_cnt,s_cnt2 : integer range 0 to 15 := 0;
signal rx1 : std_logic := '0';
signal rec_cnt : integer range 0 to 63 := 52;
signal err_pat : std_logic_vector(23 downto 0) := (others => '0');

begin

-- For Decoder circuit

-- calculate syndrom

process(clk,rst,rx_code)

begin
if(rst = '1')then
rx1 <= '0';
rx_n <= 12;
synd1 <= (others => '0');
synd2 <= (others => '0');
mult_rx <= "110111000101";
elsif rising_edge(clk)then
if( rx_n = 1)then
synd1(0) <= rx_code(12) xor rx_code(11) xor rx_code(10) xor rx_code(9) xor
rx_code(8) xor rx_code(7) xor rx_code(6) xor rx_code(5) xor rx_code(4) xor
rx_code(3) xor rx_code(2) xor rx_code(1);

rx_n <= 0;
elsif (rx_n=0)then
rx1 <= '1';
mult_rx <= "110111000101";
else
synd1(rx_n-1) <= (rx_code(rx_n+11) xor (rx_code(11) and mult_rx(11)) xor
(rx_code(10) and mult_rx(10)) xor (rx_code(9) and mult_rx(9)) xor (rx_code(8) and
and mult_rx(1)) xor (rx_code(0) and mult_rx(0)));
synd2(rx_n-1) <= (rx_code(rx_n-1) xor (rx_code(23) and mult_rx(11)) xor

65
(rx_code(22) and mult_rx(10)) xor (rx_code(21) and mult_rx(9)) xor (rx_code(20) and
mult_rx(8)) xor (rx_code(19) and mult_rx(7)) xor (rx_code(18) and mult_rx(6)) xor
(rx_code(17) and mult_rx(5)) xor (rx_code(16) and mult_rx(4))

rx_n <= rx_n - 1;

end if;
end if ;
end process;

-- Check weight and other steps

process(clk,rst,rx1,synd1,synd2,sb1,sb2,rec_cnt)
begin
if (rst = '1' or rx1 = '0')then
B_Shift <= "110111000101";
s_cnt <= 14;
elsif falling_edge(clk)then
if (rec_cnt = 0)then
s_cnt <= ones_cnt(synd1);
elsif (rec_cnt < 13) then
s_cnt <= ones_cnt(sb1);
B_Shift(11 downto 1) <= B_shift(10 downto 1) & B_shift(11);
elsif (rec_cnt = 13) then
B_Shift <= "110111000101";
elsif(rec_cnt = 14 ) then
s_cnt <= ones_cnt(synd2);
end if;
end if;
end process;

process(clk,rst,rx1,synd1,s_cnt)
begin
if (rst = '1' or rx1 = '0')then
recover_code <= (others =>'0');
rec_cnt <= 0;
done <= '0';
sb1 <= (others => '0');
sb2 <= (others => '0');
err_pat <= (others => '0');
elsif rising_edge(clk) then
if (rec_cnt = 0)then
if(s_cnt <= 3) then
rec_cnt <= 42;
err_pat(23 downto 12) <= synd1;
else
rec_cnt <= rec_cnt + 1;

66
 sb1 <= synd1 xor B_shift;
end if;

elsif(rec_cnt < 13) then -- 1,2,3,4,5,6,7,8,9,10,11,12

if(s_cnt <= 2) then
rec_cnt <= 43;
err_pat(23 downto 12) <= sb1;
err_pat(12-rec_cnt) <= '1';
else
if(rec_cnt = 11) then
sb1 <= not(synd1(11 downto 1)) & synd1(0);
else
sb1 <= synd1 xor B_shift;
end if;
rec_cnt <= rec_cnt + 1;
end if;

elsif(rec_cnt < 14) then -- 13

rec_cnt <= rec_cnt + 1;

elsif(rec_cnt < 15) then -- 14

-- s_cnt <= ones_cnt(synd2);
if(s_cnt <= 3) then
err_pat(11 downto 0) <= synd2;
rec_cnt <= 44;
else
rec_cnt <= rec_cnt + 1;
sb2 <= synd2 xor B_shift;
end if;
elsif (rec_cnt < 28) then -- 16,17,18,19,20,21,22,23,24,25,26,27
if(s_cnt <= 2) then
rec_cnt <= 45;
err_pat(11 downto 0) <= sb2;
err_pat(37-rec_cnt) <= '1';

end if;

else
recover_code <= rx_code xor err_pat;
rec_info <=recover_code(11 downto 0);
done <= '1';
rec_cnt <= 50;
end if;
end if;
end process;

err_out <= err_pat;

67
synd1_out <=synd1;
synd2_out <= synd2;
end Behavioral ;

68
APPENDIX-II
LIST OF PUBLICATION
[1] Amit Shrivastava and Mohd Abdullah, “High Speed Design Of FPGA Based Golay Encoder and
Decoder”, International Journal of Computer Applications (0975 – 8887) Volume 128, issue 11, Nov.-2016.
Amit Shrivastava
M. Tech Scholar
SISTec , Airport Road
Gandhi Nagar Bhopal
ABSTRACT
In wireless communication systems the most important issue to
be considered is the ability of the receiver to detect the errors
and correct them from the received information, so as to
provide correct information data to the processor. A number of
different methods are available to implement the hardware and
software with such preference. But, when the length of the
communication link becomes very long, i.e., the distance
between the wireless transmitter and receiver is very large, the
effect of noise on the transmitted signal may cause a change in
multiple bits of the transmitted information. This can cause
drastic loss in many cases. In this brief a Field Programmable
Gate Array (FPGA) based design and simulation of Golay Code
(G23) and Extended Golay Code (G24) Encoding scheme are
presented. This work is based on the optimization of the time
delay of the operational circuit to encode a data packet using the
Golay Encoder.
General Terms
Golay code, extended golay code, encoderAlgorithm, Decoder
algorithm, Xilinx ISE
Keywords
Encoder, Decoder, FPGA, Operational Delay
1. INTRODUCTION
Communication is important in our daily life. We use phones,
satellites, computers and other devices to send messages
through a channel to a receiver. Regrettably, most types of
communication are subject to noise, which may cause errors in
the messages that are being sent. Especially when sending
messages is a complicated or expensive task, for example in
satellite communication, it is important to find ways to
moderate the occurrence of errors as much as possible. This is
the central idea in coding theory: what we have received and
what message was being sent? To make this problem
uncomplicated we use error-correcting codes. The foremost
idea is to add redundancy to the messages which enables us to
both recognize and correct the errors that may have occurred.
This paper proposed a specific type of error-correcting codes,
the extended Golay code G24.The information is transfer in
three steps a source sends, a channel transmits, and a receiver
receives. There is an option that at the time of transmission the
information is altered to noise so to avoid this condition we use
error correction codes. Figure 1 show that a message is encoded
into a codeword, it is sent to the receiver through a channel, in
this channel the possibility exists that errors occur, and the
receiver tries to obtain the original message by decoding the
word.
International Journal of Computer Applications (0975 – 8887)
Volume 154 – No.10, November 2016
Mohd. Abdullah
Assistant Professor
SISTec, Airport Road
Gandhi Nagar Bhopal
Fig 1:Process of Error Correction Code
Golay code is an error correcting code which is used to
specifies that what we have received and what is send .some of
the most important properties of such codes which allows us to
give a detailed description of the extended Golay is :Firstly a
message m of length k is a sequence of k symbols out of some
k
finite field F, so m = (m1 : : :mk) belongs to F . Then an n-code
n
C over a finite field F is a set of vectors in F , where n ≤ k.
Since we will be commerce with a binary code only, we will
assume codes are binary from now on. Second property says
that the probability of error p is the probability that 1 is
received when 0 was sent, or 0 is received when 1 was sent.
Third property says that the hamming weight of a vector
n
belongs to a function F is the number of its non zero elements.
Fourth property says that the humming distance of two vectors
n
belongs to a function F is the number of place where they
n
differ. The idea is that an n-code C is a strict subset of F in
which we want the Hamming distance between any two vectors
to be as large as possible. Therefore, the min. Hamming
distance is an important characteristic of the code. Fifth
property says that the min. Hamming distance D of a code C is
defined as D = min {dist (X, Y) I X, Y belongs to C} where C
is the code. The description of work in this paper is as follows:
Section-II gives an overview on the work performed by other
scholars in Golay Code implementation and applications.
Introduction on Golay code and its encoding algorithm is
described in Section-III. Section-IV presents the simulation and
synthesis results of the performed work. The conclusion based
on the proposed work and the future work scope is presented in
Section-V. In the last the references arementioned.
2. LITERATURE REVIEW
In reference [1] the proposed paper addresses error correcting
phenomena using Golay code encoder. . A brief introduction
and explanation of Golay coding scheme is presented in [3]. 4-
bit Golay Encoder and Decoder design and implementation
Based on FPGA is simulated in [4] using Xilinx ISE and
Models in Tools. Reference [5] presents a soft algorithm based
decoding orientation to hardware implementation of
36
 International Journal of Computer Applications (0975 – 8887) Volume 154 – No.10,
November 2016

(24, 12, 8) Golay code with implementation of the algorithm 3. GENERATOR AND PARITY MATRIX
on FPGA. In [6] it is shown that the (24, 12, 8) Golay code is
to be designed as a direct sum of two array codes that involve
OF(24,12) GOLAY CODE
four component codes from which two are simple block codes A binary Golay code is represented by (23, 12, 7), In which
Which are linear (repetition code and SPC code). Construction the distance between two binary Golay codes is Represented
of Golay Code Complementary Sequences is presented in [7] by 7 and 12-bits is of massage bits and codeword is 23 bits
for application of Golay Coding in the fields of physics, long. It is necessary to construct binary codes in a Galois
combinatory (orthogonal design and Hadmard matrices), Field (GF). Binary field is denoted by GF(2), which supports
surface acoustics and tele-communication. A better algorithm different binary arithmetic operations.
for decoding Golay Code is presented in [8] which uses one- The extended (24, 12) binary Golay code [1] which presents
to-one mapping between the syndrome “S1” and error patterns in this paper can correct three and less than three errors. With
which can be corrected. In this proposed work the algorithm the help of the 11 x 11 Bc Matrix.. Because of Bc Which has
determines the error locations by using look-up tables without the Property Of cyclic structure and also it is the component
the multiplication operation over a finite field. This algorithm of both generator and the parity check matrices its procedure
has been verified by the scholars on a C-language based of decoding is very easy.
software simulation platform. The work presented in [9]
focuses on Golay code decoding using soft-in/soft-out and Genrator and Parity Matrix Of Golay Code
symbol by symbol APP (a posteriori probability) algorithm
b1
through co-set based technique. A study based on discussion
on the error correction capability of MSK modulation with
b2
Golay code and BPSK modulation with Golay code is
presented in [10], which concludes that Minimum Shift
Bc = b3
Keying Golay code is comparatively more robust. A technique
based upon reversing the conventional scheme of Golay code
b4
(24, 12, 8) that maps 24-bit vectors into 12-bit message words
is proposed in [11] to improve the search operation when
b5
multi-attribute objects are partially distorted. The work in [12]
presents generation of Doppler Resilient waveforms using
b6
Golay Complementary sequence which have ideal ambiguity
along the zero Doppler axis but are sensitive to non-zero
b7
Doppler shifts. The work in [13] showa Golay code
transformation used for Ensemble Clustering that is usufull in
b8
application to Medical purposes. This method of cluster is
unique to all other techniques because of its linear time
b9
complexity. Reference [14] presents an error correction Golay
code for clustering large amount of data Streams with thw use
b10
of error correction Golay codes and this approach is used in
the field where the requirement to accumulate
b11
multidimensional data. In Reference [15] the proposed
methodology fulfill the requirement reducing the peak to
average ratio (PTAR) with the help of special Fractional Let Bc be 11*11 Matrix over Galois Fiels GF Where
Fourier Transform (FRFT) followed to the low complicity
Golay sequence coder in order to provide optimal de- b1 = 1,1,0,1,1,1,0,0,0,1,0
correlation between signal and noise. To achieve the
requirement of low complexity, low bit error rate and ratio of b2 is Obtained From b1 By Shifting Cyclically the
peak to average power. Reference [16] presents an Sequence b1 one Position to the Left, the Third row in Bc is
Methedology for the implementation of Hardware of (24, 12, Obtain in the same way,and so on.
8) Golay code in FPGA (Field programmable gate array)
system. For removing the complexity of arithmetic operations
this arises in the existing algorithm. The proposed algorithm
chooses the absolute value rather than bit error probability to
obtained better results as compared to the existing algorithms.
Reference [17] proposes a new algorithm to fulfill the
requirement of faster decoding for the Gosset Lattice, Golay
code and Leech Lattice. The proposed design introduced two
approaches to first when charge in of length n and taking soft
n
decoding algorithm at an arbitrary point R in to the nearest
code word and second a decoding algorithm for a lattice A in
n n
R changesan arbitral point of R into a closest lattice
point.Reference [18]proposedan efficient soft-decision
decoder of the (23, 12, 7) binary Golay code up to the four
errors and almost all patterns of three errors and all fewer
random error can be corrected with the help of proposed
algorithm.

The (24, 12) Golay code has the generator and parity
check matrices as Follows.
 International Journal of Computer Applications (0975 – 8887)
Volume 154 – No.10, November 2016

, ,
where I - identity matrix 12 x 12,

and

.
It can be seen that ,,
Therefore

4. ENCODING AND DECODING OF

(24,12) GOLAY CODE

Same in the case of any linear code, to generate a code vector it nessesary to multiply the vector i, which is having 12 information
bits.

i=[
by the matrix: G

Wherefrom
 International Journal of Computer Applications (0975 – 8887)
Volume 154 – No.10, November 2016

For decoding of the extended Golay code, shown below,need

to determine the error patternu = v + w,
where w is vector received and v the nearest w code vector.
wt(x) represents the weight of the vector x, ( the number of
"ones" presents in x),
bi- Is the i-th row of the matrix B,
ei- Is the word having length 12 and 1 in the i-th position and
zero elsewhere. After calculating u Let we assume that the
received vector which is corrected will be v = w + u.. the steps
of the algorithm are as follows:

Step 1. Determine the syndrome(S)

Step 2. If
U = [S, 000000000000].

Step 3. If

then U = S+bi ,ei

Step 4. Determine the second syndrome(SB)

Step 5. If then

U = [000000000000, SB].
Fig:2 RTL Schematic Diagram of Proposed Golay Code
(24, 12, 8) Encoder

Step 6. If For some bi of B then U = [ ei,SB+bi ].

Step 7. Retransmit the signal if U is not determine

5. SIMULATION AND SYNTHESIS RESULTS

The present work is simulated using Xilinx. The RTL Schematic diagrams of Encoder and Decoder designs are shown in Fig 2 and Fig
3 respectively.
 International Journal of Computer Applications (0975 –
8887) Volume 154 – No.10, November 2016

Table 1.Hardware Utilization Summary of Encoder

Vertex-IV 12-bit Golay Encoder
XC4VLX160 Total
-12FF1148 Used %
Slices 67584 40 0
Flipflops 135168 53 0
LUTs 4-
135168 72 0
Inputs

Bonded IOBs 768 39 5

Table 2.Hardware Utilization Summary of Decoder

Vertex-IV 12-bit Golay Decoder
XC4VLX160 Total
-12FF1148 Used %
Slices 67584 196 0
Flipflops 135168 151 0
LUTs 4-
135168 367 0
Inputs

Bonded IOBs 768 87 11

Table-III represents a comparative analysis of the delay based

results of the proposed work with some existing works.
Table 3.Comparison of Dynamic Power Consumption of Proposed Design
Operational Frequency (MHz)
Work
Encoder Decoder
Proposed 333.206 89.123
[1] 238.575 80
Fig :3 RTL Schematic of Proposed Golay Code (24, 12, 8)
Decoder -

The Encoder and Decoder simulation waveforms are shown in

Fig4 and Fig 5 respectively. A 12-bit data is used to encode
using the proposed encoder.. The FPGA based hardware
utilization summary of the proposed Encoder and Decoder
designs is presented in Table-I and Table-II respectively.

Fig 4 Encoder Simulation Waveform for Proposed Golay Code (24, 12, 8)
 International Journal of Computer Applications (0975 – 8887)
Volume 154 – No.10, November 2016
Fig5: : Decoder Simulation Waveform for Proposed Golay Code (24, 12, 8)
6. CONCLUSION
Hardware architecture for extended binary Golay
encoder and decoder for High speed
Implementation are designed and simulated in the
proposed work. The results obtained from the
design synthesis for encoder and decoder
supersedes the reference schemes in term of the
operational frequency. This makes the proposed
design a good option to be used in the high speed
application based configurable circuits. In future
there is a great scope to further optimize the
performance of the proposed algorithm. In future
the scholars may undertake the challenge to
reduce the ratio of overhead bits versus data bits
in the encoded codeword. Or the researchers
might increase the length of the data word that can
be encoded using the same algorithm with the
same or better error detection and correction
ability.
7. ACKNOWLEDGMENTS
The authors thank Mr. Rakesh Gumasta
(Navigator Technology, Bhopal India) for sharing
his ideas in writing this paper.
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 PLAGIARISM REPORT

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