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Question Paper Code: 10662

B.E DEGREE INTERNAL EXAMINATIONS, APRIL 2022

INTERNAL ASSESSMENT TEST-1
Sixth Semester
Department of Electronics and Communication Engineering
EC 8095 VLSI DESIGN
Time: 2 Hours Maximum marks: 70
Answer ALL questions

Q.N PART - A (10x2=20 marks)

CO K
o
1 Define Logical Effort. CO1 K1
2 What is channel length modulation? CO1 K1
Define Moore’s Law CO1
3 K1
4 Define Noise Margin. CO1 K1
5 Infer body effect. CO1 K2
6 What is Critical path? CO2 K1
7 Infer bubble pushing. CO2 K2
8 Define Ratioed Circuits. CO2 K1

Q.No PART - B (5x13=65 marks)

CO K
9(a) Inspect the following:
i) CMOS process enhancements (8) CO1 K4
ii) Layout design rules. (5)
Or
(b) Examine and derive the DC Transfer characteristics of CMOS inverter for the
CO1 K4
various regions of operation. (13)
10(a) Compare the scaling techniques which improves the circuit performance (13) CO1 K3
Or
(b) Develop three Capacitance and Voltage characteristics models for a MOS
CO1 K3
transistor. (13)
11(a) Contrast asymmetric and skewed gates used for Static CMOS optimization
process CO2 K4
(13)
 Or
(b) Analyze pseudo nMOS and Ganged CMOS Logic for designing Ratioed Circuits. CO2
K4
(13)

Q.No PART - C (1x15=15 marks) CO K

12(a) Determine CMOS Logic for the following equations.
(i) Y=( A . B )+ ( A . C )+(B . D) (7) CO1 K5
(ii) Y=( A . B )+(C . D) (8)
Or
(b) Determine the delay using RC Delay and Linear delay model.
CO1 K5
(15)

Staff In-Charge HOD/ECE