B.

E DEGREE INTERNAL EXAMINATIONS, APRIL 2022

INTERNAL ASSESSMENT TEST-1
Department of Electronics and Communication Engineering
EC 8095 VLSI DESIGN
Time: 2 Hours Maximum marks: 70
Answer ALL questions
PART - A (8x2=16 marks)
1. Define Logical Effort
Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter
delivering the same output current.
2. What is channel length modulation?
Channel length modulation (CLM) is a shortening of the length of the
inverted channel region with increase in drain bias for large drain biases. The result of CLM is an
increase in current with drain bias and a reduction of output resistance.
3. Define Moore’s Law
Gordon Moore found that transistor count doubles for every 18 months . This observation is called
as Moore’s Law.
4. Define Noise Margin.
Noise margin is a measure of design margins to ensure circuits functioning properly within
specified conditions.
NML = |VIL max – VOL max|
 NMH = |VOH min – VIH min|
5. What is body effect?
Body effect refers to the change in the threshold voltage of the device when there is a difference
between substrate(body) and source voltages.
6. What is Critical path?
The critical path is defined as the path between an input and an output with the maximum delay.
Once the circuit timing has been computed by one of the techniques listed below, the critical
path can easily be found by using a traceback method.
7. Infer bubble pushing.
 Change the logic gate (AND to OR and OR to AND).
 Add bubbles to the inputs and outputs where there were none, and remove the original bubbles.
8. Define Ratioed Circuits.
Ratioed circuits use weak pull-up and stronger pull-down networks. ... Ratioed circuits dissipate
static power and must be used sparingly. The pull-up network for ratioed CMOS (pseudo-nMOS)
uses a single pMOS. whose gate terminal is grounded (device is always on).

PART - B (3*13=39 marks)

9. Inspect the following:
i) CMOS process enhancements (8)
 manufacturing of an IC (8)
ii) Layout design rules. (5)
  Micron Rules (3)
 Lambda Rules (2)
(or)
(b). Examine and derive the DC Transfer characteristics of CMOS inverter for the various regions
of operation. (13)
 Circuit (1 mark)
 Conditions (1 mark)
 Different regions and its behavior (10 marks)
 DC curve (2 marks)

10. (a) Compare the scaling techniques which improves the circuit performance. (13)
 Introduction ( 2 marks)
 Constant field scaling ( 3 marks)
 Constant voltage scaling ( 3 marks)
 Limits of scaling ( 5 marks)
b. Develop three Capacitance and Voltage characteristics models for a MOS transistor.
(13)
 Simple MOS capacitance Model (5 marks)
 Detailed MOS Gate capacitance model (4 marks)
 Detailed MOS diffusion capacitance model (5 marks)

11. (a)Contrast asymmetric and skewed gates used for Static CMOS optimization process. (13)
 Asymmetric gates (6)
 skewed gates (7) (or)
(b) Analyze pseudo nMOS and Ganged CMOS Logic for designing Ratioed Circuits. (13)

 pseudo nMOS (6)

 Ganged CMOS (7)
PART - C (1x15=15 marks)
12. Determine CMOS Logic for the following equations.
(i) Y=( A . B )+ ( A . C )+( B . D) (7)
 Realization using NMOS,PMOS (3)
 Realization Using CMOS Logic(4)
(ii) Y=( A . B )+(C . D) (8)
 Realization using NMOS,PMOS (4)
 Realization Using CMOS Logic(4)
(or)
(b) Determine the delay using RC Delay and Linear delay model. (15)
 Logical Effort , RC delay(8)
 Linear delay(7)

Subject In charge Verified By HOD/ECE